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Change in ...coreboot[master]: mb/google/sarien: Enable MAC address passthru support
by Duncan Laurie (Code Review) 04 Mar '19

04 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31670 Change subject: mb/google/sarien: Enable MAC address passthru support ...................................................................... mb/google/sarien: Enable MAC address passthru support Enable the support for proving a MAC address for a dock to use based on the VPD values set in the platform. BUG=b:123925776 TEST=tested on sarien by setting VPD values and observing the string returned by the AMAC() method: > vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA" > vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB" 1) Test with no policy set, returns "dock_mac" ACPI Debug: "VPD region RW did not verify" ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB" ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB" ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#" 2) Test with policy set to "builtin", returns nothing > vpd -i RW_VPD -s "dock_passthru"="builtin" ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero] 3) Test with policy set to "ethernet_mac0" > vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0" ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0" ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA" ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA" ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#" 4) Test with policy set to "dock_mac" > vpd -i RW_VPD -s "dock_passthru"="dock_mac" ACPI Debug: "Found VPD KEY dock_passthru = dock_mac" ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB" ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB" ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#" Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31670/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 547253f..642e240 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -45,6 +45,10 @@ #if IS_ENABLED(CONFIG_CHROMEOS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> + /* VPD support */ + #include <vendorcode/google/chromeos/acpi/vpd.asl> + /* MAC address passthru */ + #include <vendorcode/google/chromeos/acpi/amac.asl> #endif /* Chipset specific sleep states */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54 Gerrit-Change-Number: 31670 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/google/chromeos: Support MAC address passthru policy
by Duncan Laurie (Code Review) 04 Mar '19

04 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31669 Change subject: vendorcode/google/chromeos: Support MAC address passthru policy ...................................................................... vendorcode/google/chromeos: Support MAC address passthru policy This change adds support for providing a MAC address that can be used by the OS network drivers to change the MAC address that a NIC uses. The Realtek r8152 driver in the Linux kernel supports a MAC address passthru feature which can result in the dock ethernet port using the same MAC address that is assigned to the internal NIC. This is done by calling an ACPI method at \_SB.AMAC() which returns a formatted string containing the MAC address for the dock to use. The Linux kernel implementation can be found at drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() This is implemented specifically for Chrome OS as it relies on VPD to determine the MAC address to supply. The policy which controls where the dock MAC address comes from is written into RW_VPD property "dock_passthru": "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" "ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0" "builtin": existing dock MAC address (return nothing) The MAC address in VPD is the standard format AA:BB:CC:DD:EE:FF and it must be converted into the string format expected by the OS which involves some string manipulation which ACPI is not great at handling. BUG=b:123925776 TEST=this was tested on a sarien board by setting the VPD keys to their expected values and observing if the AMAC() method returns the expected string. Change-Id: I3335e5d924155431e299844e2aaace62168294e0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/vendorcode/google/chromeos/acpi/amac.asl 1 file changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/31669/1 diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl new file mode 100644 index 0000000..07a0518 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The Realtek r8152 driver in the Linux kernel supports a MAC address + * passthru feature which can result in the dock ethernet port using the + * same MAC address that is assigned to the internal NIC. This is done + * by calling an ACPI method at \_SB.AMAC() which returns a formatted + * string containing the MAC address for the dock to use. + * + * The Linux kernel implementation can be found at + * drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read() + * + * For Chrome OS, the policy which controls where the dock MAC address + * comes from is written into RW_VPD property "dock_passthru": + * + * "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac" + * "ethernet_mac0": Use MAC address from RO_VPD value "ethernet_mac0" + * "builtin": existing dock MAC address (return nothing) + */ + +Scope (\_SB) +{ + Method (AMAC, 0, Serialized) + { + /* Format expected by the Linux kernel r8152 driver */ + Name (MACA, "_AUXMAC_#XXXXXXXXXXXX#") + + /* Get "dock_passthru" value from RW_VPD */ + Local0 = \VPD.VPDF ("RW", "dock_passthru") + + Switch (ToString (Local0)) + { + Case ("ethernet_mac0") { + Local1 = \VPD.VPDF ("RO", "ethernet_mac0") + } + Case ("builtin") { + Return (Zero) + } + /* "dock_mac" or policy not found. */ + Default { + Local1 = \VPD.VPDF ("RO", "dock_mac") + } + } + If (!Local1) { + Return (Zero) + } + Printf ("MAC address returned from VPD: %o", Local1) + + /* Verify MAC address format is AA:BB:CC:DD:EE:FF */ + For (Local3 = 2, Local3 < 17, Local3+=3) { + If (ToString (DeRefOf (Local1[Local3])) != ":") { + Printf ("Invalid MAC address byte %o", Local3) + Return (Zero) + } + } + + /* Convert MAC address into format specified by MACA */ + Local2 = ToBuffer (MACA) + Local4 = 0 /* First MAC address byte in input buffer */ + Local5 = 9 /* First MAC address byte in output buffer */ + For (Local3 = 0, Local3 < 6, Local3++) { + Local2[Local5] = DeRefOf (Local1[Local4]) + Local2[Local5 + 1] = DeRefOf (Local1[Local4 + 1]) + Local5 += 2 + Local4 += 3 /* Skip ":" in address from VPD */ + } + + Printf ("AMAC = %o", ToString (Local2)) + Return (ToString (Local2)) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3335e5d924155431e299844e2aaace62168294e0 Gerrit-Change-Number: 31669 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/google/chromeos: Add support for reading VPD in ACPI
by Duncan Laurie (Code Review) 04 Mar '19

04 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31668 Change subject: vendorcode/google/chromeos: Add support for reading VPD in ACPI ...................................................................... vendorcode/google/chromeos: Add support for reading VPD in ACPI This ACPI device presents an interface that allows other ACPI devices or methods to read VPD strings. The VPDF() method is provided the VPD partition to look in, and the name of the VPD key to find and it will return the VPD string if it exists. For example: VPD.VPDF ("RO", "serial_number") BUG=b:123925776 TEST=this was tested on a sarien platform by adding ACPI code that searches for a VPD key and returns the value it finds, and then setting that VPD string from the OS with the Chrome OS 'vpd' utility to ensure the ACPI method returns the correct value. Change-Id: I4668f66d7f7f364ac8c3b064d406b24135abb0f6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/vendorcode/google/chromeos/acpi/vpd.asl 1 file changed, 226 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31668/1 diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl new file mode 100644 index 0000000..bd77cb7 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This device provides an ACPI interface to read VPD keys from either + * the RO_VPD or RW_VPD region. For example: + * + * VPD.VPDF ("RO", "ro_key_name") + * VPD.VPDF ("RW", "rw_key_name") + */ + +Device (VPD) +{ + Name (_HID, "GOOG000F") + Name (_UID, 1) + Name (_STA, 0xf) + + Name (VOFS, 0x600) /* Start of VPD header in VPD region */ + Name (VIHL, 0x10) /* Length of VPD info header */ + Name (VPET, 0x00) /* VPD Entry Type: Terminator */ + Name (VPES, 0x01) /* VPD Entry Type: String */ + Name (VPEI, 0xfe) /* VPD Entry Type: Info (header) */ + Name (MORE, 0x80) /* Bit to indicate more length bytes */ + + Name (VPTR, Zero) /* Pointer to current byte in VPD for parser */ + Name (VEND, Zero) /* End of VPD region */ + + /* + * VLOC() - Return location and length of VPD region in memory. + * These values must be initialized in GNVS by coreboot. + * + * Returns: Package indicating start and length of region: + * [0] = Address of the start of VPD region. + * [1] = Length of the VPD region. + */ + Method (VLOC, 1, Serialized) + { + Switch (ToString (Arg0)) + { + Case ("RO") { + Return (Package () { \ROVP, \ROVL }) + } + Case ("RW") { + Return (Package () { \RWVP, \RWVL }) + } + Default { + Return (Package () { Zero, Zero }) + } + } + } + + /* + * VVPD() - Verify VPD info header. + * Arg0: VPD partition base address. + * Returns: VPD length or Zero if VPD header is not valid. + */ + Method (VVPD, 1, Serialized) + { + Local0 = Arg0 + ^VOFS + + OperationRegion (VPDH, SystemMemory, Local0, ^VIHL) + Field (VPDH, DWordAcc, NoLock, Preserve) + { + TYPE, 8, /* VPD Header Tag (=0xfe) */ + KLEN, 8, /* Key length (=9) */ + IVER, 8, /* Info version (=1) */ + SIGN, 64, /* Signature (="gVpdInfo") */ + VLEN, 8, /* Value length (=4) */ + SIZE, 32, /* VPD length */ + } + + If (TYPE != ^VPEI) { + Return (Zero) + } + If (KLEN != 9) { + Return (Zero) + } + If (IVER != 1) { + Return (Zero) + } + If (ToString (SIGN) != "gVpdInfo") { + Return (Zero) + } + If (VLEN != 4) { + Return (Zero) + } + + Return (SIZE) + } + + /* Return next byte from VPD at pointer VPTR, and increment VPTR. */ + Method (VPRB, 0, Serialized) + { + If (^VPTR > ^VEND) { + Printf ("Access beyond end of VPD region") + Return (Zero) + } + + Local0 = ^VPTR + OperationRegion (VPDR, SystemMemory, Local0, One) + Field (VPDR, DWordAcc, NoLock, Preserve) + { + BYTE, 8, + } + + /* Increment address pointer */ + ^VPTR++ + Return (BYTE) + } + + /* Extract and return next string from VPD. */ + Method (VPDE, 0, Serialized) + { + Local0 = One /* Indicates if there are more bytes */ + Local1 = Zero /* Length */ + + /* Decode the string length */ + While (Local0) { + /* Read the next byte at indicated address */ + Local2 = ^VPRB () + + /* Update the more bit from the byte in Local2 */ + Local0 = Local2 >> 7 + + /* Save the length bits from Local2 */ + Local1 <<= 7 + Local1 |= Local2 & 0x7f + } + If (!Local1) { + Return (Zero) + } + + /* Extract the string */ + Local3 = Zero + Local4 = "" + While (Local3 < Local1) { + Concatenate (Local4, ToString (^VPRB ()), Local4) + Local3++ + } + + Return (Local4) + } + + /* + * VPDS() - Find next VPD key and value. + * Returns: Package containing key and value: + * [0] = VPD key string + * [1] = VPD value string + */ + Method (VPDS, 0, Serialized) + { + Name (VPKV, Package () { Zero, Zero }) + + /* Read the VPD type and ensure it is a string */ + If (^VPRB () != ^VPES) { + Printf ("VPDS: Type is not a string") + Return (VPKV) + } + + /* Extract the key string and value */ + VPKV[0] = VPDE () + VPKV[1] = VPDE () + + Return (VPKV) + } + + /* + * VPDF() - Find VPD key with matching name. + * Arg0: VPD Partition, either "RO" or "RW". + * Arg1: VPD key name to search for. + * Returns: VPD string corresponding to VPD key, or Zero if not found. + */ + Method (VPDF, 2, Serialized) + { + Local0 = VLOC (Arg0) + + /* Start of VPD region */ + ^VPTR = DeRefOf (Local0[0]) + + /* End address of VPD region */ + ^VEND = ^VPTR + DeRefOf (Local0[1]) + + If (!^VPTR || !^VEND) { + Printf ("Unable to find VPD region") + Return (Zero) + } + + /* Verify VPD info header and save size */ + Local0 = VVPD (^VPTR) + If (!Local0) { + Printf ("VPD region %o did not verify", Arg0) + Return (Zero) + } + + /* Set VPD pointer to start of VPD entries */ + ^VPTR += ^VOFS + ^VIHL + + /* Search through VPD entries until key is found */ + Local1 = "" + While (Local1 != ToString (Arg1)) { + Local2 = VPDS () + Local1 = DeRefOf (Local2[0]) + If (!Local1) { + Printf ("VPD KEY %o not found", Arg1) + Return (Zero) + } + } + Local3 = DeRefOf (Local2[1]) + + Printf ("Found VPD KEY %o = %o", Local1, Local3) + Return (Local3) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4668f66d7f7f364ac8c3b064d406b24135abb0f6 Gerrit-Change-Number: 31668 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/google/chromeos: Save VPD region into GNVS
by Duncan Laurie (Code Review) 04 Mar '19

04 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31667 Change subject: vendorcode/google/chromeos: Save VPD region into GNVS ...................................................................... vendorcode/google/chromeos: Save VPD region into GNVS Store the memory address of VPD region start and length for the memory mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code. BUG=b:123925776 TEST=boot on sarien and verify VPD start/length in GNVS Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/acpi/gnvs.asl M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h 3 files changed, 38 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31667/1 diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 52d3a0d..69e848a 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -32,4 +32,8 @@ MEHH, 256, // 0xd9e - Management Engine Hash RMOB, 32, // 0xdbe - RAM oops base address RMOL, 32, // 0xdc2 - RAM oops length - // 0xdc6 +ROVP, 32, // 0xdc6 - pointer to RO_VPD +ROVL, 32, // 0xdca - size of RO_VPD +RWVP, 32, // 0xdce - pointer to RW_VPD +RWVL, 32, // 0xdd2 - size of RW_VPD + // 0xdd6 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 86ba4f3..44162c8 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -20,6 +20,7 @@ #include <cbmem.h> #include <console/console.h> #include <elog.h> +#include <fmap.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> #include <vboot_struct.h> @@ -30,14 +31,41 @@ static chromeos_acpi_t *chromeos_acpi; static u32 me_hash_saved[8]; +static size_t chromeos_vpd_region(const char *region, uintptr_t *base) +{ + struct region_device vpd; + + if (fmap_locate_area_as_rdev(region, &vpd)) + return 0; + + *base = (uintptr_t)rdev_mmap_full(&vpd); + + return region_device_sz(&vpd); +} + void chromeos_init_chromeos_acpi(chromeos_acpi_t *init) { + size_t vpd_size; + uintptr_t vpd_base = 0; + chromeos_acpi = init; /* Copy saved ME hash into NVS */ memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh)); chromeos_ram_oops_init(chromeos_acpi); + + vpd_size = chromeos_vpd_region("RO_VPD", &vpd_base); + if (vpd_size && vpd_base) { + chromeos_acpi->vpd_ro_base = vpd_base; + chromeos_acpi->vpd_ro_size = vpd_size; + } + + vpd_size = chromeos_vpd_region("RW_VPD", &vpd_base); + if (vpd_size && vpd_base) { + chromeos_acpi->vpd_rw_base = vpd_base; + chromeos_acpi->vpd_rw_size = vpd_size; + } } void chromeos_set_me_hash(u32 *hash, int len) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 76ca20c..b114dd0 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -70,7 +70,11 @@ u32 mehh[8]; // d9e management engine hash u32 ramoops_base; // dbe ramoops base address u32 ramoops_len; // dc2 ramoops length - u8 pad[314]; // dc6-eff + u32 vpd_ro_base; // dc6 pointer to RO_VPD + u32 vpd_ro_size; // dca size of RO_VPD + u32 vpd_rw_base; // dce pointer to RW_VPD + u32 vpd_rw_size; // dd2 size of RW_VPD + u8 pad[298]; // dd6-eff } __packed chromeos_acpi_t; void chromeos_init_chromeos_acpi(chromeos_acpi_t *init); -- To view, visit https://review.coreboot.org/c/coreboot/+/31667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf Gerrit-Change-Number: 31667 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Move common definitions to a header file
by Rizwan Qureshi (Code Review) 04 Mar '19

04 Mar '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31621 Change subject: soc/intel/cannonlake: Move common definitions to a header file ...................................................................... soc/intel/cannonlake: Move common definitions to a header file Move common definitions for PCH H and LP to a common header. Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- A src/soc/intel/cannonlake/include/soc/gpio_common.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h 3 files changed, 27 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31621/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h new file mode 100644 index 0000000..722637d --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpio_common.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ +#define _SOC_CANNONLAKE_GPIO_COMMON_H_ +#define GPIORXSTATE_MASK 0x1 +#define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 +#define GPIOPADMODE_MASK 0xC00 +#define GPIOPADMODE_SHIFT 10 +#define GPIOTXBUFDIS_MASK 0x100 +#define GPIORXBUFDIS_MASK 0x200 + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 3399526..8a944b1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -19,9 +19,9 @@ #ifndef __ACPI__ #include <stddef.h> #endif +#include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h> - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ @@ -250,13 +250,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIOTXBUFDIS_SHIFT 8 -#define GPIORXBUFDIS_MASK 0x200 -#define GPIORXBUFDIS_SHIFT 9 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index c7f3c81..e77dbf8 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -19,9 +19,9 @@ #ifndef __ACPI__ #include <stddef.h> #endif +#include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h> - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ @@ -324,13 +324,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIOTXBUFDIS_SHIFT 8 -#define GPIORXBUFDIS_MASK 0x200 -#define GPIORXBUFDIS_SHIFT 9 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127 Gerrit-Change-Number: 31621 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cnl/acpi: add ish ACPI device
by Jett Rink (Code Review) 04 Mar '19

04 Mar '19

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31681 Change subject: soc/intel/cnl/acpi: add ish ACPI device ...................................................................... soc/intel/cnl/acpi: add ish ACPI device Create the ISH ACPI device so we can hang fields off of a _DSD table. Since this is also a PCI device that has run time probing, we can always emit the ACPI device and let the device tree true the device on or off. BRANCH=none BUG=b:122722008 TEST=verify that _DSD table gets publish under ISH device in kernel ACPI tables. Also verified that device is still turned off if device tree for ISH is off. Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- A src/soc/intel/cannonlake/acpi/ish.asl M src/soc/intel/cannonlake/acpi/southbridge.asl 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31681/1 diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl new file mode 100644 index 0000000..8a724d3 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/ish.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel Integrated Sensor Hub Controller 0:13.0 */ + +Device (ISHB) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Integrated Sensor Hub Controller") +} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index dfa2975..ae8de6a 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -51,6 +51,9 @@ /* SMBus 0:1f.4 */ #include "smbus.asl" +/* ISH 0:13.0 */ +#include "ish.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/31681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2 Gerrit-Change-Number: 31681 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix DSDT compile remarks
by Patrick Georgi (Code Review) 04 Mar '19

04 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31666 ) Change subject: soc/intel/cannonlake: Fix DSDT compile remarks ...................................................................... soc/intel/cannonlake: Fix DSDT compile remarks The following remarks show up during cannonlake based platform coreboot build: dsdt.asl 55: Offset (0x00), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 136: Offset (0xa8), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Address those two remarks in coreboot. BUG=N/A TEST=Build coreboot and check build log to see no more remark. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Reviewed-on: https://review.coreboot.org/c/31666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/acpi/globalnvs.asl M src/soc/intel/cannonlake/acpi/northbridge.asl 2 files changed, 3 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, but someone else must approve Bora Guvendik: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl index ac60b36..940cf43 100644 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ b/src/soc/intel/cannonlake/acpi/globalnvs.asl @@ -32,7 +32,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 68ab059..7fb4c09 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -54,11 +54,9 @@ , 11, DIBR, 20, /* DMIBAR [31:12] */ - Offset (0xa0), /* Top of Used Memory */ - TOM, 64, - - Offset (0xa8), /* Top of Upper Used Memory */ - TUUD, 64, + Offset (0xa0), + TOM, 64, /* Top of Used Memory */ + TUUD, 64, /* Top of Upper Used Memory */ Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, -- To view, visit https://review.coreboot.org/c/coreboot/+/31666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Gerrit-Change-Number: 31666 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Werner Zeh (Code Review) 04 Mar '19

04 Mar '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 61: Code-Review+1 (5 comments) https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi.h@29 PS61, Line 29: * not needed https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi.h@30 PS61, Line 30: ram RAM? https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi.h@56 PS61, Line 56: set's sets https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi/log.c@109 PS61, Line 109: or digest type You only check for name here, so maybe this will be missleading someday? https://review.coreboot.org/#/c/29563/61/src/security/tpm/tspi/log.c@145 PS61, Line 145: ram RAM? -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 61 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 13:58:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/i82801gx: Remove unnecessary/redundant use of ACPI offset op...
by HAOUAS Elyes (Code Review) 04 Mar '19

04 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31672 Change subject: sb/intel/i82801gx: Remove unnecessary/redundant use of ACPI offset operator ...................................................................... sb/intel/i82801gx: Remove unnecessary/redundant use of ACPI offset operator Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/acpi/ich7.asl 2 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31672/1 diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 33472b6..3e2b3b0 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -30,7 +30,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter @@ -48,7 +47,6 @@ LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ - Offset (0x14), ACTT, 8, // 0x14 - active trip point TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 @@ -87,7 +85,6 @@ UTIL, 8, // 0x3a - ACIN, 8, // 0x3b - /* Integrated Graphics Device */ - Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 38ca483..1086e0f 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -43,12 +43,12 @@ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select + // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, GU03, 8, - Offset(0x04), // GPIO IO Select + // GPIO IO Select GIO0, 8, GIO1, 8, GIO2, 8, @@ -96,17 +96,17 @@ GIV1, 8, GIV2, 8, GIV3, 8, - Offset(0x30), // GPIO Use Select 2 + // GPIO Use Select 2 GU04, 8, GU05, 8, GU06, 8, GU07, 8, - Offset(0x34), // GPIO IO Select 2 + // GPIO IO Select 2 GIO4, 8, GIO5, 8, GIO6, 8, GIO7, 8, - Offset(0x38), // GPIO Level 2 + // GPIO Level 2 GP32, 1, GP33, 1, GP34, 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/31672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8 Gerrit-Change-Number: 31672 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 04 Mar '19

04 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31671 Change subject: nb/intel/i945: Remove redundant use of ACPI offset operator ...................................................................... nb/intel/i945: Remove redundant use of ACPI offset operator Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/hostbridge.asl 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31671/1 diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 7b3917d..8318773 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -34,18 +34,18 @@ , 11, // EPBR, 20, // EPBAR - Offset (0x44), // MCHBAR + // MCHBAR MHEN, 1, // Enable , 13, // MHBR, 18, // MCHBAR - Offset (0x48), // PCIe BAR + // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // PXBR, 6, // PCIe BAR - Offset (0x4c), // DMIBAR + // DMIBAR DMEN, 1, // Enable , 11, // DMBR, 20, // DMIBAR @@ -56,32 +56,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), // PAM1 + // PAM1 PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), // PAM2 + // PAM2 PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), // PAM3 + // PAM3 PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), // PAM4 + // PAM4 PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), // PAM5 + // PAM5 PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), // PAM6 + // PAM6 PM6L, 2, , 2, PM6H, 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/31671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e Gerrit-Change-Number: 31671 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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