coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: inteltool: coffeelake support
by Thomas Heijligen (Code Review) 14 Mar '19

14 Mar '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31501 Change subject: inteltool: coffeelake support ...................................................................... inteltool: coffeelake support Change-Id: I9f3b3108f5672b557610fa7d8fbd5c199af8d353 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 495 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31501/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dd09214..2f51a44 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1033,6 +1033,16 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_H310: + case PCI_DEVICE_ID_INTEL_H370: + case PCI_DEVICE_ID_INTEL_Z390: + case PCI_DEVICE_ID_INTEL_Q370: + case PCI_DEVICE_ID_INTEL_B360: + case PCI_DEVICE_ID_INTEL_C246: + case PCI_DEVICE_ID_INTEL_C242: + case PCI_DEVICE_ID_INTEL_QM370: + case PCI_DEVICE_ID_INTEL_HM370: + case PCI_DEVICE_ID_INTEL_CM246: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 53a8eb9..c50917e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -841,6 +841,456 @@ &denverton_community_north, &denverton_community_south, }; + + +// heijligen +static const char *const coffeelake_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", "n/a", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", "n/a", + "GPP_A11", "PME#", "SD_VDD_PWR_EN#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", "n/a", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(coffeelake_group_a_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_a_names, +}; + +static const char *const coffeelake_group_b_names[] = { + "GPP_B0", "GSPI0_CS1#", "n/a", "n/a", "n/a", + "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", "n/a", "n/a", + "GPP_B2", "VRALRERT#", "n/a", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", "n/a", + "GPP_B11", "I2S_MCLK", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(coffeelake_group_b_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_b_names, +}; + + +static const char *const coffeelake_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", "n/a", + "GPP_C8", "UART0A_RXD", "n/a", "n/a", "n/a", + "GPP_C9", "UART0A_TXD", "n/a", "n/a", "n/a", + "GPP_C10", "UART0A_RTS#", "n/a", "n/a", "n/a", + "GPP_C11", "UART0A_CTS#", "n/a", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(coffeelake_group_c_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_c_names, +}; + + +static const char *const coffeelake_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "SBK0", "BK0", + "GPP_D1", "SPI1_CLK", "n/a", "SBK1", "BK1", + "GPP_D2", "SPI1_MISO", "n/a", "SBK2", "BK2", + "GPP_D3", "SPI2_MOSI", "n/a", "SBK3", "BK3", + "GPP_D4", "ISH_I2C2SDA", "I2C3_SDA", "SBK4", "BK4" + "GPP_D5", "I2S2_SFRM", "n/a", "CNV_RF_RESET#", "n/a", + "GPP_D6", "I2S2_TXD", "n/a", "modem_CLKREQ", "n/a", + "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", + "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", "n/a", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", "n/a", + "GPP_D11", "ISH_SPI_MISO", "GP_BSSB_CLK", "GSPI2_MISO", "n/a", + "GPP_D12", "ISH_SPI_MOSI", "GP_BSSB_DI", "GSPI2_MOSI", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "GSPI_CS1#", "n/a", "CNV_WFEN", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "CNV_WCEN", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(coffeelake_group_d_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_d_names, +}; + +static const char *const coffeelake_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_e = { + .display = "-------GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(coffeelake_group_e_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_e_names, +}; + + +static const char *const coffeelake_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", "n/a", "n/a", + "GPP_F14", "n/a", "PS_ON#", "n/a", "n/a", + "GPP_F15", "USB2_OC4#", "n/a", "n/a", "n/a", + "GPP_F16", "USB2_OC5#", "n/a", "n/a", "n/a", + "GPP_F17", "USB2_OC6#", "n/a", "n/a", "n/a", + "GPP_F18", "USB2_OC7#", "n/a", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", "n/a", + "GPP_F22", "DDPF_CTRLCLK", "n/a", "n/a", "n/a", + "GPP_F23", "DDPF_CTRLDATA", "n/a", "n/a", "n/a", + +}; + +static const struct gpio_group coffeelake_group_f = { + .display = "-------GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(coffeelake_group_f_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_f_names, +}; + + +static const char *const coffeelake_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", "n/a", + "GPP_G3", "SD_DATRA2", "n/a", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_g = { + .display = "-------GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(coffeelake_group_g_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_g_names, +}; + + +static const char *const coffeelake_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", "n/a", + "GPP_H23", "TIME_SYNC0", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_h = { + .display = "-------GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(coffeelake_group_h_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_h_names, +}; + + +static const char *const coffeelake_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "DISP_MISC0", "n/a", "n/a", + "GPP_I1", "DDPB_HPD1", "DISP_MISC1", "n/a", "n/a", + "GPP_I2", "DDPB_HPD2", "DISP_MISC2", "n/a", "n/a", + "GPP_I3", "DDPB_HPD3", "DISP_MISC3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "DISP_MISC4", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", "n/a", + "GPP_I11", "M2_SKT2_CFG0", "n/a", "n/a", "n/a", + "GPP_I12", "M2_SKT2_CFG1", "n/a", "n/a", "n/a", + "GPP_I13", "M2_SKT2_CFG2", "n/a", "n/a", "n/a", + "GPP_I14", "M2_SKT2_CFG3", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_i = { + .display = "-------GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(coffeelake_group_i_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_i_names, +}; + + +static const char *const coffeelake_group_j_names[] = { + "GPP_J0", "CNV_PA_BLANKING", "n/a", "n/a", "n/a", + "GPP_J1", "n/a", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_J2", "n/a", "n/a", "n/a", "n/a", + "GPP_J3", "n/a", "n/a", "n/a", "n/a", + "GPP_J4", "CNV_BRI_DT", "UART0B_RTS#", "n/a", "n/a", + "GPP_J5", "CNV_BRI_RSP", "UART0B_RXD", "n/a", "n/a", + "GPP_J6", "CNV_RGI_DT", "UART0B_TXD", "n/a", "n/a", + "GPP_J7", "CNV_RGI_RSP", "UART0B_CTS#", "n/a", "n/a", + "GPP_J8", "CNV_MFUART2_RXD", "n/a", "n/a", "n/a", + "GPP_J9", "CNV_MFUART2_TXD", "n/a", "n/a", "n/a", + "GPP_J10", "n/a", "n/a", "n/a", "n/a", + "GPP_J11", "A4WP_PRESENT", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_j = { + .display = "-------GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(coffeelake_group_j_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_j_names, +}; + + +static const char *const coffeelake_group_k_names[] = { + "GPP_K0", "n/a", "n/a", "n/a", "n/a", + "GPP_K1", "n/a", "n/a", "n/a", "n/a", + "GPP_K2", "n/a", "n/a", "n/a", "n/a", + "GPP_K3", "n/a", "n/a", "n/a", "n/a", + "GPP_K4", "n/a", "n/a", "n/a", "n/a", + "GPP_K5", "n/a", "n/a", "n/a", "n/a", + "GPP_K6", "n/a", "n/a", "n/a", "n/a", + "GPP_K7", "n/a", "n/a", "n/a", "n/a", + "GPP_K8", "Reserved", "n/a", "n/a", "n/a", + "GPP_K9", "Reserved", "n/a", "n/a", "n/a", + "GPP_K10", "Reserved", "n/a", "n/a", "n/a", + "GPP_K11", "Reserved", "n/a", "n/a", "n/a", + "GPP_K12", "GSXOUT", "n/a", "n/a", "n/a", + "GPP_K13", "GSXSLOAD", "n/a", "n/a", "n/a", + "GPP_K14", "GSXDIN", "n/a", "n/a", "n/a", + "GPP_K15", "GSXSRESET#", "n/a", "n/a", "n/a", + "GPP_K16", "GSXCLK", "n/a", "n/a", "n/a", + "GPP_K17", "ADR_COMPLETE", "n/a", "n/a", "n/a", + "GPP_K18", "NMI#", "n/a", "n/a", "n/a", + "GPP_K19", "SMI#", "n/a", "n/a", "n/a", + "GPP_K20", "Reserved", "n/a", "n/a", "n/a", + "GPP_K21", "Reserved", "n/a", "n/a", "n/a", + "GPP_K22", "IMGCLKOUT0", "n/a", "n/a", "n/a", + "GPP_K23", "IMGCLKOUT1", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group coffeelake_group_k = { + .display = "-------GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(coffeelake_group_k_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_k_names, +}; + +static const char *const coffeelake_group_ds_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", "n/a", + "GPD3", "PRWBTN#", "n/a", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", "n/a", + "GPD7", "n/a", "n/a", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", "n/a", +}; +static const struct gpio_group coffeelake_group_ds = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(coffeelake_group_ds_names) / 5, + .func_count = 5, + .pad_names = coffeelake_group_ds_names, +}; + + +static const struct gpio_group *const coffeelake_community_ab_groups[] = { + &coffeelake_group_a, + &coffeelake_group_b, +}; +static const struct gpio_community coffeelake_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(coffeelake_community_ab_groups), + .groups = coffeelake_community_ab_groups, +}; + + +static const struct gpio_group *const coffeelake_community_cdg_groups[] = { + &coffeelake_group_c, + &coffeelake_group_d, + &coffeelake_group_g, +}; +static const struct gpio_community coffeelake_community_cdg = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(coffeelake_community_cdg_groups), + .groups = coffeelake_community_cdg_groups, +}; + + +static const struct gpio_group *const coffeelake_community_ds_groups[] = { + &coffeelake_group_ds, +}; +static const struct gpio_community coffeelake_community_ds = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(coffeelake_community_ds_groups), + .groups = coffeelake_community_ds_groups, +}; + + +static const struct gpio_group *const coffeelake_community_khef_groups[] = { + &coffeelake_group_k, + &coffeelake_group_h, + &coffeelake_group_e, + &coffeelake_group_f, +}; +static const struct gpio_community coffeelake_community_khef = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0x6b, + .group_count = ARRAY_SIZE(coffeelake_community_khef_groups), + .groups = coffeelake_community_khef_groups, +}; + + +static const struct gpio_group *const coffeelake_community_ij_groups[] = { + &coffeelake_group_i, + &coffeelake_group_j, +}; +static const struct gpio_community coffeelake_community_ij = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(coffeelake_community_ij_groups), + .groups = coffeelake_community_ij_groups, +}; + +static const struct gpio_community *const coffeelake_communities[] = { + &coffeelake_community_ab, + &coffeelake_community_cdg, + &coffeelake_community_ds, + &coffeelake_community_khef, + &coffeelake_community_ij, +}; + + + + + + + + + + + + + + + + + + + + + + static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { @@ -860,7 +1310,7 @@ printf("%s\n", group->display); - for (p = 0; p < group->pad_count; ++p, pad_cfg += 8) { + for (p = 0; p < group->pad_count; ++p, pad_cfg += 16) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4); @@ -892,7 +1342,7 @@ for (group = 0; group < community->group_count; ++group) { print_gpio_group(community->pcr_port_id, pad_cfg, community->groups[group]); - pad_cfg += community->groups[group]->pad_count * 8; + pad_cfg += community->groups[group]->pad_count * 16; } } @@ -923,6 +1373,20 @@ communities = denverton_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_H310: + case PCI_DEVICE_ID_INTEL_H370: + case PCI_DEVICE_ID_INTEL_Z390: + case PCI_DEVICE_ID_INTEL_Q370: + case PCI_DEVICE_ID_INTEL_B360: + case PCI_DEVICE_ID_INTEL_C246: + case PCI_DEVICE_ID_INTEL_C242: + case PCI_DEVICE_ID_INTEL_QM370: + case PCI_DEVICE_ID_INTEL_HM370: + case PCI_DEVICE_ID_INTEL_CM246: + community_count = ARRAY_SIZE(coffeelake_communities); + communities = coffeelake_communities; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 5c97a6c..0814c8b 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -74,7 +74,7 @@ if (sbbar) return; - +#if 0 switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: @@ -103,6 +103,17 @@ case PCI_DEVICE_ID_INTEL_APL_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); break; + case PCI_DEVICE_ID_INTEL_H310: + case PCI_DEVICE_ID_INTEL_H370: + case PCI_DEVICE_ID_INTEL_Z390: + case PCI_DEVICE_ID_INTEL_Q370: + case PCI_DEVICE_ID_INTEL_B360: + case PCI_DEVICE_ID_INTEL_C246: + case PCI_DEVICE_ID_INTEL_C242: + case PCI_DEVICE_ID_INTEL_QM370: + case PCI_DEVICE_ID_INTEL_HM370: + case PCI_DEVICE_ID_INTEL_CM246: + break; default: perror("Unknown LPC device."); exit(1); @@ -135,23 +146,28 @@ pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS); const pciaddr_t sbbar_phys = p2sb->base_addr[0] & ~0xfULL; +#endif + const pciaddr_t sbbar_phys = 0xfd000000; + printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys); sbbar = map_physical(sbbar_phys, SBBAR_SIZE); if (sbbar == NULL) { perror("Error mapping SBREG_BAR"); error_exit = true; } - +#if 0 if (p2sb_revealed) { printf("Hiding Primary to Sideband Bridge (P2SB).\n"); pci_write_byte(p2sb, 0xe0 + 1, 1); } pci_free_dev(p2sb); - +#endif if (error_exit) exit(1); } + + void pcr_cleanup(void) { if (sbbar) -- To view, visit https://review.coreboot.org/c/coreboot/+/31501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f3b3108f5672b557610fa7d8fbd5c199af8d353 Gerrit-Change-Number: 31501 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: libpayload: Fix compile error with DEBUG_MALLOC
by You-Cheng Syu (Code Review) 14 Mar '19

14 Mar '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31562 Change subject: libpayload: Fix compile error with DEBUG_MALLOC ...................................................................... libpayload: Fix compile error with DEBUG_MALLOC DEBUG_MALLOC is an option for debugging memory allocator issues. However, we would encounter a lot of compile error if we turn it on in environments with strict compile options (e.g., ChromeOS) or different architecture (e.g., ARM64). This CL: 1. Eliminate redundant redeclaration errors in memory allocation macros. 2. Include 'stdio.h' for printing debug messages. 3. Move the declaration of 'print_malloc_map' from 'malloc.c' to 'stdlib.h' for memory allocation macros. 4. Cast arguments to unsigned int when printing debug messages to eliminate printf argument type errors. BUG=b:125576961 TEST='emerge-kukui libpayload' succeeds with and without DEBUG_MALLOC Change-Id: I5927f941f386d4920a5d41528b1471e5af294fcb Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/malloc.c 2 files changed, 38 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31562/1 diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index a2e612d..682cbf4 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -33,6 +33,9 @@ #include <die.h> #include <stddef.h> +#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) +#include <stdio.h> +#endif #include <string.h> #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) @@ -45,13 +48,19 @@ * @defgroup malloc Memory allocation functions * @{ */ +void free(void *ptr); +void *malloc(size_t size); +void *calloc(size_t nmemb, size_t size); +void *realloc(void *ptr, size_t size); +void *memalign(size_t align, size_t size); +void *dma_malloc(size_t size); +void *dma_memalign(size_t align, size_t size); +void print_malloc_map(void); #if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) -#define free(p) \ +#define free(p) \ ({ \ - extern void print_malloc_map(void); \ - extern void free(void *); \ - printf("free(%p) called from %s:%s:%d...\n", p, __FILE__, __func__, \ - __LINE__);\ + printf("free(%p) called from %s:%s:%d...\n", \ + p, __FILE__, __func__, __LINE__); \ printf("PRE free()\n"); \ print_malloc_map(); \ free(p); \ @@ -60,11 +69,9 @@ }) #define malloc(s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *malloc(size_t); \ void *ptr; \ - printf("malloc(%u) called from %s:%s:%d...\n", s, __FILE__, __func__, \ - __LINE__);\ + printf("malloc(%u) called from %s:%s:%d...\n", \ + (unsigned int)(s), __FILE__, __func__, __LINE__); \ printf("PRE malloc\n"); \ print_malloc_map(); \ ptr = malloc(s); \ @@ -74,11 +81,10 @@ }) #define calloc(n,s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *calloc(size_t,size_t); \ void *ptr; \ - printf("calloc(%u, %u) called from %s:%s:%d...\n", n, s, __FILE__, \ - __func__, __LINE__);\ + printf("calloc(%u, %u) called from %s:%s:%d...\n", \ + (unsigned int)(n), (unsigned int)(s), \ + __FILE__, __func__, __LINE__); \ printf("PRE calloc\n"); \ print_malloc_map(); \ ptr = calloc(n,s); \ @@ -88,11 +94,9 @@ }) #define realloc(p,s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *realloc(void*,size_t); \ void *ptr; \ - printf("realloc(%p, %u) called from %s:%s:%d...\n", p, s, __FILE__, \ - __func__, __LINE__);\ + printf("realloc(%p, %u) called from %s:%s:%d...\n", \ + p, (unsigned int)(s), __FILE__, __func__, __LINE__); \ printf("PRE realloc\n"); \ print_malloc_map(); \ ptr = realloc(p,s); \ @@ -102,11 +106,10 @@ }) #define memalign(a,s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *memalign(size_t, size_t); \ void *ptr; \ - printf("memalign(%u, %u) called from %s:%s:%d...\n", a, s, __FILE__, \ - __func__, __LINE__);\ + printf("memalign(%u, %u) called from %s:%s:%d...\n", \ + (unsigned int)(a), (unsigned int)(s), \ + __FILE__, __func__, __LINE__); \ printf("PRE memalign\n"); \ print_malloc_map(); \ ptr = memalign(a,s); \ @@ -116,11 +119,9 @@ }) #define dma_malloc(s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *dma_malloc(size_t); \ void *ptr; \ - printf("dma_malloc(%u) called from %s:%s:%d...\n", s, __FILE__, \ - __func__, __LINE__);\ + printf("dma_malloc(%u) called from %s:%s:%d...\n", \ + (unsigned int)(s), __FILE__, __func__, __LINE__); \ printf("PRE dma_malloc\n"); \ print_malloc_map(); \ ptr = dma_malloc(s); \ @@ -130,11 +131,10 @@ }) #define dma_memalign(a,s) \ ({ \ - extern void print_malloc_map(void); \ - extern void *dma_memalign(size_t, size_t); \ void *ptr; \ - printf("dma_memalign(%u, %u) called from %s:%s:%d...\n", a, s, \ - __FILE__, __func__, __LINE__);\ + printf("dma_memalign(%u, %u) called from %s:%s:%d...\n", \ + (unsigned int)(a), (unsigned int)(s), \ + __FILE__, __func__, __LINE__); \ printf("PRE dma_memalign\n"); \ print_malloc_map(); \ ptr = dma_memalign(a,s); \ @@ -142,14 +142,6 @@ print_malloc_map(); \ ptr; \ }) -#else -void free(void *ptr); -void *malloc(size_t size); -void *calloc(size_t nmemb, size_t size); -void *realloc(void *ptr, size_t size); -void *memalign(size_t align, size_t size); -void *dma_malloc(size_t size); -void *dma_memalign(size_t align, size_t size); #endif void init_dma_memory(void *start, u32 size); int dma_initialized(void); diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 595af63..c4a39b4 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -84,7 +84,6 @@ #define HAS_MAGIC(_h) (((_h) & MAGIC) == MAGIC) static int free_aligned(void* addr, struct memory_type *type); -void print_malloc_map(void); void init_dma_memory(void *start, u32 size) { @@ -480,7 +479,10 @@ if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) { #if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) - printf(" found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align); + printf(" found memalign region. " + "%u free, %u required\n", + (unsigned int)reg->free, + (unsigned int)((size + align - 1)/align)); #endif break; } @@ -563,9 +565,10 @@ /* FIXME: Verify the size of the block. */ - printf("%s %x: %s (%x bytes)\n", type->name, + printf("%s 0x%x: %s (%u bytes)\n", type->name, (unsigned int)(ptr - type->start), - hdr & FLAG_FREE ? "FREE" : "USED", SIZE(hdr)); + hdr & FLAG_FREE ? "FREE" : "USED", + (unsigned int)SIZE(hdr)); if (hdr & FLAG_FREE) free_memory += SIZE(hdr); @@ -576,7 +579,8 @@ if (free_memory && (type->minimal_free > free_memory)) type->minimal_free = free_memory; printf("%s: Maximum memory consumption: %u bytes\n", type->name, - (type->end - type->start) - HDRSIZE - type->minimal_free); + (unsigned int)(type->end - type->start - HDRSIZE - + type->minimal_free)); if (type != dma) { type = dma; -- To view, visit https://review.coreboot.org/c/coreboot/+/31562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5927f941f386d4920a5d41528b1471e5af294fcb Gerrit-Change-Number: 31562 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: util/autoport: Add missing IDs
by Angel Pons (Code Review) 13 Mar '19

13 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30962 Change subject: util/autoport: Add missing IDs ...................................................................... util/autoport: Add missing IDs Add four IDs found in PCIe root ports on the CPU. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30962/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 29b1c21..2f24655 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -430,6 +430,7 @@ /* PCIe bridge */ for _, id := range []uint16{ + 0x0101, 0x0105, 0x0109, 0x010d, 0x0151, 0x0155, 0x1c10, 0x1c12, 0x1c14, 0x1c16, 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, 0x1e10, 0x1e12, -- To view, visit https://review.coreboot.org/c/coreboot/+/30962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Gerrit-Change-Number: 30962 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: lib/hardwaremain: Remove unused acpi_is_wakeup() function
by Subrata Banik (Code Review) 13 Mar '19

13 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31140 Change subject: lib/hardwaremain: Remove unused acpi_is_wakeup() function ...................................................................... lib/hardwaremain: Remove unused acpi_is_wakeup() function Looks like acpi_is_wakeup() return value is not getting honoured, hence this function is not doing anything rather reading from romstage buffer. Change-Id: Icc57804074a58315e72e276fcae799febc10612d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/lib/hardwaremain.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31140/1 diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 98b8841..3ec7e8e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2019 Intel Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -469,11 +470,6 @@ timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); - /* Handoff sleep type from romstage. */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - acpi_is_wakeup(); -#endif - exception_init(); threads_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc57804074a58315e72e276fcae799febc10612d Gerrit-Change-Number: 31140 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 17

Change in ...coreboot[master]: mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN()
by HAOUAS Elyes (Code Review) 13 Mar '19

13 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30787 Change subject: mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN() ...................................................................... mb/mainboard/amd/serengeti_cheetah_fam10: Use PCI_DEVFN() Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30787/1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index 4ce5285..8fc7153 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -101,7 +101,7 @@ u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - write_pirq_info(pirq_info, busn, (devn << 3) | 0, 0x1, 0xdef8, + write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; @@ -110,12 +110,12 @@ } #if CONFIG_CBB - write_pirq_info(pirq_info, CONFIG_CBB, (0 << 3) | 0, 0x1, 0xdef8, 0x2, + write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if (sysconf.nodes > 32) { - write_pirq_info(pirq_info, CONFIG_CBB - 1, (0 << 3) | 0, 0x1, + write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; -- To view, visit https://review.coreboot.org/c/coreboot/+/30787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2ea269152c30ded7c865adc2454bccc4f986ec Gerrit-Change-Number: 30787 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: lib: Add Bubble sort algorithm
by Werner Zeh (Code Review) 12 Mar '19

12 Mar '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31544 Change subject: lib: Add Bubble sort algorithm ...................................................................... lib: Add Bubble sort algorithm Add an implementation for Bubble sort. For now, only Integers can be sorted in an ascending or descending order. It can be later simply extended to cover other datasets like strings if needed. Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- A src/include/sort.h M src/lib/Makefile.inc A src/lib/sort.c 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31544/1 diff --git a/src/include/sort.h b/src/include/sort.h new file mode 100644 index 0000000..0117d66 --- /dev/null +++ b/src/include/sort.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SORT_H_ +#define SORT_H_ + +#include <stddef.h> + +typedef enum{ + NUM_ASCENDING, + NUM_DESCENDING +} sort_order_t; + +void bubblesort(int *v, size_t num_entries, sort_order_t order); + +#endif /* SORT_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index fa1ff8b..33f68d2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -150,6 +150,7 @@ ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c +ramstage-y += sort.c romstage-y += cbmem_common.c romstage-y += imd_cbmem.c diff --git a/src/lib/sort.c b/src/lib/sort.c new file mode 100644 index 0000000..48802c1 --- /dev/null +++ b/src/lib/sort.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <sort.h> + +static void swap(int *v1, int *v2) +{ + int tmp = *v1; + + *v1 = *v2; + *v2 = tmp; +} + +static int is_bigger(int v1, int v2) +{ + return v1 > v2 ? 1 : 0; +} +/* Implement a simple Bubble sort algorithm. Reduce the needed number of + * iterations by taking care of already sorted entries in the list. */ +void bubblesort(int *v, size_t num_entries, sort_order_t order) +{ + size_t len = num_entries, idx, i; + + do { + idx = 1; + for (i = 0; i < (len - 1); ++i) { + switch (order) { + case NUM_ASCENDING: + if (is_bigger(v[i], v[i + 1])) + swap(&v[i], &v[i + 1]); + break; + case NUM_DESCENDING: + if (is_bigger(v[i + 1], v[i])) + swap(&v[i], &v[i + 1]); + break; + default: + return; + } + idx = i + 1; + } + len = idx; + } while (len > 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6 Gerrit-Change-Number: 31544 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

6 20

Change in ...coreboot[master]: acpi: Sort the reported APIC-IDs in the MADT table
by Werner Zeh (Code Review) 12 Mar '19

12 Mar '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31545 Change subject: acpi: Sort the reported APIC-IDs in the MADT table ...................................................................... acpi: Sort the reported APIC-IDs in the MADT table coreboot performs MP-Init in a parallel way. That leads to the fact that the order, in which the CPUs are woken up, can vary from boot to boot. The creation of the MADT table just parses the devicetree and takes the CPUs reported there as it is for creating the single local APIC entries. Therefore, The OS will see different order of CPUs. There are CPUs out there (like Apollo Lake for example) which have shared caches on core-level and if the order is random this can end up in assigning cores to different tasks or even OSes (in a virtual enviroinment) which uses the same cache. This in turn will produce performance penalties across these distributed tasks/OSes. Though there is a way on discover the core- and cache-topology it will in the end be necessary to take the APIC-ID into account. To simplify it, one can achieve the same output by sorting the APIC-IDs in an ascending order. This will lead to the fact that CPUs that share a given cache will be reported right next to each other in the MADT. Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/acpi.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31545/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 0c85d3a..c7b9214 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -8,7 +8,7 @@ * Copyright (C) 2005-2009 coresystems GmbH * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, * Raptor Engineering - * Copyright (C) 2016-2017 Siemens AG + * Copyright (C) 2016-2019 Siemens AG * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9(a)btinternet.com>, and those portions @@ -47,6 +47,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> +#include <sort.h> u8 acpi_checksum(u8 *table, u32 length) { @@ -148,7 +149,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) { struct device *cpu; - int index = 0; + int index, apic_ids[CONFIG_MAX_CPUS], num_cpus = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -157,9 +158,12 @@ } if (!cpu->enabled) continue; + apic_ids[num_cpus++] = cpu->path.apic.apic_id; + } + bubblesort(apic_ids, num_cpus, NUM_ASCENDING); + for (index = 0; index < num_cpus; index++) { current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, - index, cpu->path.apic.apic_id); - index++; + index, apic_ids[index]); } return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/31545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735 Gerrit-Change-Number: 31545 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: util/lint: Fix clang-format test and enable it by default
by Patrick Georgi (Code Review) 11 Mar '19

11 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31654 Change subject: util/lint: Fix clang-format test and enable it by default ...................................................................... util/lint: Fix clang-format test and enable it by default git diff needed to emit diffs without prefix (e.g. a/ and b/) for clang-format-diff to be able to work. Also require that the test succeeds. Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- R util/lint/lint-stable-022-clang-format 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31654/1 diff --git a/util/lint/lint-022-clang-format b/util/lint/lint-stable-022-clang-format similarity index 79% rename from util/lint/lint-022-clang-format rename to util/lint/lint-stable-022-clang-format index 932d9c0..bd662e4 100755 --- a/util/lint/lint-022-clang-format +++ b/util/lint/lint-stable-022-clang-format @@ -30,5 +30,9 @@ fi if [ $(clang-format $files_to_check | wc -l) -gt 0 ]; then - git diff HEAD~..HEAD -- $files_to_check | clang-format-diff + if [ "$(git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff)" != "" ]; then + echo "Coding style mismatch. The following patch fixes it:" + git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff + exit 1 + fi fi -- To view, visit https://review.coreboot.org/c/coreboot/+/31654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372 Gerrit-Change-Number: 31654 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mb/google/hatch: Enable Audio support
by Sathya Prakash M R (Code Review) 11 Mar '19

11 Mar '19

Sathya Prakash M R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31280 Change subject: mb/google/hatch: Enable Audio support ...................................................................... mb/google/hatch: Enable Audio support Following changes are done to enable Audio support on hatch 1. Enable I2C4 device at 400Khz at 3.3V 2. Configure GPIO for HP INT and SPEAKER EN 3. Add ACPI entry for RT5682 4. Enable DMIC, I2S0 and I2S1 lines. BUG=b:123738217 BRANCH=none TEST=check SSDT table for RT5682 entry. verify audio over SOF. Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 46 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31280/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f2..6d0ea04 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -27,6 +27,7 @@ #| | before memory is up | #| I2C0 | Touchpad | #| I2C1 | Touch screen | + #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -39,6 +40,9 @@ .i2c[1] = { .speed = I2C_SPEED_FAST, }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, }" # FSP configuration @@ -92,6 +96,12 @@ register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" + #Enable I2S Audio, SSP0, SSP1 and DMIC0 + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaAudioLinkDmic0" = "1" + device cpu_cluster 0 on device lapic 0 on end end @@ -223,7 +233,21 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA - device pci 19.0 on end # I2C #4 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H0_IRQ)" + register "probed" = "1" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC @@ -264,7 +288,13 @@ end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f8d5d7d..5820af7 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -65,6 +65,10 @@ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* PCH_I2C_AUDIO_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* PCH_I2C_AUDIO_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* H1_PCH_INT_ODL */ @@ -143,6 +147,16 @@ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP => NC */ PAD_NC(GPP_G7, DN_20K), + /*AUDIO IRQ*/ + PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT), + /*SPEAKER SD MODE ENABLE*/ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/31280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Gerrit-Change-Number: 31280 Gerrit-PatchSet: 1 Gerrit-Owner: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-MessageType: newchange

7 23

Change in ...coreboot[master]: drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYP...
by mikeb mikeb (Code Review) 08 Mar '19

08 Mar '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31222 to review the following change. Change subject: drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP ...................................................................... drivers/intel/wifi/Kconfig: disable DRIVERS_INTEL_WIFI if !SYSTEM_TYPE_LAPTOP Intel PCI-e WiFi adapters are rare outside of laptops. DRIVERS_INTEL_WIFI should not be selected by default if the mainboard is not a laptop. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9a7e5cd515da4ee4c4176227eea2e863ed55c420 --- M src/drivers/intel/wifi/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31222/1 diff --git a/src/drivers/intel/wifi/Kconfig b/src/drivers/intel/wifi/Kconfig index 4dc4d7f..80a7ef8 100644 --- a/src/drivers/intel/wifi/Kconfig +++ b/src/drivers/intel/wifi/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_INTEL_WIFI bool "Support Intel PCI-e WiFi adapters" depends on ARCH_X86 - default y if PCIEXP_PLUGIN_SUPPORT + default y if PCIEXP_PLUGIN_SUPPORT && !SYSTEM_TYPE_LAPTOP help When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets. -- To view, visit https://review.coreboot.org/c/coreboot/+/31222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a7e5cd515da4ee4c4176227eea2e863ed55c420 Gerrit-Change-Number: 31222 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019