coreboot-gerrit February 2019

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Change in ...coreboot[master]: src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default
by mikeb mikeb (Code Review) 08 Mar '19

08 Mar '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31308 to review the following change. Change subject: src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default ...................................................................... src/mainboard/emulation/Kconfig: disable DRIVERS_INTEL_WIFI by default It is impossible to insert the Intel PCI-e WiFi adapter to any of the Emulation boards because they are not physical, so this driver option should be disabled by default. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ia5802b3234f984d906c6a1048ed8176f85f9bb99 --- M src/mainboard/emulation/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31308/1 diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 759b1de..f9e1198 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -19,4 +19,8 @@ string default "Emulation" +config DRIVERS_INTEL_WIFI + bool + default n + endif # VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/31308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5802b3234f984d906c6a1048ed8176f85f9bb99 Gerrit-Change-Number: 31308 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: src/mb: Remove include <commonlib/loglevel.h>
by HAOUAS Elyes (Code Review) 08 Mar '19

08 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31239 Change subject: src/mb: Remove include <commonlib/loglevel.h> ...................................................................... src/mb: Remove include <commonlib/loglevel.h> This file is alreasy included in <console/console.h> Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c 26 files changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31239/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index bb14c59..80ad1aa 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -27,7 +27,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <arch/cpu.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7d245e7..1252346 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 87ef750..2b37f9b 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 40ff0bb..bf5c9de 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 538e7a7..7a38f95 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 4316d4f..48ece89 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index c59816e..4bb35fb 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 58fea20..3419df5 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -29,7 +29,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <spd.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 11d6837..9ae3834 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0e65b53..4c35df696 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 0081c2f..16786aa 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 76e2290..2b2f0a2 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -16,7 +16,6 @@ */ #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 3f78c4c..3bb622d 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 4802b9d..122e510 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 8dbd9e5..9ececa8 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 061764d..602faa2 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -27,7 +27,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 1e19b9e..af8fd2a 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -20,7 +20,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index f587257..f71858a 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <device/pci_def.h> #include <arch/io.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 94d2abe..09fc200 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 9745895..a41b6cd 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 19b6022..5990c4d 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -26,7 +26,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 252add0..33af7d6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 16d3068..078e19b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 9701193..d0c021f 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -30,7 +30,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6c405b8..9c36499 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,7 +21,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> #include <timestamp.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index ef3a372..b4c08aa 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief61106eb78d0de743c920f358937c51658c228a Gerrit-Change-Number: 31239 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

7 17

Change in ...coreboot[master]: src/device/Kconfig: Add support for discrete VGA OpROM inclusion at c...
by mikeb mikeb (Code Review) 07 Mar '19

07 Mar '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31449 to review the following change. Change subject: src/device/Kconfig: Add support for discrete VGA OpROM inclusion at config UI ...................................................................... src/device/Kconfig: Add support for discrete VGA OpROM inclusion at config UI Create the way of adding the discrete VGA OpROM at config UI ( alternative to ./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom ) DGPU options are accessible only if CONFIG_MULTIPLE_VGA_ADAPTERS is enabled. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a --- M src/arch/x86/Makefile.inc M src/device/Kconfig 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31449/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8dafac8..47ef66b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,6 +47,13 @@ pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)) pci$(stripped_vgabios_id).rom-type := optionrom +ifeq ($(CONFIG_MULTIPLE_VGA_ADAPTERS),y) +stripped_vgabios_dgpu_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_ID)) +cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom +pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE)) +pci$(stripped_vgabios_dgpu_id).rom-type := optionrom +endif + verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c diff --git a/src/device/Kconfig b/src/device/Kconfig index b90b15f..33c1e5b3 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -613,6 +613,41 @@ Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. +config VGA_BIOS_DGPU + bool "Add a Discrete VGA BIOS image" + depends on ARCH_X86 && MULTIPLE_VGA_ADAPTERS + help + Select this option if you have a VGA BIOS image for Discrete GPU + that you would like to add to your ROM. + + You will be able to specify the location and file name of the + image later. + +config VGA_BIOS_DGPU_FILE + string "Discrete VGA BIOS path and filename" + depends on VGA_BIOS_DGPU + default "vgabios_dgpu.bin" + help + The path and filename of the file to use as VGA BIOS for Discrete GPU. + +config VGA_BIOS_DGPU_ID + string "Discrete VGA device PCI IDs" + depends on VGA_BIOS_DGPU + default "1002,6663" + help + The comma-separated PCI vendor and device ID that would associate + your VGA BIOS to your discrete video card. + + Examples: + 1002,6663 for HD 8570M + 1002,6665 for R5 M230 + + In the above examples 1002 is the PCI vendor ID (in hex, but without + the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the + discrete video card (also in hex, without "0x" prefix). + + Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. + config INTEL_GMA_HAVE_VBT bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/31449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a Gerrit-Change-Number: 31449 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 25

Change in ...coreboot[master]: intelmetool: Add more flag descriptions
by Damien Zammit (Code Review) 07 Mar '19

07 Mar '19

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31589 Change subject: intelmetool: Add more flag descriptions ...................................................................... intelmetool: Add more flag descriptions Obtained by inspecting intel SPSinfo tool output Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e Author: roncapat Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M util/intelmetool/me.h M util/intelmetool/me_status.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31589/1 diff --git a/util/intelmetool/me.h b/util/intelmetool/me.h index dfd5cbb..6a20807 100644 --- a/util/intelmetool/me.h +++ b/util/intelmetool/me.h @@ -33,6 +33,8 @@ #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 #define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_TEST 3 +#define ME_HFS_CWS_DISABLED 4 #define ME_HFS_CWS_NORMAL 5 #define ME_HFS_CWS_WAIT 6 #define ME_HFS_CWS_TRANS 7 @@ -45,6 +47,7 @@ #define ME_HFS_STATE_ERROR 7 #define ME_HFS_ERROR_NONE 0 #define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_DISABLED 2 #define ME_HFS_ERROR_IMAGE 3 #define ME_HFS_ERROR_DEBUG 4 #define ME_HFS_MODE_NORMAL 0 diff --git a/util/intelmetool/me_status.c b/util/intelmetool/me_status.c index 0cc670b..ede3e3a 100644 --- a/util/intelmetool/me_status.c +++ b/util/intelmetool/me_status.c @@ -24,6 +24,8 @@ [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_TEST] = "Test", + [ME_HFS_CWS_DISABLED] = "Disabled", [ME_HFS_CWS_NORMAL] = "Normal", [ME_HFS_CWS_WAIT] = "Platform Disable Wait", [ME_HFS_CWS_TRANS] = "OP State Transition", @@ -53,6 +55,7 @@ static const char *me_error_values[] = { [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_DISABLED] = "Disabled", [ME_HFS_ERROR_IMAGE] = "Image Failure", [ME_HFS_ERROR_DEBUG] = "Debug Failure" }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e Gerrit-Change-Number: 31589 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: intelmetool: Consolidate all model support from upstream
by Damien Zammit (Code Review) 07 Mar '19

07 Mar '19

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31588 Change subject: intelmetool: Consolidate all model support from upstream ...................................................................... intelmetool: Consolidate all model support from upstream Some of the older chipsets that are known not to have ME at all were removed for some reason, add them back in. Also some newer chipsets/ME models were missing, add them in. Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M util/intelmetool/intelmetool.c M util/intelmetool/intelmetool.h 2 files changed, 218 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/31588/1 diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 5a00025..cca5d45 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -138,7 +138,12 @@ if (dev->vendor_id != PCI_VENDOR_ID_INTEL) continue; - if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) { + if (PCI_DEV_NO_ME(dev->device_id)) { + printf(CGRN "Good news, you have a `%s` so you have no ME " + "present at all, continuing...\n\n" + RESET, name); + break; + } else if (PCI_DEV_HAS_ME_DISABLE(dev->device_id)) { printf(CGRN "Good news, you have a `%s` so ME is " "present but can be disabled, continuing...\n\n" RESET, name); diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 49f0537..6db3dbb 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2010 by coresystems GmbH * Copyright (C) 2009 Carl-Daniel Hailfinger - * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2015-2019 Damien Zammit * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -71,6 +71,76 @@ #define PCI_VENDOR_ID_INTEL 0x8086 +// Chipset does not have ME +#define PCI_DEVICE_ID_INTEL_82810 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 +#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 +#define PCI_DEVICE_ID_INTEL_82830M 0x3575 +#define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82865 0x2570 +#define PCI_DEVICE_ID_INTEL_82915 0x2580 +#define PCI_DEVICE_ID_INTEL_82945P 0x2770 +#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac +#define PCI_DEVICE_ID_INTEL_82X58 0x3405 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 +#define PCI_DEVICE_ID_INTEL_I63XX 0x2670 +#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0 +#define PCI_DEVICE_ID_INTEL_I5000Z 0x25d0 +#define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 +#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 +#define PCI_DEVICE_ID_INTEL_82443LX 0x7180 +#define PCI_DEVICE_ID_INTEL_82443BX 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192 +#define PCI_DEVICE_ID_INTEL_82371XX 0x7110 +#define PCI_DEVICE_ID_INTEL_ICH 0x2410 +#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH2 0x2440 +#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 +#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 +#define PCI_DEVICE_ID_INTEL_ICH6 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 +#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 +#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_NM10 0x27bc + +#define PCI_DEV_NO_ME(x) ( \ + ((x) == PCI_DEVICE_ID_INTEL_82810 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82810_DC ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82810E_DC ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82830M ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82845 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82865 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82915 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82945P ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82945GM ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82945GSE ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82X58 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ATOM_DXXX ) || \ + ((x) == PCI_DEVICE_ID_INTEL_I63XX ) || \ + ((x) == PCI_DEVICE_ID_INTEL_I5000X ) || \ + ((x) == PCI_DEVICE_ID_INTEL_I5000Z ) || \ + ((x) == PCI_DEVICE_ID_INTEL_I5000V ) || \ + ((x) == PCI_DEVICE_ID_INTEL_I5000P ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82443LX ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82443BX ) || \ + ((x) == PCI_DEVICE_ID_INTEL_82443BX_NO_AGP) || \ + ((x) == PCI_DEVICE_ID_INTEL_82371XX ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH0 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH2 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH4 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH4M ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH5 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH6 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH7DH ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH7 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH7M ) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICH7MDH ) || \ + ((x) == PCI_DEVICE_ID_INTEL_NM10 )) + // Definitely has ME and can be disabled #define PCI_DEVICE_ID_INTEL_ICH8ME 0x2811 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 @@ -130,13 +200,70 @@ #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f -#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f #define PCI_DEVICE_ID_INTEL_DH89XXCC 0x2310 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 -#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 +#define PCI_DEVICE_ID_INTEL_H81 0x8c5c +#define PCI_DEVICE_ID_INTEL_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_Z87 0x8c44 #define PCI_DEVICE_ID_INTEL_X99 0x8d47 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP1 0x9cc1 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP2 0x9cc2 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP3 0x9cc3 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP4 0x9cc5 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP5 0x9cc6 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP6 0x9cc7 +#define PCI_DEVICE_ID_INTEL_WILDCAT_LP7 0x9cc9 +#define PCI_DEVICE_ID_INTEL_SUNRISE_LP1 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISE_LP2 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISE_LP3 0x9d4e +#define PCI_DEVICE_ID_INTEL_SUNRISE_LP4 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISE_LP5 0x9d58 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H0 0xa140 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H1 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H2 0xa142 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H3 0xa143 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H4 0xa144 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H5 0xa145 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H6 0xa146 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H7 0xa147 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H8 0xa148 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H9 0xa149 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H10 0xa14a +#define PCI_DEVICE_ID_INTEL_SUNRISE_H11 0xa14b +#define PCI_DEVICE_ID_INTEL_SUNRISE_H12 0xa14c +#define PCI_DEVICE_ID_INTEL_SUNRISE_H13 0xa14d +#define PCI_DEVICE_ID_INTEL_SUNRISE_H14 0xa14e +#define PCI_DEVICE_ID_INTEL_SUNRISE_H15 0xa14f +#define PCI_DEVICE_ID_INTEL_SUNRISE_H16 0xa150 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H17 0xa151 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H18 0xa152 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H19 0xa153 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H20 0xa154 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H21 0xa155 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H22 0xa156 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H23 0xa157 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H24 0xa158 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H25 0xa159 +#define PCI_DEVICE_ID_INTEL_SUNRISE_H26 0xa15a +#define PCI_DEVICE_ID_INTEL_SUNRISE_H27 0xa15b +#define PCI_DEVICE_ID_INTEL_SUNRISE_H28 0xa15c +#define PCI_DEVICE_ID_INTEL_SUNRISE_H29 0xa15d +#define PCI_DEVICE_ID_INTEL_SUNRISE_H30 0xa15e +#define PCI_DEVICE_ID_INTEL_SUNRISE_H31 0xa15f +#define PCI_DEVICE_ID_INTEL_LEWISBURG_1 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_2 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_3 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_4 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_5 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_6 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_7 0xa1c7 #define PCI_DEV_HAS_ME_DIFFICULT(x) ( \ ((x) == PCI_DEVICE_ID_INTEL_ICH10R) || \ @@ -187,13 +314,71 @@ ((x) == PCI_DEVICE_ID_INTEL_HM75 ) || \ ((x) == PCI_DEVICE_ID_INTEL_HM70 ) || \ ((x) == PCI_DEVICE_ID_INTEL_NM70 ) || \ - ((x) == PCI_DEVICE_ID_INTEL_QM87 ) || \ ((x) == PCI_DEVICE_ID_INTEL_DH89XXCC ) || \ ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL ) || \ ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM ) || \ ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE ) || \ - ((x) == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP ) || \ - ((x) == PCI_DEVICE_ID_INTEL_X99 )) + ((x) == PCI_DEVICE_ID_INTEL_H81 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_B85 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_Q85 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_Q87 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_QM87 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_H87 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_HM87 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_Z87 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_X99 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP1 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP2 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP3 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP4 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP5 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP6 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_LP7 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP1 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP2 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP3 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP4 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP5 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H0 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H4 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H5 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H6 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H7 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H8 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H9 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H10 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H11 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H12 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H13 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H14 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H15 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H16 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H17 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H18 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H19 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H20 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H21 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H22 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H23 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H24 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H25 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H26 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H27 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H28 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H29 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H30 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H31 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_1 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_2 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_3 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_4 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_5 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_6 ) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_7 ) || \ + 0) // Not sure if ME present, but should be able to disable it easily #define PCI_DEVICE_ID_INTEL_ICH8 0x2810 @@ -219,6 +404,7 @@ ((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC) || \ ((x) == PCI_DEVICE_ID_INTEL_SCH_POULSBO)) +// ME PCI IDs (HECI) #define PCI_DEVICE_ID_INTEL_COUGARPOINT_1 0x1C3A /* Cougar Point */ #define PCI_DEVICE_ID_INTEL_PATSBURG_1 0x1D3A /* C600/X79 Patsburg */ #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_1 0x1CBA /* Panther Point */ @@ -258,9 +444,16 @@ #define PCI_DEVICE_ID_INTEL_LYNXPOINT_4 0x9C3A /* Lynx Point LP */ #define PCI_DEVICE_ID_INTEL_WILDCAT_1 0x9CBA /* Wildcat Point LP */ #define PCI_DEVICE_ID_INTEL_WILDCAT_2 0x9CBB /* Wildcat Point LP 2 */ -#define PCI_DEVICE_ID_INTEL_SUNRISE_H1 0xa13a /* SUNRISE Point-H 1 */ -#define PCI_DEVICE_ID_INTEL_SUNRISE_H2 0xa13b /* SUNRISE Point-H 2 */ #define PCI_DEVICE_ID_INTEL_SUNRISE_LP 0x9d3a /* SUNRISE Point-LP */ +#define PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME 0xa13a /* SUNRISE Point-H 1 */ +#define PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME 0xa13b /* SUNRISE Point-H 2 */ +#define PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME 0xA13E /* SUNRISE Point-H 3 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1 0xA1BA /* CSME Lewisburg #1 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2 0xA1BB /* CSME Lewisburg #2 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3 0xA1BE /* CSME Lewisburg #3 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE1 0xA1F8 /* IE Lewisburg #1 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE2 0xA1F9 /* IE Lewisburg #2 */ +#define PCI_DEVICE_ID_INTEL_LEWISBURG_IE3 0xA1FC /* IE Lewisburg #3 */ #define PCI_DEV_HAS_SUPPORTED_ME(x) ( \ ((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \ @@ -302,9 +495,17 @@ ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_4) || \ ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_1) || \ ((x) == PCI_DEVICE_ID_INTEL_WILDCAT_2) || \ - ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1) || \ - ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2) || \ - ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP)) + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_LP) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H1_ME) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H2_ME) || \ + ((x) == PCI_DEVICE_ID_INTEL_SUNRISE_H3_ME) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME1) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME2) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_CSME3) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE1) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE2) || \ + ((x) == PCI_DEVICE_ID_INTEL_LEWISBURG_IE3) || \ + 0) #define BOOTGUARD_DISABLED 0x400000000 #define BOOTGUARD_ENABLED_VERIFIED_MODE 0x100000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/31588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba Gerrit-Change-Number: 31588 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist
by Subrata Banik (Code Review) 07 Mar '19

07 Mar '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31608 Change subject: prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist ...................................................................... prog_loader: Associate TS_END_ROMSTAGE timestamp with postcar if exist This patch adds timestamp for "end of romstage" with postcar if platform has selected postcar as dedicated stage. If postcar stage doesn't exist then "end of romstage" timestamp will get call while starting of ramstage as exist today. TEST=Its been observed that "end of romstage" timestamp doesn't appear in "cbmem -t" log when ramstage is not getting executed. As part of this fix "end of romstage" timestamp is showing in "cbmem -t" log on IA platform where POSTCAR is a dedicated stage. Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/postcar_loader.c M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/31608/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 141e8d2..8d1cab4 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -23,6 +23,7 @@ #include <rmodule.h> #include <romstage_handoff.h> #include <stage_cache.h> +#include <timestamp.h> static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { @@ -159,6 +160,9 @@ struct prog prog = PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar"); + /* As postcar exist, its end of romstage here */ + timestamp_add_now(TS_END_ROMSTAGE); + postcar_commit_mtrrs(pcf); if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 70ea7ef..5baeb8b 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -128,7 +128,9 @@ struct prog ramstage = PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage"); - timestamp_add_now(TS_END_ROMSTAGE); + /* Call "end of romstage" here if postcar stage doesn't exist */ + if (!IS_ENABLED(CONFIG_ARCH_POSTCAR_X86_32)) + timestamp_add_now(TS_END_ROMSTAGE); /* * Only x86 systems using ramstage stage cache currently take the same -- To view, visit https://review.coreboot.org/c/coreboot/+/31608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17fd89296354b66a5538f85737c79145232593d3 Gerrit-Change-Number: 31608 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Enable PM timer emulation support
by Subrata Banik (Code Review) 07 Mar '19

07 Mar '19

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31609 to review the following change. Change subject: soc/intel/icelake: Enable PM timer emulation support ...................................................................... soc/intel/icelake: Enable PM timer emulation support TEST=Able to build and boot with alt/tianocore payload. Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/cpu.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31609/1 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 0585450..f4ebacf 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -24,6 +24,7 @@ #include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> #include <intelblocks/smm.h> #include <romstage_handoff.h> #include <soc/cpu.h> @@ -118,6 +119,23 @@ } } +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + static void set_energy_perf_bias(u8 policy) { msr_t msr; @@ -190,6 +208,9 @@ /* Configure Intel Speed Shift */ configure_isst(); + /* Enable PM timer emulation */ + enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h index 1e8d9e8..fae8500 100644 --- a/src/soc/intel/icelake/include/soc/cpu.h +++ b/src/soc/intel/icelake/include/soc/cpu.h @@ -35,6 +35,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 38.4MHz. */ +#define CTC_FREQ 38400000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/31609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff Gerrit-Change-Number: 31609 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: rename VB2_DISABLE_DEVELOPER_MODE
by Joel Kitching (Code Review) 07 Mar '19

07 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31298 Change subject: vboot: rename VB2_DISABLE_DEVELOPER_MODE ...................................................................... vboot: rename VB2_DISABLE_DEVELOPER_MODE Rename VB2_DISABLE_DEVELOPER_MODE to VB2_CONTEXT_DISABLE_DEVELOPER_MODE. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460645 BRANCH=none Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31298/1 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 1b24160..afed5cc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -326,7 +326,7 @@ if (get_recovery_mode_switch()) { ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (IS_ENABLED(CONFIG_VBOOT_DISABLE_DEV_ON_RECOVERY)) - ctx.flags |= VB2_DISABLE_DEVELOPER_MODE; + ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; } if (IS_ENABLED(CONFIG_VBOOT_WIPEOUT_SUPPORTED) && -- To view, visit https://review.coreboot.org/c/coreboot/+/31298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9754425dc2f346e8edac584c4d076d13ae31d2d Gerrit-Change-Number: 31298 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: rename VB2_SD_DEV_MODE_ENABLED
by Joel Kitching (Code Review) 07 Mar '19

07 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31297 Change subject: vboot: rename VB2_SD_DEV_MODE_ENABLED ...................................................................... vboot: rename VB2_SD_DEV_MODE_ENABLED Rename VB2_SD_DEV_MODE_ENABLED to VB2_SD_FLAG_DEV_MODE_ENABLED. See CL in CQ-DEPEND for details. BUG=b:124141368 TEST=Build locally CQ-DEPEND=CL:1460644 BRANCH=none Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31297/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 684b495..884879e 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -71,7 +71,7 @@ *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; } - if (vb2_sd->flags & VB2_SD_DEV_MODE_ENABLED) { + if (vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; *oflags |= VB_INIT_OUT_CLEAR_RAM; *oflags |= VB_INIT_OUT_ENABLE_DISPLAY; -- To view, visit https://review.coreboot.org/c/coreboot/+/31297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298cd3a5026055e439de1ce409e61f1feb24369b Gerrit-Change-Number: 31297 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Add myself as potential mentor for QEMU targets
by Patrick Georgi (Code Review) 07 Mar '19

07 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31556 Change subject: Documentation: Add myself as potential mentor for QEMU targets ...................................................................... Documentation: Add myself as potential mentor for QEMU targets Change-Id: I11df0283f14ae03243247fe9377754b216df0442 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31556/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 3bd8216..9a2d414 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -78,6 +78,7 @@ hardware is available. ### Mentors +* Patrick Georgi <patrick(a)georgi.software> ## Add Kernel Address Sanitizer functionality to coreboot The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector. -- To view, visit https://review.coreboot.org/c/coreboot/+/31556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11df0283f14ae03243247fe9377754b216df0442 Gerrit-Change-Number: 31556 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019