coreboot-gerrit February 2019

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Change in ...coreboot[master]: soc/intel/skylake: Unify serial IRQ options
by Nico Huber (Code Review) 01 Mar '19

01 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31596 Change subject: soc/intel/skylake: Unify serial IRQ options ...................................................................... soc/intel/skylake: Unify serial IRQ options We had two ways to configure the serial IRQ mode. One time in the devicetree for FSP and one time through Kconfig for coreboot. We'll use `enum serirq_mode` from soc/intel/common/ as a devicetree option instead. As the default is `quiet mode` here and that is the most common mode, this saves us a lot of lines. In two cases KBLRVP8 and 11, we had conflicting settings in devicetree and Kconfig. We'll maintain the devicetree state, although it might be that coreboot overrode this earlier. Note: A lot of Google boards have serial IRQ enabled, while the pin seems to be unconnected? Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/lpc.c 29 files changed, 16 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31596/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 66c1c53..2f275ac 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -46,7 +46,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 07a453d..bfabe29 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -81,7 +81,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index d365e8f..e0a792d 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -38,7 +38,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index cffb6df..0f5a911 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index e0c7fc7..a9b28a8 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 1b87cca..07467b3 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index f4e09a6..d4266cc 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 56087ad..f3f5eab 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -36,7 +36,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 0effbd7..5cce0f0 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -38,7 +38,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5b49884..407c37d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -54,7 +54,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 251cab8..7335c0a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 5d9c096..59cca29 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -50,7 +50,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 75a01c2..fed85b6 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4d9403c..ac52208 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -56,7 +56,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index c8e4008..4f58f40 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -54,7 +54,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4713a81..d813cc1 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 51399dc..fcd5aab 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -54,8 +54,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 119767f..436a4ed 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -11,7 +11,7 @@ register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0" - register "SerialIrqConfigSirqMode" = "0x01" + register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enable PCIE slot register "PcieRpEnable[5]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 9753c64..8dbaf68 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -10,7 +10,8 @@ register "ScsSdCardEnabled" = "0" register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" - register "SerialIrqConfigSirqMode" = "0x01" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 4b720bf..ec1c11f 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -60,8 +60,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 197121e..524bcca 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -25,7 +25,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_LPSS_UART_FOR_CONSOLE - select SERIRQ_CONTINUOUS_MODE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7036b28..8f78249 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -60,9 +60,7 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" - register "SerialIrqConfigSirqMode" = "0x01" + register "serirq_mode" = "SERIRQ_CONTINUOUS" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 399c643..a089712 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -61,7 +61,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f9f7ef7..9bf0b98 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -61,7 +61,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 77d259b..53094b1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -162,13 +162,6 @@ help This option allows you to select MMIO Base Address of sideband bus. -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - config SMM_RESERVED_SIZE hex default 0x200000 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index cbbfaaa..1f32a3e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -22,6 +22,7 @@ #include <fsp/util.h> #include <intelblocks/chip.h> #include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <soc/acpi.h> @@ -190,8 +191,9 @@ params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; - params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable; - params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode; + params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->SerialIrqConfigSirqMode = + config->serirq_mode == SERIRQ_CONTINUOUS; params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f131a1a..a8ee064 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -24,6 +24,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> #include <stdint.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -428,13 +429,7 @@ RESET_POWER_CYCLE_4S = 4, } PmConfigPwrCycDur; - /* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/ - u8 SerialIrqConfigSirqEnable; - - enum { - SERIAL_IRQ_QUIET_MODE = 0, - SERIAL_IRQ_CONTINUOUS_MODE = 1, - } SerialIrqConfigSirqMode; + enum serirq_mode serirq_mode; enum { SERIAL_IRQ_FRAME_PULSE_4CLK = 0, diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f4e17c6..c9afeb4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -26,6 +26,7 @@ #include <fsp/util.h> #include <intelblocks/chip.h> #include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -418,8 +419,8 @@ /* Indicate whether platform supports Voltage Margining */ params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; - params->PchSirqEnable = config->SerialIrqConfigSirqEnable; - params->PchSirqMode = config->SerialIrqConfigSirqMode; + params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init(); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 8d97822..ae6c144 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -109,6 +109,8 @@ void lpc_soc_init(struct device *dev) { + const config_t *const config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script); @@ -117,10 +119,7 @@ lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); + lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ pch_enable_ioapic(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/31596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Gerrit-Change-Number: 31596 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: payloads/tianocore: Add option for custom bootsplash
by Matt DeVillier (Code Review) 01 Mar '19

01 Mar '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31561 Change subject: payloads/tianocore: Add option for custom bootsplash ...................................................................... payloads/tianocore: Add option for custom bootsplash Add Kconfig options to use custom bootsplash file, dependent on using MrChromebox's stable branch, with help info conveying required file format. Adjust Makefile to copy the custom bootsplash and overwrite the default Logo.bmp file, handling both absolute and relative paths, and restore the original logo file after building so as to keep the working directory clean. Test: build with and without custom bootsplash, ensure correct bootsplash displayed Change-Id: I164f46777169801cff56633fd920bc81b7c8129a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31561/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 4fda725..7249553 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -135,6 +135,7 @@ CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ + CONFIG_TIANOCORE_BOOTSPLASH_FILE="$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 79e09e6..12010ea 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -87,4 +87,24 @@ help Use 8254 Timer for legacy support. +config TIANOCORE_BOOTSPLASH_IMAGE + bool "Use a custom bootsplash image" + depends on TIANOCORE_STABLE + help + Select this option if you have a bootsplash image that you would + like to be used. If this option is not selected, the default + coreboot logo (European Brown Hare) will used. + +config TIANOCORE_BOOTSPLASH_FILE + string "Tianocore Bootsplash path and filename" + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "bootsplash.bmp" + help + The path and filename of the file to use as graphical bootsplash + screen. The file format must be uncompressed BMP, and the file's + resolution must be less than the native resolution of the display. + + If an absolute path is not given, the path will assumed to be + relative to the coreboot root directory. + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index e4f395f..989f723 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -87,6 +87,15 @@ build: $(project_dir)/.version_$(TAG-y) checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools echo " build $(project_name) $(TAG-y)" + if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ + echo " Copying custom bootsplash image"; \ + if [[ "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" = /* ]]; then \ + cp "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" "$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp"; \ + else \ + cp "$$(dirname "$$(dirname "$$(dirname "$(CURDIR)")")")/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" \ + "$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp"; \ + fi; \ + fi; \ cd $(project_dir); \ export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \ export WORKSPACE=$(project_dir); \ @@ -96,7 +105,8 @@ cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd + mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/31561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164f46777169801cff56633fd920bc81b7c8129a Gerrit-Change-Number: 31561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: mb/siemens/mc_bdx1: Enable TPM2 on LPC
by Werner Zeh (Code Review) 01 Mar '19

01 Mar '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31663 Change subject: mb/siemens/mc_bdx1: Enable TPM2 on LPC ...................................................................... mb/siemens/mc_bdx1: Enable TPM2 on LPC This mainboard has a TPM located on the LPC bus. Enable the driver for it so that it is initialized and the ACPI table entry is generated. Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/Kconfig M src/mainboard/siemens/mc_bdx1/devicetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31663/1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index 667a6ee..d99fea8 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -14,6 +14,8 @@ select DRIVER_SIEMENS_NC_FPGA select DRIVERS_I2C_RX6110SA select DRIVERS_I2C_PCA9538 + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb index 6b5c118..fd7d83f 100644 --- a/src/mainboard/siemens/mc_bdx1/devicetree.cb +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -7,7 +7,11 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on # LPC Bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on # Enable external RTC chip -- To view, visit https://review.coreboot.org/c/coreboot/+/31663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360 Gerrit-Change-Number: 31663 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: doc/util: Improve cbmem utility description
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31653 Change subject: doc/util: Improve cbmem utility description ...................................................................... doc/util: Improve cbmem utility description Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Documentation/util.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31653/1 diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1..8f252c4 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -26,7 +26,7 @@ * _fmaptool_ - Converts plaintext fmd files into fmap blobs `C` * _rmodtool_ - Creates rmodules `C` * _ifwitool_ - For manipulating IFWI `C` -* __cbmem__ - Cbmem console log reader `C` +* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` * __checklist__ - Board implementation checklist generator `Make` * __chromeos__ - These scripts can be used to extract System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) -- To view, visit https://review.coreboot.org/c/coreboot/+/31653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Gerrit-Change-Number: 31653 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: mb/google/sarien: Set CPU boot up mode to turbo
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30446 Change subject: mb/google/sarien: Set CPU boot up mode to turbo ...................................................................... mb/google/sarien: Set CPU boot up mode to turbo Set CPU to be running at non-turbo maxium speed first and then switch to turbo maxium speed to accelerate boot performance. BUG=N/A TEST=Boot up with sarien platform, check with cbmem -t, boot time had been 110ms less. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30446/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52840de..ce83d10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -24,6 +24,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc..98566f1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -28,6 +28,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 Gerrit-Change-Number: 30446 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445 Change subject: soc/intel/cannonlake: Add option for boot frquency ...................................................................... soc/intel/cannonlake: Add option for boot frquency Cannonlake/Coffeelake FSP have options for CPU boot up frequency selection, expose that in coreboot side. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..7e50a73 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -110,6 +110,11 @@ SaGv_Enabled, } SaGv; + /* Boot Frequency from reset vector. + * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2: + * Maximum turbo performance @note If 2 is selected, system will start + * with non-turbo mode and then switch to turbo. */ + uint8_t bootfreq; /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509..0514844 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -54,6 +54,8 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + m_cfg->BootFrequency = config->bootfreq; + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 Gerrit-Change-Number: 30445 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/model_1067x: Don't try to apply MCU a second time
by Nico Huber (Code Review) 28 Feb '19

28 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31665 Change subject: cpu/intel/model_1067x: Don't try to apply MCU a second time ...................................................................... cpu/intel/model_1067x: Don't try to apply MCU a second time Applying microcode updates a second time seems to be only necessary on newer platforms (Nehalem+) for "uncore" updates. Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31665/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index b8b3159..4b67893 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -85,9 +85,6 @@ /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); } static void post_mp_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384 Gerrit-Change-Number: 31665 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/sarien: ALC3204 HDA verb table pin config change
by Joyce Toh (Code Review) 28 Feb '19

28 Feb '19

Joyce Toh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31624 Change subject: mb/google/sarien: ALC3204 HDA verb table pin config change ...................................................................... mb/google/sarien: ALC3204 HDA verb table pin config change On Sarien, change pin config of 0x19 (headset mic) and 0x21(headset headphone) to change jack location so that naming does not use "Front" in the name."Front Headphone" --> "Headphone" so it matches naming on Arcada. BUG=b:126334749 TEST= build coreboot with change and verify with 'evtest' command that jack name is "HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone". Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Signed-off-by: Joyce Toh <joyce.toh(a)intel.com> --- M src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31624/1 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h index 52ebb48..6eb6d14 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h @@ -34,12 +34,12 @@ AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x02a11030), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001), AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x02211020), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), /* ALC3204 default-1 */ 0x02050040, -- To view, visit https://review.coreboot.org/c/coreboot/+/31624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Gerrit-Change-Number: 31624 Gerrit-PatchSet: 1 Gerrit-Owner: Joyce Toh <joyce.toh(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: rmodule: Add support for R_X86_64_PLT32
by Aaron Durbin (Code Review) 28 Feb '19

28 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31468 ) Change subject: rmodule: Add support for R_X86_64_PLT32 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31468/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31468/2//COMMIT_MSG@13 PS2, Line 13: R_X86_64_PLT32 > I tried to disable it, but it's not possible. […] That's helpful context here. Can you please include it and elaborate in the commit description? -- To view, visit https://review.coreboot.org/c/coreboot/+/31468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81350d2728c20ac72cc865e7ba92319858352632 Gerrit-Change-Number: 31468 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Feb 2019 18:20:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: rmodule: Add support for R_X86_64_PLT32
by Patrick Rudolph (Code Review) 28 Feb '19

28 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31468 ) Change subject: rmodule: Add support for R_X86_64_PLT32 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31468/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31468/2//COMMIT_MSG@13 PS2, Line 13: R_X86_64_PLT32 > I'm not sure we should be allowing the compiler/linker to emit these relocations. […] I tried to disable it, but it's not possible. It's tested on qemu and works fine. It's also done here: https://lists.gnu.org/archive/html/grub-devel/2018-02/msg00064.html or here https://lore.kernel.org/patchwork/patch/895855/ -- To view, visit https://review.coreboot.org/c/coreboot/+/31468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81350d2728c20ac72cc865e7ba92319858352632 Gerrit-Change-Number: 31468 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Feb 2019 18:18:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2019