coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Update ACPI table's revision numbers
by Martin Roth (Code Review) 28 Feb '19

28 Feb '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29579 ) Change subject: src/arch/x86/acpi.c: Update ACPI table's revision numbers ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Gerrit-Change-Number: 29579 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 17:00:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by Martin Roth (Code Review) 28 Feb '19

28 Feb '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29986 ) Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 16:58:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by HAOUAS Elyes (Code Review) 28 Feb '19

28 Feb '19

Hello Alexander Couzens, Patrick Rudolph, David Guckian, Vanessa Eusebio, Huang Jin, York Yang, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29986 to look at the new patch set (#5). Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... ACPI: Rename FADT model and set it to zero INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using greater version than ACPI 1.0. Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 26 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29986/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by HAOUAS Elyes (Code Review) 28 Feb '19

28 Feb '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29986 ) Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29986/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29986/4//COMMIT_MSG@12 PS4, Line 12: So set this value to zero as we are using greater version than ACPI 1.0 > Please add a dot/period at the end of the sentence. Done. Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 16:36:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Nico Huber (Code Review) 28 Feb '19

28 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ? IIRC, the original problem was that the current coreboot source is incompatible with the upstream headers (because UPDs were added that are unknown to Intel?). -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Feb 2019 16:32:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by Paul Menzel (Code Review) 28 Feb '19

28 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29986 ) Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... Patch Set 4: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/29986/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29986/4//COMMIT_MSG@11 PS4, Line 11: compatibility with ACPI 1.0. Please add a blank line below. https://review.coreboot.org/#/c/29986/4//COMMIT_MSG@12 PS4, Line 12: So set this value to zero as we are using greater version than ACPI 1.0 Please add a dot/period at the end of the sentence. -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 16:29:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 28 Feb '19

28 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 60: (9 comments) https://review.coreboot.org/#/c/29563/60/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/60/src/include/memlayout.h@167 PS60, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/60/src/include/memlayout.h@167 PS60, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@94 PS60, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@156 PS60, Line 156: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@157 PS60, Line 157: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@160 PS60, Line 160: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@165 PS60, Line 165: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@166 PS60, Line 166: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/60/src/security/tpm/tspi/log.c@167 PS60, Line 167: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 60 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 16:00:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 28 Feb '19

28 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#60). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A Documentation/security/index.md M Documentation/security/vboot/measured_boot.md M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 20 files changed, 366 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/60 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 60 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: console: Add timestamp prints to boot stages.
by Tim Wawrzynczak (Code Review) 28 Feb '19

28 Feb '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31649 Change subject: console: Add timestamp prints to boot stages. ...................................................................... console: Add timestamp prints to boot stages. When a new bootstage starts, if it has console support and the RTC enabled, the current RTC timestamp will be printed. Change-Id: I27676ceac8bccc56ac3d775915f217c8b3c47f4d Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/console/init.c M src/drivers/pc80/rtc/Makefile.inc M src/lib/Makefile.inc 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31649/1 diff --git a/src/console/init.c b/src/console/init.c index 7d1f31a..630478a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -21,6 +21,7 @@ #include <device/pci.h> #include <option.h> #include <version.h> +#include <rtc.h> /* Mutable console log level only allowed when RAM comes online. */ #if defined(__PRE_RAM__) @@ -84,4 +85,10 @@ printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", coreboot_version, coreboot_extra_version, coreboot_build, get_log_level()); + +#if IS_ENABLED(CONFIG_RTC) + struct rtc_time tm; + if (!rtc_get(&tm)) + rtc_display(&tm); +#endif } diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 998b7e7..9047536 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -7,6 +7,14 @@ ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +bootblock-$(CONFIG_RTC) += mc146818rtc_boot.c +bootblock-$(CONFIG_RTC) += mc146818rtc.c +postcar-$(CONFIG_RTC) += mc146818rtc.c +romstage-$(CONFIG_RTC) += mc146818rtc.c +ramstage-$(CONFIG_RTC) += mc146818rtc.c +smm-$(CONFIG_RTC) += mc146818rtc.c +verstage-$(CONFIG_RTC) += mc146818rtc.c + ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index fa1ff8b..86a17b2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -36,6 +36,10 @@ bootblock-y += bootblock.c endif +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_RTC) += rtc.c +endif + bootblock-y += prog_loaders.c bootblock-y += prog_ops.c bootblock-y += cbfs.c @@ -66,6 +70,7 @@ verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +verstage-$(CONFIG_RTC) += rtc.c romstage-y += prog_loaders.c romstage-y += prog_ops.c @@ -109,6 +114,8 @@ romstage-$(CONFIG_GENERIC_UDELAY) += timer.c +romstage-$(CONFIG_RTC) += rtc.c + ramstage-y += prog_loaders.c ramstage-y += prog_ops.c ramstage-y += hardwaremain.c @@ -165,6 +172,10 @@ postcar-y += imd.c postcar-y += romstage_handoff.c +ifeq ($(CONFIG_POSTCAR_CONSOLE),y) +postcar-$(CONFIG_RTC) += rtc.c +endif + bootblock-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c @@ -196,6 +207,10 @@ smm-y += cbfs.c memcmp.c smm-$(CONFIG_GENERIC_UDELAY) += timer.c +ifeq ($(CONFIG_DEBUG_SMI),y) +smm-$(CONFIG_RTC) += rtc.c +endif + bootblock-y += version.c romstage-y += version.c ramstage-y += version.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27676ceac8bccc56ac3d775915f217c8b3c47f4d Gerrit-Change-Number: 31649 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 28 Feb '19

28 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 59: (9 comments) https://review.coreboot.org/#/c/29563/59/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/59/src/include/memlayout.h@167 PS59, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/59/src/include/memlayout.h@167 PS59, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@94 PS59, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@156 PS59, Line 156: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@157 PS59, Line 157: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@160 PS59, Line 160: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@165 PS59, Line 165: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@166 PS59, Line 166: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/59/src/security/tpm/tspi/log.c@167 PS59, Line 167: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 59 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:56:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019