coreboot-gerrit February 2019

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Change in ...coreboot[master]: src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all ...
by Patrick Georgi (Code Review) 28 Feb '19

28 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29287 ) Change subject: src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all LNKx ...................................................................... src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all LNKx IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates. These interrupt numbers are added to all LNKx. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/29287 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/braswell/acpi/irqlinks.asl 1 file changed, 9 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Michał Żygowski: Looks good to me, approved diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index a160f6e..a943c88a 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -29,7 +30,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -88,7 +89,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -147,7 +148,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -206,7 +207,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -265,7 +266,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -324,7 +325,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -383,7 +384,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ @@ -442,7 +443,7 @@ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) /* Current Resource Settings for this link */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604 Gerrit-Change-Number: 29287 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: wvervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/soc/intel/braswell/hda.c: Configure HDA codecs
by Frans Hendriks (Code Review) 28 Feb '19

28 Feb '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 ) Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs ...................................................................... Patch Set 12: > Patch Set 12: > > wouldn't it be easier to use soc/intel/common/block/hda/hda.c by using > "select SOC_INTEL_COMMON_BLOCK_HDA" and adding the braswell PCI ID ? Agree, -- To view, visit https://review.coreboot.org/c/coreboot/+/29394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Gerrit-Change-Number: 29394 Gerrit-PatchSet: 12 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 28 Feb 2019 14:14:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/mtrr/mtrr.c:Avoid static scan false positive
by Richard Spiegel (Code Review) 28 Feb '19

28 Feb '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31527 Change subject: cpu/x86/mtrr/mtrr.c:Avoid static scan false positive ...................................................................... cpu/x86/mtrr/mtrr.c:Avoid static scan false positive Static scan does not know the contents of the fixed MTRR descriptor, so it has no way to eval the result for variable num_ranges. If num_ranges is less or equal to 0, the for loop will not be entered, and the values of fixed_msrs will not be set. Asserting that num_ranges is greater than 0 ensures the loop enters at least once. BUG=b:112253891 TEST=build grunt Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31527/1 diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 23473df..3b23926 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -36,6 +36,7 @@ #include <arch/acpi.h> #include <memrange.h> #include <cpu/amd/mtrr.h> +#include <assert.h> #if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) #else @@ -331,6 +332,7 @@ desc = &fixed_mtrr_desc[i]; num_ranges = (desc->end - desc->begin) / desc->step; + ASSERT (num_ranges > 0); for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { msr_index[msr_num] = desc->msr_index_base + (j / RANGES_PER_FIXED_MTRR); -- To view, visit https://review.coreboot.org/c/coreboot/+/31527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77 Gerrit-Change-Number: 31527 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: cbfs: Check decompressed size when loading files.
by You-Cheng Syu (Code Review) 28 Feb '19

28 Feb '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31564 Change subject: libpayload: cbfs: Check decompressed size when loading files. ...................................................................... libpayload: cbfs: Check decompressed size when loading files. After loading compressed files in CBFS, we should check the decompressed size is equal to the expected size. This might help us detect file content corruption or compressor/decompressor bugs. BUG=none BRANCH=none TEST=boot into kernel on kukui Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M payloads/libpayload/libcbfs/cbfs_core.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31564/1 diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 91f2603..e234214 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -256,7 +256,7 @@ return NULL; ret = malloc(*size); - if (ret != NULL && !cbfs_decompress(algo, data, ret, *size)) { + if (ret != NULL && cbfs_decompress(algo, data, ret, *size) != *size) { free(ret); ret = NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795 Gerrit-Change-Number: 31564 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: cbfs: Require input size and output size for cbfs_decompress
by You-Cheng Syu (Code Review) 28 Feb '19

28 Feb '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31606 Change subject: libpayload: cbfs: Require input size and output size for cbfs_decompress ...................................................................... libpayload: cbfs: Require input size and output size for cbfs_decompress Currently, cbfs_decompress() calls ulzma() and ulz4f() for LZMA/LZ4 decompression. These two functions don't accept input/output size as parameters. We can make cbfs_decompress more robust by calling ulzman() and ulz4fn() instead. This could prevent us from overflowing destination buffer. BUG=none BRANCH=none TEST=boot into kernel on Kukui with COMPRESSED_PAYLOAD_LZMA / COMPRESSED_PAYLOAD_LZ4. Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M payloads/libpayload/include/cbfs_core.h M payloads/libpayload/libcbfs/cbfs.c M payloads/libpayload/libcbfs/cbfs_core.c 3 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31606/1 diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 364f6c4..0206f5e 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -253,8 +253,8 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz); -/* returns decompressed size on success, 0 on failure */ -int cbfs_decompress(int algo, void *src, void *dst, int len); +/* Returns decompressed size on success, 0 on failure. */ +int cbfs_decompress(int algo, const void *src, int srcn, void *dst, int dstn); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 577fb20..d679e67 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -114,8 +114,9 @@ final_size = cbfs_decompress(stage->compression, ((unsigned char *) stage) + sizeof(struct cbfs_stage), + stage->len, (void *) (uintptr_t) stage->load, - stage->len); + stage->memlen); if (!final_size) { entry = -1; goto out; diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 91f2603..75d5e9a 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -48,6 +48,7 @@ * */ +#include <libpayload.h> #include <cbfs.h> #include <string.h> #include <sysinfo.h> @@ -256,7 +257,8 @@ return NULL; ret = malloc(*size); - if (ret != NULL && !cbfs_decompress(algo, data, ret, *size)) { + if (ret != NULL && + !cbfs_decompress(algo, data, on_media_size, ret, *size)) { free(ret); ret = NULL; } @@ -321,23 +323,25 @@ return NULL; } -int cbfs_decompress(int algo, void *src, void *dst, int len) +int cbfs_decompress(int algo, const void *src, int srcn, void *dst, int dstn) { + int len; switch (algo) { case CBFS_COMPRESS_NONE: + len = MIN(srcn, dstn); memcpy(dst, src, len); return len; #ifdef CBFS_CORE_WITH_LZMA case CBFS_COMPRESS_LZMA: - return ulzma(src, dst); + return ulzman(src, srcn, dst, dstn); #endif #ifdef CBFS_CORE_WITH_LZ4 case CBFS_COMPRESS_LZ4: - return ulz4f(src, dst); + return ulz4fn(src, srcn, dst, dstn); #endif default: ERROR("tried to decompress %d bytes with algorithm #%x," - "but that algorithm id is unsupported.\n", len, + "but that algorithm id is unsupported.\n", srcn, algo); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33 Gerrit-Change-Number: 31606 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel: Remove socket_BGA1284
by Nico Huber (Code Review) 28 Feb '19

28 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31646 Change subject: cpu/intel: Remove socket_BGA1284 ...................................................................... cpu/intel: Remove socket_BGA1284 Unused since the removal of `fsp_sandybridge`. Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/Makefile.inc D src/cpu/intel/socket_BGA1284/Kconfig D src/cpu/intel/socket_BGA1284/Makefile.inc 3 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31646/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 9535262..73a8bf8 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -6,7 +6,6 @@ subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p diff --git a/src/cpu/intel/socket_BGA1284/Kconfig b/src/cpu/intel/socket_BGA1284/Kconfig deleted file mode 100644 index 402dc5c..0000000 --- a/src/cpu/intel/socket_BGA1284/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -config CPU_INTEL_SOCKET_BGA1284 - bool - -if CPU_INTEL_SOCKET_BGA1284 - -config SOCKET_SPECIFIC_OPTIONS # dummy - def_bool y - select MMX - select SSE - -endif diff --git a/src/cpu/intel/socket_BGA1284/Makefile.inc b/src/cpu/intel/socket_BGA1284/Makefile.inc deleted file mode 100644 index 539f285..0000000 --- a/src/cpu/intel/socket_BGA1284/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../turbo -- To view, visit https://review.coreboot.org/c/coreboot/+/31646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3 Gerrit-Change-Number: 31646 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel: Rename socket_mPGA478MN to socket_p
by Patrick Georgi (Code Review) 28 Feb '19

28 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31645 ) Change subject: cpu/intel: Rename socket_mPGA478MN to socket_p ...................................................................... cpu/intel: Rename socket_mPGA478MN to socket_p These marketing names are much easier to distinguish. My mnemonic: Socket M => up to Merom, Socket P => up to Penryn. Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/31645 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc R src/cpu/intel/socket_p/Kconfig R src/cpu/intel/socket_p/Makefile.inc M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/devicetree.cb 6 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index f88e631..10f7ad4 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -21,7 +21,7 @@ source src/cpu/intel/socket_BGA1284/Kconfig source src/cpu/intel/socket_FCBGA559/Kconfig source src/cpu/intel/socket_m/Kconfig -source src/cpu/intel/socket_mPGA478MN/Kconfig +source src/cpu/intel/socket_p/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA775/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index e4d3f84..9535262 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -9,7 +9,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m -subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN +subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_p/Kconfig similarity index 74% rename from src/cpu/intel/socket_mPGA478MN/Kconfig rename to src/cpu/intel/socket_p/Kconfig index 7d97022..0ec9ced 100644 --- a/src/cpu/intel/socket_mPGA478MN/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -1,11 +1,11 @@ -config CPU_INTEL_SOCKET_MPGA478MN +config CPU_INTEL_SOCKET_P bool select CPU_INTEL_MODEL_1067X select CPU_INTEL_MODEL_6FX select MMX select SSE -if CPU_INTEL_SOCKET_MPGA478MN +if CPU_INTEL_SOCKET_P config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc similarity index 100% rename from src/cpu/intel/socket_mPGA478MN/Makefile.inc rename to src/cpu/intel/socket_p/Makefile.inc diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index ab5818f..57e31f2 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MPGA478MN + select CPU_INTEL_SOCKET_P select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 4e88e27..8e90431 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -6,7 +6,7 @@ register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on - chip cpu/intel/socket_mPGA478MN + chip cpu/intel/socket_p device lapic 0 on end end chip cpu/intel/model_1067x -- To view, visit https://review.coreboot.org/c/coreboot/+/31645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Gerrit-Change-Number: 31645 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel: Remove models 69x and 6dx
by Patrick Georgi (Code Review) 28 Feb '19

28 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31644 ) Change subject: cpu/intel: Remove models 69x and 6dx ...................................................................... cpu/intel: Remove models 69x and 6dx These came for the Socket 479 which is not supported anymore. Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/31644 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/Kconfig D src/cpu/intel/model_69x/Kconfig D src/cpu/intel/model_69x/Makefile.inc D src/cpu/intel/model_69x/model_69x_init.c D src/cpu/intel/model_6dx/Kconfig D src/cpu/intel/model_6dx/Makefile.inc D src/cpu/intel/model_6dx/model_6dx_init.c 7 files changed, 0 insertions(+), 121 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index bdf5b54..f88e631 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -3,9 +3,7 @@ source src/cpu/intel/model_65x/Kconfig source src/cpu/intel/model_67x/Kconfig source src/cpu/intel/model_68x/Kconfig -source src/cpu/intel/model_69x/Kconfig source src/cpu/intel/model_6bx/Kconfig -source src/cpu/intel/model_6dx/Kconfig source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig deleted file mode 100644 index ff1d5e2..0000000 --- a/src/cpu/intel/model_69x/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CPU_INTEL_MODEL_69X - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc deleted file mode 100644 index 7bf028c..0000000 --- a/src/cpu/intel/model_69x/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -ramstage-y += model_69x_init.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c deleted file mode 100644 index fe7d2ca..0000000 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> - -static void model_69x_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_69x_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */ - { X86_VENDOR_INTEL, 0x0695 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig deleted file mode 100644 index edbeac8..0000000 --- a/src/cpu/intel/model_6dx/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CPU_INTEL_MODEL_6DX - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc deleted file mode 100644 index 92985ea..0000000 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -ramstage-y += model_6dx_init.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c deleted file mode 100644 index 337b613..0000000 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> - -static void model_6dx_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_6dx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - /* Pentium M on 90nm with 2MiB of L2 cache */ - { X86_VENDOR_INTEL, 0x06D0 }, - { X86_VENDOR_INTEL, 0x06D6 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1 Gerrit-Change-Number: 31644 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: cpu/intel/socket_m: Remove models 69x and 6dx
by Nico Huber (Code Review) 28 Feb '19

28 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31643 Change subject: cpu/intel/socket_m: Remove models 69x and 6dx ...................................................................... cpu/intel/socket_m: Remove models 69x and 6dx These sneaked in and were never supported by this socket (nor expected in the notebooks that have it). Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_m/Makefile.inc 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31643/1 diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index aadc9a4..02330f9 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -5,8 +5,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_MODEL_69X - select CPU_INTEL_MODEL_6DX select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX select MMX diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 139b1bb..96f16dc 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -1,5 +1,3 @@ -subdirs-y += ../model_69x -subdirs-y += ../model_6dx subdirs-y += ../model_6ex subdirs-y += ../model_6fx subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/31643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2 Gerrit-Change-Number: 31643 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: cpu/intel: Rename socket_mFCPGA478 to socket_m
by Nico Huber (Code Review) 28 Feb '19

28 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31642 Change subject: cpu/intel: Rename socket_mFCPGA478 to socket_m ...................................................................... cpu/intel: Rename socket_mFCPGA478 to socket_m The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN, the successor of the socket that was meant. The official name of this socket is mPGA478MT. But "Socket M" is much easier to distinguish. Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc R src/cpu/intel/socket_m/Kconfig R src/cpu/intel/socket_m/Makefile.inc M src/mainboard/apple/macbook21/Kconfig M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/getac/p470/Kconfig M src/mainboard/getac/p470/devicetree.cb M src/mainboard/ibase/mb899/Kconfig M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/kontron/986lcd-m/Kconfig M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/lenovo/z61t/Kconfig M src/mainboard/lenovo/z61t/devicetree.cb M src/mainboard/roda/rk886ex/Kconfig M src/mainboard/roda/rk886ex/devicetree.cb M util/docker/coreboot.org-status/board-status.html/tohtml.sh 21 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31642/1 diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 4fd8efb..bdf5b54 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -22,7 +22,7 @@ source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_BGA1284/Kconfig source src/cpu/intel/socket_FCBGA559/Kconfig -source src/cpu/intel/socket_mFCPGA478/Kconfig +source src/cpu/intel/socket_m/Kconfig source src/cpu/intel/socket_mPGA478MN/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_441/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 3ed3297..e4d3f84 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -8,7 +8,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_m/Kconfig similarity index 82% rename from src/cpu/intel/socket_mFCPGA478/Kconfig rename to src/cpu/intel/socket_m/Kconfig index 503ad64..aadc9a4 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -1,7 +1,7 @@ -config CPU_INTEL_SOCKET_MFCPGA478 +config CPU_INTEL_SOCKET_M bool -if CPU_INTEL_SOCKET_MFCPGA478 +if CPU_INTEL_SOCKET_M config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc similarity index 100% rename from src/cpu/intel/socket_mFCPGA478/Makefile.inc rename to src/cpu/intel/socket_m/Makefile.inc diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index d60130b..6535f8f 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -4,7 +4,7 @@ def_bool y select SYSTEM_TYPE_LAPTOP select ARCH_X86 - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 898aae4..9da3891 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,7 +30,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 7a6b996..a5eed1a 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index a81ef3a..c0cad6a 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -20,7 +20,7 @@ register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index ba510fa..621395d 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -2,7 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3544c96..f81a68b 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -4,7 +4,7 @@ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 4b9f526..43bdf14 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -2,7 +2,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 06f29e0..5e00109 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -4,7 +4,7 @@ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bb43557..a6a88b3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7b1721e..b4c8fb8 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,7 +30,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 36fbe6c..6db7f11 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2a60b87..87cfa84 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,7 +30,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index 9aa6350..a223077 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 92bf3ce..8519b31 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -30,7 +30,7 @@ register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 9f4af85..821a9a1 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_M select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index ec42766..082a9e8 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -20,7 +20,7 @@ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 + chip cpu/intel/socket_m device lapic 0 on end end end diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index f786c33..1992826 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -323,9 +323,9 @@ INTEL_SOCKET_MPGA604) cpu_nice="Intel® Xeon®"; socket_nice="Socket 604";; - INTEL_SOCKET_MFCPGA478) + INTEL_SOCKET_M) cpu_nice="Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M"; - socket_nice="Socket mPGA478";; + socket_nice="Socket M (mPGA478MT)";; INTEL_SOCKET_LGA771) cpu_nice="Intel Xeon™ 5000 series"; socket_nice="Socket LGA771";; -- To view, visit https://review.coreboot.org/c/coreboot/+/31642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Gerrit-Change-Number: 31642 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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