Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29333 )
Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area
......................................................................
Patch Set 4: Code-Review+2
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Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29394
to look at the new patch set (#12).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add:
- hda_enable()
- hda_init()
hda_enable() will disable the HDA controller when
controllered is not used.
hda_init() will detect attached codecs and configure the codecs
using cim_verb_data[].
Based on Intel Broadwell (intel/broadwell/hda.c) implementation.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
7 files changed, 124 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/12
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
> Patch Set 5:
>
> > Patch Set 5:
> >
> > Maybe we should ping Intel to do something about it. Changing the signature just like that made the coreboot builds for Braswell boards useless if someone have built their image with latest FSP from the fsp submodule. The FSP binary should at least remain the same signature.
>
> MR2 release is almost 3 years old. Would not expect Intel to perform updates on this.
>
> The problem is that coreboot expects the 'old' signature and the third party FSP is based on MR2. Not sure which FSP is used on which mainboard. For this reason add config. If developer wants using latest FSP (signature) the config value must be enabled.
But if the signature could remain the same, coreboot would require only version bumping. I did not mean anything else. The Kconfig option works as expected.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
> Patch Set 5:
>
> Maybe we should ping Intel to do something about it. Changing the signature just like that made the coreboot builds for Braswell boards useless if someone have built their image with latest FSP from the fsp submodule. The FSP binary should at least remain the same signature.
MR2 release is almost 3 years old. Would not expect Intel to perform updates on this.
The problem is that coreboot expects the 'old' signature and the third party FSP is based on MR2. Not sure which FSP is used on which mainboard. For this reason add config. If developer wants using latest FSP (signature) the config value must be enabled.
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Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/22604
to look at the new patch set (#72).
Change subject: cpu/intel/speedstep: Add Netburst
......................................................................
cpu/intel/speedstep: Add Netburst
CPUs Netburst CPUs hang if we read MSR_PLATFORM_INFO or
MSR_EXTENDED_CONFIG. The maximum bus ratio can be read
in MSR_PERF_STAT[44:40]
Tested with P4 (CPUID F65) on 945G-M4 board.
Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/intel/speedstep/speedstep.c
1 file changed, 31 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22604/72
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
Patch Set 11:
> Patch Set 8:
>
> (2 comments)
>
> Did you copy this from some other device?
Yes, from Intel Broadwell. Have added this to comment
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Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29394
to look at the new patch set (#11).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add:
- hda_enable()
- hda_init()
hda_enable() will disable the HDA controller when
controllered is not used.
hda_init() will detect attached codecs and configure the codecs
using cim_verb_data[].
Based on intel/broadwell/hda.c implementation.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
7 files changed, 124 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/11
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG@10
PS8, Line 10: Added
> Add
Done
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG@15
PS8, Line 15: TEST=Intel CherryHill CRB
> Please add more details.
Done
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