Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29969 )
Change subject: qcs405: memlayout: Make bootblock 64k aligned
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Patch Set 13:
(1 comment)
https://review.coreboot.org/#/c/29969/13//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29969/13//COMMIT_MSG@9
PS13, Line 9: The qc_sec in qcs405 excepts that bootblock to be 64k aligned. So
Where does this requirement come from? SDM845 doesn't have that, so why does QCS405 need it? Can QC-SEC be fixed to not require this instead?
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29971 )
Change subject: qcs405: Clear bss for bootblock
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Patch Set 13:
> I was considering whether this should be hidden behind a kconfig flag, but I doubt that there will be bootblocks on arm64 with "huge" bss sections where it would matter. Julius, any opinion on that?
This is not needed. The bootblock is linked treated as a binary image where all the .bss is already included in the .data section, so it does not need to be initialized separately. I assume this patch was just cherry-picked from an early version of Cheza code before I told them the same thing -- if you follow the Makefile stuff from more recent Cheza patches, this shouldn't be necessary anymore.
As a separate problem to the immediate question of how to get Mistral to work, I'd be open to discussing whether we want to generally switch to self-cleared bootblock .bss (and not including it in the BootROM-loaded binary) on all Arm devices. There are some advantages to that although I don't think it's a big problem in general (especially if you're using COMPRESS_BOOTBLOCK). However, if we want to do that it needs to be done in a way that works on and benefits all platforms.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29949 )
Change subject: mainboard/google/mistral: Add support for Mistral
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Patch Set 11:
(1 comment)
https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/chrome…
File src/mainboard/google/mistral/chromeos.fmd:
https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/chrome…
PS2, Line 38: RW_XBL_BUFFER_A@0x1E8000 0x4000
> Ok. Infact we were asked to have the same FMAP layout as in Gale […]
I would suggest you orient yourself on the Cheza layout, since Gale is very old and many things in there may be outdated. I assume you can drop the RO_FSG section from Cheza if you don't need that and then maybe shuffle the other WP_RO parts around a bit to make more of the resulting free space usable in the COREBOOT section, but otherwise it should fit pretty well for you. (In particular, unless memory training somehow works significantly different for you than for SDM845, I suggest you stick to the model we developed for Cheza with one RO and only one (probably unused) RW section -- you can refer to T.mike for details.)
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