Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29394
to look at the new patch set (#10).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add:
- hda_enable()
- hda_init()
hda_enable() will disable the HDA controller when
controllered is not used.
hda_init() will detect attached codecs and configure the codecs
using cim_verb_data[].
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
7 files changed, 124 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/10
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Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29394
to look at the new patch set (#9).
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
src/soc/intel/braswell/hda.c: Configure HDA codecs
The support of the HDA did not configure the codecs.
Add:
- hda_enable()
- hda_init()
The function hda_enable() will disable the HDA controller when
controllered is not used.
In hda_init() will detect attached codecs and configure the codecs
using cim_verb_data[].
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/hda_verb.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/hda_verb.c
M src/soc/intel/braswell/hda.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/southcluster.c
7 files changed, 124 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/9
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29664 )
Change subject: mb/google/poppy/variants/atlas: enable eist
......................................................................
Patch Set 2: Code-Review+1
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29290 )
Change subject: src/soc/intel/braswell/cpu.c: Setup local APIC
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG@7
PS2, Line 7: Setup
Set up
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG@13
PS2, Line 13: Ubuntu
With what Linux kernel?
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29423 )
Change subject: soc/intel/braswell: Configure IO APIC
......................................................................
Patch Set 6: Code-Review+2
Tested on Intel Celeron J3060 and J3160 by booting Debian. IO APIC is required for proper operation of SeaBIOS and OS.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
Maybe we should ping Intel to do something about it. Changing the signature just like that made the coreboot builds for Braswell boards useless if someone have built their image with latest FSP from the fsp submodule. The FSP binary should at least remain the same signature.
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 )
Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit
......................................................................
Patch Set 15:
> Patch Set 15:
>
> previous comments still apply
You mean the gerrit 'macros with complex values"?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 )
Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
......................................................................
Patch Set 3:
> @Nico/Patrick: Can you please reconsider your -1 on this CL?
Why? A -1 merely states that we'd prefer something else. It's
no problem to merge something with -1, especially not in a
situation like this with FSP involved. I assume that you have
to work with what you get from the people building FSP.
If you want, you can take the -1 as a reminder to tell those
people that they are dragging Intel down. (I mean, if I built
something with the wrong numbers, I'd just rebuild it when
somebody tells me about it. But that'd probably just be me.)
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
Patch Set 8:
(2 comments)
Did you copy this from some other device?
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG@10
PS8, Line 10: Added
Add
https://review.coreboot.org/#/c/29394/8//COMMIT_MSG@15
PS8, Line 15: TEST=Intel CherryHill CRB
Please add more details.
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