Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ?
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David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29986 )
Change subject: ACPI: Rename FADT model and set it to zero
......................................................................
Patch Set 4: Code-Review+1
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Hello Alexander Couzens, Patrick Rudolph, Vanessa Eusebio, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29986
to look at the new patch set (#4).
Change subject: ACPI: Rename FADT model and set it to zero
......................................................................
ACPI: Rename FADT model and set it to zero
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/x86/include/arch/acpi.h
M src/mainboard/aopen/dxplplusu/fadt.c
M src/mainboard/emulation/qemu-q35/acpi_tables.c
M src/mainboard/google/auron/fadt.c
M src/mainboard/google/cyan/fadt.c
M src/mainboard/google/jecht/fadt.c
M src/mainboard/google/rambi/fadt.c
M src/mainboard/intel/harcuvar/fadt.c
M src/mainboard/intel/strago/fadt.c
M src/mainboard/intel/wtm2/fadt.c
M src/mainboard/lenovo/t400/fadt.c
M src/mainboard/lenovo/x200/fadt.c
M src/mainboard/purism/librem_bdw/fadt.c
M src/mainboard/roda/rk9/fadt.c
M src/mainboard/scaleway/tagada/fadt.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/cimx/sb800/fadt.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
26 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29986/4
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs
......................................................................
Patch Set 12:
wouldn't it be easier to use soc/intel/common/block/hda/hda.c by using
"select SOC_INTEL_COMMON_BLOCK_HDA" and adding the braswell PCI ID ?
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Hello Alexander Couzens, Patrick Rudolph, Vanessa Eusebio, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29986
to look at the new patch set (#3).
Change subject: ACPI: Rename FADT model and set it to zero
......................................................................
ACPI: Rename FADT model and set it to zero
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/arch/x86/include/arch/acpi.h
M src/mainboard/aopen/dxplplusu/fadt.c
M src/mainboard/emulation/qemu-q35/acpi_tables.c
M src/mainboard/google/auron/fadt.c
M src/mainboard/google/cyan/fadt.c
M src/mainboard/google/jecht/fadt.c
M src/mainboard/google/rambi/fadt.c
M src/mainboard/intel/harcuvar/fadt.c
M src/mainboard/intel/strago/fadt.c
M src/mainboard/intel/wtm2/fadt.c
M src/mainboard/lenovo/t400/fadt.c
M src/mainboard/lenovo/x200/fadt.c
M src/mainboard/purism/librem_bdw/fadt.c
M src/mainboard/roda/rk9/fadt.c
M src/mainboard/scaleway/tagada/fadt.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/southbridge/amd/agesa/hudson/fadt.c
M src/southbridge/amd/cimx/sb800/fadt.c
M src/southbridge/amd/pi/hudson/fadt.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
25 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29986/3
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HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29986 )
Change subject: ACPI: Rename FADT model and set it to zero
......................................................................
Restored
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29290 )
Change subject: src/soc/intel/braswell/cpu.c: Set up local APIC
......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG@7
PS2, Line 7: Setup
> Set up
Done
https://review.coreboot.org/#/c/29290/2//COMMIT_MSG@13
PS2, Line 13: Ubuntu
> With what Linux kernel?
Tested with 4.15.0. Will add this to comment
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Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29290
to look at the new patch set (#3).
Change subject: src/soc/intel/braswell/cpu.c: Set up local APIC
......................................................................
src/soc/intel/braswell/cpu.c: Set up local APIC
Local APIC was not configured.
Add setup_lapic() to configure the APIC.
BUG=N/A
TEST= Ubuntu 4.15.0 reports correct local APIC information
on Intel CherryHill CRB
Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/soc/intel/braswell/cpu.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29290/3
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 )
Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig
File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig@137
PS5, Line 137:
: config ENABLE_SERIRQ
: bool "Enable Serial IRQ"
: default n
: help
: Enable Serial IRQ
:
: config SERIRQ_CONTINUOUS_MODE
: bool "Serial IRQ continuous mode"
: default n
: depends on ENABLE_SERIRQ
: help
: Enable Serial IRQ continuous mode
> Do Chromebooks want to have the SERIRQ disabled as it was in the 'old' code base? Most coreboot boar […]
In 'old' code base it was disabled, so to avoid causing problems when SERIRQ becomes enabled this feature is default disabled.
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