coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 28 Feb '19

28 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 58: (9 comments) https://review.coreboot.org/#/c/29563/58/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/58/src/include/memlayout.h@167 PS58, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/58/src/include/memlayout.h@167 PS58, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@94 PS58, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@156 PS58, Line 156: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@157 PS58, Line 157: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@160 PS58, Line 160: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@165 PS58, Line 165: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@166 PS58, Line 166: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/58/src/security/tpm/tspi/log.c@167 PS58, Line 167: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 58 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:45:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 28 Feb '19

28 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#58). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A Documentation/security/index.md M Documentation/security/vboot/measured_boot.md M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 20 files changed, 366 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 58 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 28 Feb '19

28 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 57: (9 comments) https://review.coreboot.org/#/c/29563/57/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/57/src/include/memlayout.h@167 PS57, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/57/src/include/memlayout.h@167 PS57, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@94 PS57, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@156 PS57, Line 156: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@157 PS57, Line 157: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@160 PS57, Line 160: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@165 PS57, Line 165: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@166 PS57, Line 166: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/57/src/security/tpm/tspi/log.c@167 PS57, Line 167: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 57 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 28 Feb '19

28 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 56: (9 comments) https://review.coreboot.org/#/c/29563/56/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/56/src/include/memlayout.h@167 PS56, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/56/src/include/memlayout.h@167 PS56, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@94 PS56, Line 94: enum vb2_hash_algorithm digest_algo, const uint8_t *digest, line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@156 PS56, Line 156: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@157 PS56, Line 157: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@160 PS56, Line 160: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@165 PS56, Line 165: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@166 PS56, Line 166: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/56/src/security/tpm/tspi/log.c@167 PS56, Line 167: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 56 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:41:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 28 Feb '19

28 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#56). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A Documentation/security/index.md M Documentation/security/vboot/measured_boot.md M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 20 files changed, 366 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 56 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Michał Żygowski (Code Review) 28 Feb '19

28 Feb '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > > Patch Set 5: > > > > > > > Patch Set 5: > > > > > > > > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ? > > > > > > That would solve the problems with different headers. But the binary present in current FSP repo still has different signature and version which needs to be changed in coreboot according to used FSP blob revision, i.e. MR1 or MR2, thus the Kconfig option. > > > > This problem occurs when 3rdparty/fsp is used. This FSP signature is not in sync with coreboot. coreboot expects 'old' signature (used in MR1). > > Does coreboot check the signature of the FSP binary ? If headers and binary from 3rdparty/FSP are used there's no need to check it as it's already in sync, isn't it ? Sorry, my bad. For unknown reason, I have mistakenly thought for a moment that the revision and signature are hardcoded in coreboot. You are right. -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:23:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Patrick Rudolph (Code Review) 28 Feb '19

28 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: > > > > > Patch Set 5: > > > > > > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ? > > > > That would solve the problems with different headers. But the binary present in current FSP repo still has different signature and version which needs to be changed in coreboot according to used FSP blob revision, i.e. MR1 or MR2, thus the Kconfig option. > > This problem occurs when 3rdparty/fsp is used. This FSP signature is not in sync with coreboot. coreboot expects 'old' signature (used in MR1). Does coreboot check the signature of the FSP binary ? If headers and binary from 3rdparty/FSP are used there's no need to check it as it's already in sync, isn't it ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:16:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: rmodule: Add support for R_X86_64_PLT32
by Aaron Durbin (Code Review) 28 Feb '19

28 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31468 ) Change subject: rmodule: Add support for R_X86_64_PLT32 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31468/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31468/2//COMMIT_MSG@13 PS2, Line 13: R_X86_64_PLT32 I'm not sure we should be allowing the compiler/linker to emit these relocations. Is the default truly PC-relative? And w/o plt entries its treated as a normal pc relative? I think some description is warranted because on the surface this doesn't seem appropriate. -- To view, visit https://review.coreboot.org/c/coreboot/+/31468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81350d2728c20ac72cc865e7ba92319858352632 Gerrit-Change-Number: 31468 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: rmodule: Don't emit reloc for R_X86_64_PC64
by Aaron Durbin (Code Review) 28 Feb '19

28 Feb '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31469 ) Change subject: rmodule: Don't emit reloc for R_X86_64_PC64 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122 Gerrit-Change-Number: 31469 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 28 Feb 2019 15:03:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: {src/include},{soc/intel): Configure HDA codecs
by Frans Hendriks (Code Review) 28 Feb '19

28 Feb '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Hannah Williams, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29394 to look at the new patch set (#13). Change subject: {src/include},{soc/intel): Configure HDA codecs ...................................................................... {src/include},{soc/intel): Configure HDA codecs HDA support did not configure the codecs correclty. Use Intel common block support to configure the codecs. To use common Intel HDA support file hda.c file has been removed and Braswell HDA device ID is added to list of supported PCI devices in intel/common/block/hda/hda.c. CONFIG_SOC_INTEL_COMMON_BLOCK and CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled to include hda.c in build. When codec table is available at board level SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled and a codec table must be supplied. BUG=N/A TEST=Facebook FBG-1701 ALC298 configuration Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/include/device/pci_ids.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc D src/soc/intel/braswell/hda.c M src/soc/intel/common/block/hda/hda.c 5 files changed, 5 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29394/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/29394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Gerrit-Change-Number: 29394 Gerrit-PatchSet: 13 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2019