coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: cpu/intel: Rename socket_mPGA478MN to socket_p
by Nico Huber (Code Review) 27 Feb '19

27 Feb '19

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31645 to look at the new patch set (#2). Change subject: cpu/intel: Rename socket_mPGA478MN to socket_p ...................................................................... cpu/intel: Rename socket_mPGA478MN to socket_p These marketing names are much easier to distinguish. My mnemonic: Socket M => up to Merom, Socket P => up to Penryn. Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/intel/Kconfig M src/cpu/intel/Makefile.inc R src/cpu/intel/socket_p/Kconfig R src/cpu/intel/socket_p/Makefile.inc M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/devicetree.cb 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31645/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Gerrit-Change-Number: 31645 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
by Nico Huber (Code Review) 27 Feb '19

27 Feb '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… File src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h: https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 3: Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > >> do you mean that the copyright notice above applies to FSP as a whole and not just this file? […] Ok, but this file proves that part of the CMT FSP release were already published earlier. Then the copyright notice should state each year when parts of it were originally published, IMO. Also, I thought quite the opposite is common practice: that for each file, we track individually when parts of it were published. To make the scope of Intel's copyright notice clear, it would be nice if you could put a line about that above the notice in every file, e.g.: This file is part of the Comet Lake FSP release. Copyright (c) ... Subrata, I hope you don't mind this discussion. I already learned a lot, so I actually appreciate it :) -- To view, visit https://review.coreboot.org/c/coreboot/+/31529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Gerrit-Change-Number: 31529 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 27 Feb 2019 13:57:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: flapjack: use sku_id 0 for un-provisioned board
by Patrick Georgi (Code Review) 27 Feb '19

27 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31623 ) Change subject: flapjack: use sku_id 0 for un-provisioned board ...................................................................... flapjack: use sku_id 0 for un-provisioned board Instead of using 2, 0 is now used for non-CBI provisioned board or corrupted CBI board to confrom to the sku encoding. BUG=b:123676982 BRANCH=kukui TEST=test with un-provisioned board to verify the sku_id. Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Reviewed-on: https://review.coreboot.org/c/31623 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Daisuke Nojiri: Looks good to me, approved diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 2af93c8..b1d6736 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -19,7 +19,8 @@ #include <ec/google/chromeec/ec.h> #include <stddef.h> -#define FLAPJACK_UNDEF_SKU_ID 2 /* For all un-provisioned Flapjack boards */ +/* For CBI un-provisioned/corrupted Flapjack board. */ +#define FLAPJACK_UNDEF_SKU_ID 0 static uint32_t get_index(unsigned int channel, uint32_t *cached_id) { @@ -67,7 +68,7 @@ { static uint32_t cached_sku_id = BOARD_ID_INIT; - /* On Flapjack, getting the SKU via CBI */ + /* On Flapjack, getting the SKU via CBI. */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_FLAPJACK)) { if (cached_sku_id == BOARD_ID_INIT && google_chromeec_cbi_get_sku_id(&cached_sku_id)) -- To view, visit https://review.coreboot.org/c/coreboot/+/31623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Gerrit-Change-Number: 31623 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: flapjack: use sku_id 0 for un-provisioned board
by Patrick Georgi (Code Review) 27 Feb '19

27 Feb '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31623 ) Change subject: flapjack: use sku_id 0 for un-provisioned board ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Gerrit-Change-Number: 31623 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Feb 2019 11:10:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] console: Split loglevel for fast and slow
by Kyösti Mälkki (Code Review) 27 Feb '19

27 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31370 Change subject: [WIP] console: Split loglevel for fast and slow ...................................................................... [WIP] console: Split loglevel for fast and slow For fast CBMEM console use minimum BIOS_DEBUG level. For other consoles, Kconfig and/or nvram settings apply. Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/console.c M src/console/init.c M src/console/printk.c M src/include/console/console.h M src/include/console/streams.h 5 files changed, 38 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31370/1 diff --git a/src/console/console.c b/src/console/console.c index 1a6aec1..73a1937 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -36,9 +36,12 @@ __flashconsole_init(); } -void console_tx_byte(unsigned char byte) +void console_tx_byte_split(int fast_only, unsigned char byte) { __cbmemc_tx_byte(byte); + if (fast_only) + return; + __spkmodem_tx_byte(byte); __qemu_debugcon_tx_byte(byte); @@ -57,8 +60,16 @@ __flashconsole_tx_byte(byte); } -void console_tx_flush(void) +void console_tx_byte(unsigned char byte) { + console_tx_byte_split(0, byte); +} + +void console_tx_flush(int fast_only) +{ + if (fast_only) + return; + __uart_tx_flush(); __ne2k_tx_flush(); __usb_tx_flush(); @@ -67,18 +78,19 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes) { + int fast_only = 0; + /* Finish displaying all of the console data if requested */ if (number_of_bytes == 0) { - console_tx_flush(); + console_tx_flush(fast_only); return; } /* Output the console data */ while (number_of_bytes--) - console_tx_byte(*buffer++); + console_tx_byte_split(fast_only, *buffer++); } - #if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE) void gdb_hw_init(void) { diff --git a/src/console/init.c b/src/console/init.c index 7d1f31a..6640fb8 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -62,11 +62,18 @@ set_log_level(debug_level); } -int console_log_level(int msg_level) +int console_slowlog_level(int msg_level) { return (get_log_level() >= msg_level); } +int console_log_level(int msg_level) +{ + if (car_get_var(console_inited) == 0) + return 0; + return (BIOS_DEBUG >= msg_level); +} + asmlinkage void console_init(void) { init_log_level(); diff --git a/src/console/printk.c b/src/console/printk.c index 735876e..74094fa 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -36,13 +36,14 @@ static void wrap_putchar(unsigned char byte, void *data) { - do_putchar(byte); + int fast_only = *(int *)data; + console_tx_byte_split(fast_only, byte); } int do_printk(int msg_level, const char *fmt, ...) { va_list args; - int i; + int i, fast_only; if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM && !boot_cpu()) @@ -50,6 +51,7 @@ if (!console_log_level(msg_level)) return 0; + fast_only = !console_slowlog_level(msg_level); DISABLE_TRACE; #ifdef __PRE_RAM__ @@ -61,10 +63,10 @@ #endif va_start(args, fmt); - i = vtxprintf(wrap_putchar, fmt, args, NULL); + i = vtxprintf(wrap_putchar, fmt, args, &fast_only); va_end(args); - console_tx_flush(); + console_tx_flush(fast_only); #ifdef __PRE_RAM__ #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) @@ -83,7 +85,8 @@ { if (!console_log_level(msg_level)) return; - vtxprintf(wrap_putchar, fmt, args, NULL); - console_tx_flush(); + int fast_only = !console_slowlog_level(msg_level); + vtxprintf(wrap_putchar, fmt, args, &fast_only); + console_tx_flush(fast_only); } #endif /* CONFIG_VBOOT */ diff --git a/src/include/console/console.h b/src/include/console/console.h index 7ab61ea..91a0c61 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -56,6 +56,7 @@ #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); int console_log_level(int msg_level); +int console_slowlog_level(int msg_level); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); @@ -78,6 +79,7 @@ #else static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } +static inline int console_slowlog_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} static inline void do_putchar(unsigned char byte) {} #endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 6e944a6..051fa08 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -19,7 +19,8 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); -void console_tx_flush(void); +void console_tx_byte_split(int fast_only, unsigned char byte); +void console_tx_flush(int fast_only); /* * Write number_of_bytes data bytes from buffer to the serial device. -- To view, visit https://review.coreboot.org/c/coreboot/+/31370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Gerrit-Change-Number: 31370 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] console: Refactor printk() varargs prototypes
by Kyösti Mälkki (Code Review) 27 Feb '19

27 Feb '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31491 Change subject: [WIP] console: Refactor printk() varargs prototypes ...................................................................... [WIP] console: Refactor printk() varargs prototypes Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/printk.c M src/include/console/console.h 2 files changed, 16 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31491/1 diff --git a/src/console/printk.c b/src/console/printk.c index 735876e..c53f030 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -39,9 +39,8 @@ do_putchar(byte); } -int do_printk(int msg_level, const char *fmt, ...) +int do_printk_va_list(int msg_level, const char *fmt, va_list args) { - va_list args; int i; if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM && @@ -60,9 +59,7 @@ spin_lock(&console_lock); #endif - va_start(args, fmt); i = vtxprintf(wrap_putchar, fmt, args, NULL); - va_end(args); console_tx_flush(); @@ -77,13 +74,3 @@ return i; } - -#if IS_ENABLED(CONFIG_VBOOT) -void do_printk_va_list(int msg_level, const char *fmt, va_list args) -{ - if (!console_log_level(msg_level)) - return; - vtxprintf(wrap_putchar, fmt, args, NULL); - console_tx_flush(); -} -#endif /* CONFIG_VBOOT */ diff --git a/src/include/console/console.h b/src/include/console/console.h index 7ab61ea..bdddc98 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <console/post_codes.h> +#include <console/vtxprintf.h> #include <commonlib/loglevel.h> #define RAM_DEBUG (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER) @@ -56,8 +57,6 @@ #if __CONSOLE_ENABLE__ asmlinkage void console_init(void); int console_log_level(int msg_level); -int do_printk(int msg_level, const char *fmt, ...) - __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ @@ -82,15 +81,20 @@ static inline void do_putchar(unsigned char byte) {} #endif -#if IS_ENABLED(CONFIG_VBOOT) -/* FIXME: Collision of varargs with AMD headers without guard. */ -#include <console/vtxprintf.h> -#if __CONSOLE_ENABLE__ -void do_printk_va_list(int msg_level, const char *fmt, va_list args); -#else -static inline void do_printk_va_list(int l, const char *fmt, va_list args) {} -#endif -#endif +int do_printk_va_list(int msg_level, const char *fmt, va_list args); + +static inline __attribute__((format(printf, 2, 3))) +int do_printk(int msg_level, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = do_printk_va_list(msg_level, fmt, args); + va_end(args); + + return i; +} #endif /* !__ROMCC__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93 Gerrit-Change-Number: 31491 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status passing
by Patrick Georgi (Code Review) 27 Feb '19

27 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status passing ...................................................................... ec/google/chromeec: fix the error status passing Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error -- fixing cbi_get_uint32() and cbi_get_string() so they follow the same convention. BUG=b:123676982 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Reviewed-on: https://review.coreboot.org/c/31585 Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Daisuke Nojiri: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d2a0849..09357b0 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -595,7 +595,7 @@ cmd.cmd_dev_index = 0; rv = google_chromeec_command(&cmd); - if (rv < 0) + if (rv != 0) return rv; *id = r; return 0; @@ -627,7 +627,7 @@ int rv; rv = google_chromeec_command(&cmd); - if (rv < 0) + if (rv != 0) return rv; /* Ensure NUL termination. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 8 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: rtc: Fix rtc_calc_weekday
by Tim Wawrzynczak (Code Review) 27 Feb '19

27 Feb '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31557 Change subject: rtc: Fix rtc_calc_weekday ...................................................................... rtc: Fix rtc_calc_weekday This function appeared previously unused (called only from rtc_display, also unused), but it returned an incorrect weekday. Change the algorithm to use Zeller's Rule, a well-known algorithm for calculuating weekdays. Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/lib/rtc.c 1 file changed, 26 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31557/1 diff --git a/src/lib/rtc.c b/src/lib/rtc.c index c5c157f..1dd301c 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -27,51 +27,32 @@ #define DAYS_IN_YEAR(a) (LEAP_YEAR(a) ? 366 : 365) #define DAYS_IN_MONTH(a) (month_days[(a) - 1]) -static const int month_offset[] = { - 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 -}; - static const char *const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; -static int leaps_to_year(int year) -{ - return year / 4 - year / 100 + year / 400; -} - -/* This only works for the Gregorian calendar after Jan 1 1971. */ +/* Zeller's rule */ static int rtc_calc_weekday(struct rtc_time *tm) { - int leaps_to_date; - int day; - if (tm->year < 1971) return -1; - day = 4; /* Jan 1 1970 was a Thursday. */ - - /* Number of leap corrections to apply up to end of last year */ - leaps_to_date = leaps_to_year(tm->year - 1) - leaps_to_year(1970); - - /* - * This year is a leap year if it is divisible by 4 except when it is - * divisible by 100 unless it is divisible by 400 - * - * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 is. - */ - if ((tm->year % 4) && - ((tm->year % 100 != 0) || (tm->year % 400 == 0)) && - (tm->mon > 2)) { - /* We are past Feb. 29 in a leap year */ - day++; - } - - day += (tm->year - 1970) * 365 + leaps_to_date + - month_offset[tm->mon-1] + tm->mday; - tm->wday = day % 7; - - return 0; + /* k: Day of month */ + const int k = tm->mday; + /* m: Month number (March is 1, April 2, ... January 11, February 12) */ + const int m = (tm->mon < 3) ? tm->mon + 10 : tm->mon - 2; + /* D: Last 2 digits of year; but treat Jan/Feb as "last year" */ + const int D = ((tm->mon < 3) ? tm->year - 1 : tm->year) % 100; + /* C: First two digits of the year */ + const int C = tm->year / 100; + const int f = k + + (13 * m - 1) / 5 + + D + + (D >> 2) + + (C >> 2) + - 2 * C; + tm->wday = f % 7; + return 0; } int rtc_to_tm(int tim, struct rtc_time *tm) @@ -139,16 +120,18 @@ } days = (unsigned long)(year / 4 - year / 100 + year / 400 + - 367 * mon / 12 + tm->mday) + - year * 365 - 719499; + 367 * mon / 12 + tm->mday) + + year * 365 - 719499; hours = days * 24 + tm->hour; return (hours * 60 + tm->min) * 60 + tm->sec; } -void rtc_display(const struct rtc_time *tm) +void rtc_display(struct rtc_time *tm) { - printk(BIOS_INFO, "Date: %4d-%02d-%02d (%sday) Time: %2d:%02d:%02d\n", - tm->year, tm->mon, tm->mday, - (tm->wday < 0 || tm->wday > 6) ? "unknown " : weekdays[tm->wday], - tm->hour, tm->min, tm->sec); + (void)rtc_calc_weekday(tm); + printk(BIOS_INFO, "Current Date: %4d-%02d-%02d (%sday) " + "Time: %2d:%02d:%02d\n", + tm->year, tm->mon, tm->mday, + (tm->wday < 0 || tm->wday > 6) ? "unknown " : weekdays[tm->wday], + tm->hour, tm->min, tm->sec); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09 Gerrit-Change-Number: 31557 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Initialize GPIO_PCH_WP early in boot
by Rizwan Qureshi (Code Review) 27 Feb '19

27 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31599 Change subject: mb/google/hatch: Initialize GPIO_PCH_WP early in boot ...................................................................... mb/google/hatch: Initialize GPIO_PCH_WP early in boot Initialize GPIO_PCH_WP early in boot. Also update the cros_gpios[] array with GPIO_PCH_WP information. Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/31599/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index e1189b9..b4130c8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -209,6 +209,8 @@ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), /* WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) @@ -218,6 +220,8 @@ } static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; const struct cros_gpio *__weak variant_cros_gpios(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/31599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae Gerrit-Change-Number: 31599 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Select SD_PWR_EN workaround
by Rizwan Qureshi (Code Review) 27 Feb '19

27 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31446 Change subject: mb/google/hatch: Select SD_PWR_EN workaround ...................................................................... mb/google/hatch: Select SD_PWR_EN workaround Hatch implements acive high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. BUG=b:123350329 Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/31446/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 65a3562..a1e58a3 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_WHISKEYLAKE select SYSTEM_TYPE_LAPTOP -- To view, visit https://review.coreboot.org/c/coreboot/+/31446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Gerrit-Change-Number: 31446 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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