coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29949 ) Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/memlay… File src/mainboard/google/mistral/memlayout.ld: https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/memlay… PS2, Line 16: > There shouldn't be a space here (guess that's wrong in Cheza, too). ok, will fix this https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/romsta… File src/mainboard/google/mistral/romstage.c: https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/romsta… PS2, Line 22: #include <arch/stages.h> > In general, do not define functions until you need them (e.g. […] ok, will fix. Will move this to the patch that uses it first. -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 09:58:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/google/mistral: Add support for Mistral
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29949 ) Change subject: mainboard/google/mistral: Add support for Mistral ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/chrome… File src/mainboard/google/mistral/chromeos.fmd: https://review.coreboot.org/#/c/29949/2/src/mainboard/google/mistral/chrome… PS2, Line 38: RW_XBL_BUFFER_A@0x1E8000 0x4000 > Please justify what you need all the non-standard sections in here for. […] Ok. Infact we were asked to have the same FMAP layout as in Gale (https://partnerissuetracker.corp.google.com/issues/122557977). So from this, https://review.coreboot.org/c/coreboot/+/30902/11, switched to Gale FMAP. Have a couple of comments from Patrick on that. On top of that, we might need little more changes as we add more features like DDR CDT data etc later, but based on what is correct for the product requirement, we can stick to either Cheza or Gale layout. -- To view, visit https://review.coreboot.org/c/coreboot/+/29949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Gerrit-Change-Number: 29949 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 09:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29948 ) Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29948/2/src/soc/qualcomm/qcs405/timer.c File src/soc/qualcomm/qcs405/timer.c: https://review.coreboot.org/#/c/29948/2/src/soc/qualcomm/qcs405/timer.c@18 PS2, Line 18: > As a general rule for this whole SoC, do not duplicate any code that is not substantially different […] Hi Julius, Thanks for start reviewing these Mistral patches. On the src/soc/qualcomm/common code abstraction part, we are planning to do that as a separate parallel activity to this Mistral set of patches. The idea is as you mention above to keep code common for sdm845, qcs405 and also any future socs. So we will post Mistral patches with comments addressed apart from 'common code'. We will take care of posting the 'common code' refactor separately and rebase (unmerged) mistral patches on top it at that point of time. That said, we have already started looking in to the 'common code' and should start showing up in some time. -- To view, visit https://review.coreboot.org/c/coreboot/+/29948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Gerrit-Change-Number: 29948 Gerrit-PatchSet: 11 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 27 Feb 2019 09:09:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init
by Furquan Shaikh (Code Review) 27 Feb '19

27 Feb '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31614 Change subject: soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init ...................................................................... soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init PMC initialization on Cannon lake happens earlier in the boot sequence than other SoCs because FSP-Silicon init hides PMC from PCI bus. As ACPI disabling was done as part of PMC init, it was being called earlier than what other SoCs do. This resulted in a different order of events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it ended up clearing EC events (which happens as part of ACPI disabling in SMM) before logging any events of interest that happen during mainboard initialization. This change moves the call to disable ACPI to pmc_soc_init just like other SoCs to keep the order of events more aligned. BUG=b:126016602 TEST=Verified that EC panic event gets logged to eventlog correctly. Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/pmc.c 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31614/1 diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index e111e94..24ddfee 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -144,8 +144,6 @@ /* Initialize power management */ pch_power_options(dev); - pmc_set_acpi_mode(); - config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); @@ -159,3 +157,21 @@ * allocate resources. */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); + +void pmc_soc_init(struct device *dev) +{ + /* + * PMC initialization happens earlier for this SoC because FSP-Silicon + * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which + * disables ACPI mode doesn't need to happen that early and can be + * delayed till typical pmc_soc_init callback. This ensures that ACPI + * mode disabling happens the same way for all SoCs and hence the + * ordering of events is the same. + * + * This is important to ensure that the ordering does not break the + * assumptions of any other drivers (e.g. ChromeEC) which could be + * taking different actions based on disabling of ACPI (e.g. flushing of + * all EC hostevent bits). + */ + pmc_set_acpi_mode(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551 Gerrit-Change-Number: 31614 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by build bot (Jenkins) (Code Review) 27 Feb '19

27 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/31550/5/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/5/src/arch/x86/memory_clear.c@79 PS5, Line 79: printk(BIOS_ERR, "%s: CBMEM must reside below 4GiB\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Feb 2019 08:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Patrick Rudolph (Code Review) 27 Feb '19

27 Feb '19

Hello Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31550 to look at the new patch set (#5). Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... arch/x86: Introduce helper to clear memory using PAE * Add Documentation. * Add x86 helper function to clear DRAM on a typical x86 memory map Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/memory_clear.h A src/arch/x86/memory_clear.c 4 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31550/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Rudolph (Code Review) 27 Feb '19

27 Feb '19

Hello Kyösti Mälkki, Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31549 to look at the new patch set (#5). Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation. Tested on wedge100s. Takes less than 2 seconds to clear 8GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md M Documentation/security/memory_clearing.md M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 4 files changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31549/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake
by Subrata Banik (Code Review) 27 Feb '19

27 Feb '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31529 ) Change subject: vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for Cometlake ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… File src/vendorcode/intel/fsp/fsp2_0/cometlake/FspUpd.h: https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 3: Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> > Were the contents of this file newly created, though? […] >> do you mean that the copyright notice above applies to FSP as a whole and not just this file? Yes, its not only applied to this files, it applies to entire FSP code https://review.coreboot.org/#/c/31529/3/src/vendorcode/intel/fsp/fsp2_0/com… PS3, Line 40: #define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */ > Nothing to worry beside confusion, making bisecting even harder than […] Hopefully next RC release will fix this problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/31529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Gerrit-Change-Number: 31529 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 27 Feb 2019 08:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security: Add memory subfolder
by build bot (Jenkins) (Code Review) 27 Feb '19

27 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig File src/security/memory/Kconfig: https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@16 PS3, Line 16: menu "Memory initilization" 'initilization' may be misspelled - perhaps 'initialization'? https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@34 PS3, Line 34: endmenu #Memory initilization 'initilization' may be misspelled - perhaps 'initialization'? -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Feb 2019 08:22:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by build bot (Jenkins) (Code Review) 27 Feb '19

27 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 ) Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31550/4/src/arch/x86/memory_clear.c File src/arch/x86/memory_clear.c: https://review.coreboot.org/#/c/31550/4/src/arch/x86/memory_clear.c@79 PS4, Line 79: printk(BIOS_ERR, "%s: CBMEM must reside below 4GiB\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Feb 2019 08:19:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2019