coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/cannonlake: Add a power control workaround for SD controller
by Rizwan Qureshi (Code Review) 27 Feb '19

27 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31445 Change subject: soc/intel/cannonlake: Add a power control workaround for SD controller ...................................................................... soc/intel/cannonlake: Add a power control workaround for SD controller SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. For platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power. Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native funtion in _PS0. Also add a Kconfig option to allow a mainboard to choose if this workaround is required, based on how the SD_VDD1_PWR_EN is implemented on it. BUG=b:123350329 Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 3 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31445/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index bacbe7b..dce116b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -236,6 +236,14 @@ hex default 0x200000 +config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + bool "Activate workaround in ASL for keeping SD_PWR_ENABLE low in D3" + default n + help + Select this if the board has a SD_PWR_ENABLE pin connected to a + active high sensing load switch to turn on power to the card reader. + This will enable a workaround in ASL _PS3 and _PS0 methods to force + SD_PWR_ENABLE to stay low in D3. choice prompt "Cache-as-ram implementation" default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 896fd77..558d538 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -111,6 +111,11 @@ /* Set Power State to D0 */ And (PMCR, 0xFFFC, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to Native*/ + GPMO(SD_PWR_EN_PIN, 0x1) +#endif } Method (_PS3, 0, Serialized) @@ -120,6 +125,14 @@ /* Set Power State to D3 */ Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) + +#if IS_ENABLED(CONFIG_MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) + /* Change pad mode to GPIO control */ + GPMO(SD_PWR_EN_PIN, 0x0) + + /* Drive TX to zero */ + CTXS(SD_PWR_EN_PIN) +#endif } Device (CARD) diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index cb184c9..380ec66 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -352,4 +352,6 @@ #define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1) #define TOTAL_PADS 275 + +#define SD_PWR_EN_PIN GPP_A17 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Gerrit-Change-Number: 31445 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers
by Rizwan Qureshi (Code Review) 27 Feb '19

27 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31619 Change subject: soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers ...................................................................... soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers. BUG=b:123350329 Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/cannonlake/include/soc/gpio_defs.h 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31619/1 diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 0c89e99..e1cfe04 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -94,3 +94,45 @@ And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) Or (Local0, Arg1, VAL0) } + +/* + * Enable/Disable Tx buffer + * Arg0 - GPIO Number + * Arg1 - TxBuffer state + * 0 = Disable Tx Buffer + * 1 = Enable Tx Buffer + */ +Method (GTXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Arg1 = LNot (Arg1) + Store (VAL0, Local0) + And (Not (GPIOTXBUFDIS_MASK), Local0, Local0) + And (ShiftLeft (Arg1, GPIOTXBUFDIS_SHIFT, Arg1), GPIOTXBUFDIS_MASK, Arg1) + Or (Local0, Arg1, VAL0) +} + +/* + * Enable/Disable Rx buffer + * Arg0 - GPIO Number + * Arg1 - RxBuffer state + * 0 = Disable Rx Buffer + * 1 = Enable Rx Buffer + */ +Method (GRXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Arg1 = LNot (Arg1) + Store (VAL0, Local0) + And (Not (GPIORXBUFDIS_MASK), Local0, Local0) + And (ShiftLeft (Arg1, GPIORXBUFDIS_SHIFT, Arg1), GPIORXBUFDIS_MASK, Arg1) + Or (Local0, Arg1, VAL0) +} diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index e8b4f61..3399526 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -255,4 +255,8 @@ #define GPIOTXSTATE_MASK 0x1 #define GPIOPADMODE_MASK 0xC00 #define GPIOPADMODE_SHIFT 10 +#define GPIOTXBUFDIS_MASK 0x100 +#define GPIOTXBUFDIS_SHIFT 8 +#define GPIORXBUFDIS_MASK 0x200 +#define GPIORXBUFDIS_SHIFT 9 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6 Gerrit-Change-Number: 31619 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: update SD card detect GPIO
by Rizwan Qureshi (Code Review) 27 Feb '19

27 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31553 Change subject: mb/google/hatch: update SD card detect GPIO ...................................................................... mb/google/hatch: update SD card detect GPIO SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO, expose that GPIO for kernel to configure card detect IRQ. Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/gpio.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31553/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index aaef663..77e5786 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,7 +89,7 @@ register "PcieClkSrcClkReq[1]" = "1" # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" + register "sdcard_cd_gpio" = "vGPIO_39" # PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index badd978..4e2dc57 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -172,6 +172,8 @@ PAD_NC(GPP_H10, NONE), /* PCH_I2C_TRACKPAD_SCL */ PAD_NC(GPP_H11, NONE), + /* SD card detect VGPIO */ + PAD_CFG_GPI_GPIO_DRIVER(vGPIO_39, NONE, DEEP), /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/31553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d Gerrit-Change-Number: 31553 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/cyan: fix RAM training on edgar variant
by Matt DeVillier (Code Review) 27 Feb '19

27 Feb '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31615 Change subject: mb/google/cyan: fix RAM training on edgar variant ...................................................................... mb/google/cyan: fix RAM training on edgar variant Several cyan variants require memory init parameters passed to FSP for handling of specific Micron modules; edgar was missing this, leading to boot failure after the MRC cache was populated. Add the required memory init parameters for edgar. Test: build/boot on edgar board with affected Micron memory modules, verify subsequent boots successful with populated MRC cache. Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/edgar/Makefile.inc A src/mainboard/google/cyan/variants/edgar/romstage.c 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31615/1 diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index 2e8b02c..ad9ac8a 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c new file mode 100644 index 0000000..12fef77 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <mainboard/google/cyan/spd/spd_util.h> + +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params) +{ + int ram_id = get_ramid(); + + /* + * RAMID = 5 - 4GiB Micron MT52L256M32D1PF-107 + * RAMID = 7 - 2GiB Micron MT52L256M32D1PF-107 + */ + if (ram_id == 5 || ram_id == 7) { + + /* + * For new micron part, it requires read/receive + * enable training before sending cmds to get MR8. + * To override dram geometry settings as below: + * + * PcdDramWidth = x32 + * PcdDramDensity = 8Gb + * PcdDualRankDram = disable + */ + memory_params->PcdRxOdtLimitChannel0 = 1; + memory_params->PcdRxOdtLimitChannel1 = 1; + memory_params->PcdDisableAutoDetectDram = 1; + memory_params->PcdDramWidth = 2; + memory_params->PcdDramDensity = 3; + memory_params->PcdDualRankDram = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Gerrit-Change-Number: 31615 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE
by Patrick Rudolph (Code Review) 27 Feb '19

27 Feb '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31568 Change subject: soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE ...................................................................... soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGE To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE. The SoC has enough CAR space to support a separate verstage. Tested on OpenCellular Elgon. Change-Id: I18022000f6f05df89d3037896ef627070bfcca06 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31568/1 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 4bf2e65..9119bcc 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -18,7 +18,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK config ARM64_BL31_EXTERNAL_FILE diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 2222617..8412dff 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -33,9 +33,10 @@ TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 32K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x28000, 12K) + VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x2b000, 2K) + VERSTAGE(BOOTROM_OFFSET + 0x2c000, 78K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) SRAM_END(BOOTROM_OFFSET + 0x80000) -- To view, visit https://review.coreboot.org/c/coreboot/+/31568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18022000f6f05df89d3037896ef627070bfcca06 Gerrit-Change-Number: 31568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qclib: Add qclib support
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 13: (1 comment) > Patch Set 2: > > (1 comment) > > lots of parts are commented out. please sort that out before the next iteration. > Also, we indent code by tabs (as the build bot helpfully pointed out), so please account for that. ok, will fix those. https://review.coreboot.org/#/c/29967/2/src/mainboard/google/mistral/mainbo… File src/mainboard/google/mistral/mainboard.c: https://review.coreboot.org/#/c/29967/2/src/mainboard/google/mistral/mainbo… PS2, Line 21: #if 0 > what's this for? if it's not needed, kick it out entirely. oh, got in accidentally. will remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 10:52:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/qualcomm: Add T32 debug scripts
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29951 ) Change subject: util/qualcomm: Add T32 debug scripts ...................................................................... Patch Set 12: > Patch Set 2: > > (1 comment) Ok, will fix those. -- To view, visit https://review.coreboot.org/c/coreboot/+/29951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Gerrit-Change-Number: 29951 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 10:47:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add Timer for qcs405
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29953 ) Change subject: libpayload: Add Timer for qcs405 ...................................................................... Patch Set 12: > Patch Set 2: > > the commit message doesn't match what the commit does, as it only adds a config file Ok, will reword the Commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/29953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Gerrit-Change-Number: 29953 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 10:47:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add Timer support
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29952 ) Change subject: qcs405: Add Timer support ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/29952/2/src/soc/qualcomm/qcs405/Makefile.inc File src/soc/qualcomm/qcs405/Makefile.inc: https://review.coreboot.org/#/c/29952/2/src/soc/qualcomm/qcs405/Makefile.in… PS2, Line 8: bootblock-y += timer.c > is there any reason for this reordering? Hmm, will avoid this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/29952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Gerrit-Change-Number: 29952 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 10:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by Sricharan Ramabadhran (Code Review) 27 Feb '19

27 Feb '19

Sricharan Ramabadhran has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29950 ) Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c@1 PS2, Line 1: /* > This file can be deduplicated with SDM845, see CB:27349 as an example from another SoC. Ok agree. Sure this will be refactored this in Qcom 'common code' -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Feb 2019 10:44:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2019