coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: Add missing u8 eos[2] declaration to struct smbios_type38
by Łukasz Siudut (Code Review) 26 Feb '19

26 Feb '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31482 Change subject: Add missing u8 eos[2] declaration to struct smbios_type38 ...................................................................... Add missing u8 eos[2] declaration to struct smbios_type38 Each smbios should be followed with two null bytes. In other structures it's done by adding `u8 eos[2]` extra bytes at the end, it was omitted in type38 (IPMI) though. This change fixes this - tables decodes nicely: ``` IPMI Device Information Interface Type: KCS (Keyboard Control Style) Specification Version: 2.0 I2C Slave Address: 0x10 NV Storage Device: Not Present Base Address: 0x0000000000000CA2 (I/O) Register Spacing: 32-bit Boundaries ``` This is follow up of change #31435 Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: I8efea9612448f48e23e7b2226aea2a9f3bc21824 --- M src/include/smbios.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/31482/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 38ebcdc..c046b1a 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -493,6 +493,7 @@ u64 base_address; u8 base_address_modifier; u8 irq; + u8 eos[2]; } __packed; enum smbios_bmc_interface_type { -- To view, visit https://review.coreboot.org/c/coreboot/+/31482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8efea9612448f48e23e7b2226aea2a9f3bc21824 Gerrit-Change-Number: 31482 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Julius Werner (Code Review) 26 Feb '19

26 Feb '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 55: (10 comments) Please fix the line length issues, too. https://review.coreboot.org/#/c/29563/55/src/commonlib/include/commonlib/tc… File src/commonlib/include/commonlib/tcpa_log_serialized.h: https://review.coreboot.org/#/c/29563/55/src/commonlib/include/commonlib/tc… PS55, Line 26: PREMEM nit: "PRERAM" would be more consistent with other coreboot terminology usage https://review.coreboot.org/#/c/29563/55/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/55/src/include/memlayout.h@169 PS55, Line 169: 2K nit: Considering that this is such a pain to fit on some SoCs, do you think it might make sense to reduce it to 1K? Can you think of a situation where you'd need to measure more than 8 pre-RAM files? (Alternatively you could just not define a minimum and calculate the available space for entries dynamically, so that SoCs with less space but also less things to measure could use less SRAM for it.) https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi.h File src/security/tpm/tspi.h: https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi.h@56 PS55, Line 56: diget_type typo https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/log.c@40 PS55, Line 40: memset(tclt, 0, tcpa_log_len); unnecesary? https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/log.c@124 PS55, Line 124: MIN( MIN() is unnecessary https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/log.c@131 PS55, Line 131: && IS_ENABLED(CONFIG_VBOOT_TCPA_LOG_RECOVERY)) { Not sure you need all these checks here? This should only be called in cases where that is all true anyway (except for LOG_RECOVERY, maybe), and for everything else it should be garbage-collected out harmlessly. Note that ENV_CACHE_AS_RAM is actually always 0 on non-x86 systems, so that will make it not work on there. https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/log.c@135 PS55, Line 135: printk(BIOS_ERR, "TCPA: Couldn't clear coreboot TCPA log\n"); nit: this is pretty pointless to check, either the symbol exists or you get a build-time linker error. https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/tspi.c File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/#/c/29563/55/src/security/tpm/tspi/tspi.c@241 PS55, Line 241: if (IS_ENABLED(CONFIG_TPM1)) { Why not just move this part into tcpa_log_add_table_entry()? As long as we hardcode which hash to use for which TPM type anyway, no need to do this so high up. https://review.coreboot.org/#/c/29563/55/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/55/src/security/vboot/secdata_tpm.c@83 PS55, Line 83: "SHA1" I don't think this belongs here, right? Which algorithm is used is hardcoded in tlcl_extend(), it's not decided here. https://review.coreboot.org/#/c/29563/55/src/security/vboot/symbols.h File src/security/vboot/symbols.h: https://review.coreboot.org/#/c/29563/55/src/security/vboot/symbols.h@25 PS55, Line 25: #define _vboot2_tpm_log_size (_evboot2_tpm_log - _vboot2_tpm_log) Note that this got changed (CB:31539). -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 55 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 21:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status passing
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status passing ...................................................................... Patch Set 7: Patchset 6 has been converted to https://review.coreboot.org/c/coreboot/+/31626. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 7 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 21:09:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd: Remove defined but unwritten functions
by Richard Spiegel (Code Review) 26 Feb '19

26 Feb '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31507 Change subject: soc/amd: Remove defined but unwritten functions ...................................................................... soc/amd: Remove defined but unwritten functions There are functions defined on headers with no code written for. They probably existed earlier, were removed and forgot in the headers. Remove functions from headers if there's no actual code written for. BUG=b:123564495 TEST=Build grunt. Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31507/1 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d62c791..3b60400 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -121,10 +121,8 @@ */ int smm_subregion(int sub, void **start, size_t *size); void domain_enable_resources(struct device *dev); -void domain_read_resources(struct device *dev); void domain_set_resources(struct device *dev); void fam15_finalize(void *chip_info); -void setup_uma_memory(void); uint32_t nb_ioapic_read(unsigned int index); void nb_ioapic_write(unsigned int index, uint32_t value); void *get_ap_entry_ptr(void); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 705fe7a..4d1448c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -477,7 +477,6 @@ void enable_aoac_devices(void); void sb_enable_rom(void); -void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/31507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b Gerrit-Change-Number: 31507 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Patrick Georgi (Code Review) 26 Feb '19

26 Feb '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 55: Code-Review+1 (13 comments) https://review.coreboot.org/#/c/29563/55/Documentation/security/index.md File Documentation/security/index.md: https://review.coreboot.org/#/c/29563/55/Documentation/security/index.md@3 PS55, Line 3: contains documentation about describes https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… File Documentation/security/vboot/measured_boot.md: https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 4: easy understandable "easy to understand"? https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 36: SP Sp https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 38: so : that ". Therefore"? https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 41: So we We https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 41: easy understandable easy to understand https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 44: Some details regarding the eventlog table. this is either a new subtitle (e.g. ### Details, or "table format") or should be left out altogether. https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 45: The : third "Third comes" or simply "The third column contains" https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 47: . We have one prefix only. CBFS and : FMAP which describe where the measured data comes from (coreboot filesystem or : partition table). : first the namespace from where the data came from, CBFS or FMAP, then the name used to look up the data (region or file name). https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 62: CBFS In some scenarios there are multiple CBFSes with duplicate filenames. What happens then? https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 82: -f romstage -U && sha256sum -b romstage -f /dev/stdout -U | sha256sum would work, too https://review.coreboot.org/#/c/29563/55/Documentation/security/vboot/measu… PS55, Line 87: -f intel-me && sha256sum -b intel-me same here. https://review.coreboot.org/#/c/29563/55/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29563/55/src/security/vboot/vboot_crtm.c@149 PS55, Line 149: strncpy(prefix_name, CBFS_PREFIX, TCPA_PCR_HASH_NAME - 1); : strncpy(prefix_name + sizeof(CBFS_PREFIX), : name, TCPA_PCR_HASH_NAME - sizeof(CBFS_PREFIX) - 1); snprintf? -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 55 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 19:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/device/Kconfig: Add Kconfig options to choose a default VESA mode
by mikeb mikeb (Code Review) 26 Feb '19

26 Feb '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31324 to review the following change. Change subject: src/device/Kconfig: Add Kconfig options to choose a default VESA mode ...................................................................... src/device/Kconfig: Add Kconfig options to choose a default VESA mode Introduce the FRAMEBUFFER_VESA_DEFAULT_*** options which could be used to choose a default VESA mode at motherboard's Kconfig. If FRAMEBUFFER_VESA_DEFAULT_CUSTOM if false because no custom default has been selected, choose FRAMEBUFFER_VESA_MODE_117. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I4bf44002d67351195c448a2a7479daede7fcb0ef --- M src/device/Kconfig 1 file changed, 104 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31324/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index b90b15f..25301c8 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -263,9 +263,112 @@ if FRAMEBUFFER_SET_VESA_MODE +config FRAMEBUFFER_VESA_DEFAULT_CUSTOM + bool +config FRAMEBUFFER_VESA_DEFAULT_100 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_101 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_102 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_103 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_104 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_105 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_106 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_107 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_108 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_109 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10A + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10B + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10C + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10D + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10E + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_10F + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_110 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_111 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_112 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_113 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_114 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_115 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_116 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_117 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM +config FRAMEBUFFER_VESA_DEFAULT_118 + bool + select FRAMEBUFFER_VESA_DEFAULT_CUSTOM + choice prompt "framebuffer graphics resolution" - default FRAMEBUFFER_VESA_MODE_117 + default FRAMEBUFFER_VESA_MODE_100 if FRAMEBUFFER_VESA_DEFAULT_100 + default FRAMEBUFFER_VESA_MODE_101 if FRAMEBUFFER_VESA_DEFAULT_101 + default FRAMEBUFFER_VESA_MODE_102 if FRAMEBUFFER_VESA_DEFAULT_102 + default FRAMEBUFFER_VESA_MODE_103 if FRAMEBUFFER_VESA_DEFAULT_103 + default FRAMEBUFFER_VESA_MODE_104 if FRAMEBUFFER_VESA_DEFAULT_104 + default FRAMEBUFFER_VESA_MODE_105 if FRAMEBUFFER_VESA_DEFAULT_105 + default FRAMEBUFFER_VESA_MODE_106 if FRAMEBUFFER_VESA_DEFAULT_106 + default FRAMEBUFFER_VESA_MODE_107 if FRAMEBUFFER_VESA_DEFAULT_107 + default FRAMEBUFFER_VESA_MODE_108 if FRAMEBUFFER_VESA_DEFAULT_108 + default FRAMEBUFFER_VESA_MODE_109 if FRAMEBUFFER_VESA_DEFAULT_109 + default FRAMEBUFFER_VESA_MODE_10A if FRAMEBUFFER_VESA_DEFAULT_10A + default FRAMEBUFFER_VESA_MODE_10B if FRAMEBUFFER_VESA_DEFAULT_10B + default FRAMEBUFFER_VESA_MODE_10C if FRAMEBUFFER_VESA_DEFAULT_10C + default FRAMEBUFFER_VESA_MODE_10D if FRAMEBUFFER_VESA_DEFAULT_10D + default FRAMEBUFFER_VESA_MODE_10E if FRAMEBUFFER_VESA_DEFAULT_10E + default FRAMEBUFFER_VESA_MODE_10F if FRAMEBUFFER_VESA_DEFAULT_10F + default FRAMEBUFFER_VESA_MODE_110 if FRAMEBUFFER_VESA_DEFAULT_110 + default FRAMEBUFFER_VESA_MODE_111 if FRAMEBUFFER_VESA_DEFAULT_111 + default FRAMEBUFFER_VESA_MODE_112 if FRAMEBUFFER_VESA_DEFAULT_112 + default FRAMEBUFFER_VESA_MODE_113 if FRAMEBUFFER_VESA_DEFAULT_113 + default FRAMEBUFFER_VESA_MODE_114 if FRAMEBUFFER_VESA_DEFAULT_114 + default FRAMEBUFFER_VESA_MODE_115 if FRAMEBUFFER_VESA_DEFAULT_115 + default FRAMEBUFFER_VESA_MODE_116 if FRAMEBUFFER_VESA_DEFAULT_116 + default FRAMEBUFFER_VESA_MODE_117 if FRAMEBUFFER_VESA_DEFAULT_117 + default FRAMEBUFFER_VESA_MODE_118 if FRAMEBUFFER_VESA_DEFAULT_118 + default FRAMEBUFFER_VESA_MODE_117 if !FRAMEBUFFER_VESA_DEFAULT_CUSTOM help This option sets the resolution used for the coreboot framebuffer (and bootsplash screen). -- To view, visit https://review.coreboot.org/c/coreboot/+/31324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bf44002d67351195c448a2a7479daede7fcb0ef Gerrit-Change-Number: 31324 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things
by Nico Huber (Code Review) 26 Feb '19

26 Feb '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31558 ) Change subject: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things ...................................................................... mb/gigabyte/ga-h61m-s2pv: fix cosmetic things Remove unneeded options, note where usbdebug is, reorder devicetree and clean up dsdt. Tested, board still boots. Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl 3 files changed, 12 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 39a70f8..5fba47a 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ string default "GA-H61M-S2PV" -config VGA_BIOS_FILE - string - default "pci8086,0102.rom" - -config VGA_BIOS_ID - string - default "8086,0102" - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x5001 @@ -60,7 +52,7 @@ int default 8 -config USBDEBUG_HCD_INDEX # FIXME: check this +config USBDEBUG_HCD_INDEX # Bottom left port seen from rear int default 2 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb index 667dd9c..e382cbd 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -30,12 +30,12 @@ end register "pci_mmio_size" = "2048" device domain 0x0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) + device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" - register "docking_supported" = "0" register "gen1_dec" = "0x003c0a01" - register "p_cnt_throttling_supported" = "0" - register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" @@ -100,8 +100,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16) - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index 6a929d0..dbf8c96 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -14,7 +14,9 @@ */ #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + #include <arch/acpi.h> + DefinitionBlock( "dsdt.aml", "DSDT", @@ -24,7 +26,6 @@ 0x20141018 // OEM revision ) { - // Some generic macros #include "acpi/mainboard.asl" #include "acpi/platform.asl" #include "acpi/superio.asl" @@ -32,16 +33,14 @@ #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> - /* global NVS and variables. */ + /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - } + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Gerrit-Change-Number: 31558 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things
by Angel Pons (Code Review) 26 Feb '19

26 Feb '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31558 ) Change subject: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/31558/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31558/3//COMMIT_MSG@7 PS3, Line 7: src/ > Please drop src/ prefix. Done https://review.coreboot.org/#/c/31558/3//COMMIT_MSG@7 PS3, Line 7: src/mb/gigabyte/ga-h61m-s2pv: fix random things > Doesn't look like you are "fixing" anything. Well, maybe […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Gerrit-Change-Number: 31558 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Feb 2019 18:48:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things
by Angel Pons (Code Review) 26 Feb '19

26 Feb '19

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31558 to look at the new patch set (#4). Change subject: mb/gigabyte/ga-h61m-s2pv: fix cosmetic things ...................................................................... mb/gigabyte/ga-h61m-s2pv: fix cosmetic things Remove unneeded options, note where usbdebug is, reorder devicetree and clean up dsdt. Tested, board still boots. Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl 3 files changed, 12 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31558/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Gerrit-Change-Number: 31558 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: flapjack: use sku_id 0 for un-provisioned board
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

Hello Daisuke Nojiri, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31623 to look at the new patch set (#2). Change subject: flapjack: use sku_id 0 for un-provisioned board ...................................................................... flapjack: use sku_id 0 for un-provisioned board Instead of using 2, 0 is now used for non-CBI provisioned board to confrom to the sku encoding. BUG=b:123676982 BRANCH=kukui TEST=test with un-provisioned board to verify the sku_id. Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce --- M src/mainboard/google/kukui/boardid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31623/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Gerrit-Change-Number: 31623 Gerrit-PatchSet: 2 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2019