coreboot-gerrit February 2019

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Patrick Rudolph (Code Review) 26 Feb '19

26 Feb '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 51: (11 comments) https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… File Documentation/security/vboot/measured_boot.md: https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… PS51, Line 39: that we could implement it. whitespace What does it mean for coreboot? Do we implement either one of them? https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… PS51, Line 63: ``` move above example output https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… PS51, Line 64: So we decided to provide and easy understandable TCPA log which can be read out an https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… PS51, Line 65: from the operating system and firmware log itself. firmware itself https://review.coreboot.org/#/c/29563/51/Documentation/security/vboot/measu… PS51, Line 70: e one prefix only https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@25 PS51, Line 25: #include <cbmem.h> cbmem.h included twice https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@30 PS51, Line 30: MAYBE_STATIC MAYBE_STATIC makes no sense if you don't check if tclt is non NULL and return it early. https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@81 PS51, Line 81: printk(BIOS_INFO, use full 80 char line length https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@102 PS51, Line 102: if (!tclt) add warning, too https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@136 PS51, Line 136: BIOS_INFO BIOS_ERR https://review.coreboot.org/#/c/29563/51/util/cbmem/cbmem.c File util/cbmem/cbmem.c: https://review.coreboot.org/#/c/29563/51/util/cbmem/cbmem.c@722 PS51, Line 722: printf(" %s [%s]\n", use full 80 chars per line -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 51 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 12:31:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
by Paul Menzel (Code Review) 26 Feb '19

26 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29005 ) Change subject: soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab3bbba1da79dbf1790c99c611195cffbda1511 Gerrit-Change-Number: 29005 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 12:26:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by Paul Menzel (Code Review) 26 Feb '19

26 Feb '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status handling ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 12:04:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 26 Feb '19

26 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 51: (10 comments) https://review.coreboot.org/#/c/29563/51/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/51/src/include/memlayout.h@167 PS51, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/51/src/include/memlayout.h@167 PS51, Line 167: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@163 PS51, Line 163: struct tcpa_entry *tce = &ram_log->entries[ram_log->num_entries++]; line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@164 PS51, Line 164: strncpy(tce->name, preram_log->entries[i].name, TCPA_PCR_HASH_NAME - 1); line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@167 PS51, Line 167: if (preram_log->entries[i].digest_length > TCPA_DIGEST_MAX_LENGTH) { line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@172 PS51, Line 172: strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@173 PS51, Line 173: tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/log.c@174 PS51, Line 174: memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/tspi.c File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/#/c/29563/51/src/security/tpm/tspi/tspi.c@247 PS51, Line 247: strncpy(hash_name, vb2_get_hash_algorithm_name(hash_alg), TCPA_PCR_HASH_LEN - 1); line over 80 characters https://review.coreboot.org/#/c/29563/51/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29563/51/src/security/vboot/secdata_tpm.c@86 PS51, Line 86: return tpm_extend_pcr(pcr, "SHA256", buffer, size, TPM_PCR_GBB_HWID_NAME); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 51 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 12:01:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 26 Feb '19

26 Feb '19

Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29563 to look at the new patch set (#51). Change subject: security/tpm: Fix TCPA log feature ...................................................................... security/tpm: Fix TCPA log feature Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A Documentation/security/index.md M Documentation/security/vboot/measured_boot.md M src/arch/x86/car.ld M src/commonlib/include/commonlib/tcpa_log_serialized.h M src/include/memlayout.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/secdata_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vboot_crtm.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M util/cbmem/cbmem.c 20 files changed, 313 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/51 -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 51 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: ec/google/chromeec: Clarify return value of google_chromeec_command
by Daisuke Nojiri (Code Review) 26 Feb '19

26 Feb '19

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31613 Change subject: ec/google/chromeec: Clarify return value of google_chromeec_command ...................................................................... ec/google/chromeec: Clarify return value of google_chromeec_command This patch clarifies the definition of google_chromeec_command. Currently absence of the definition isn't causing any problem because wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an interface which returns only negative error codes. However, there is a chance that a new wrapper API will be addedl which check 'ret < 0' to catch errors, assuming other interfaces behave the same. Or existing wrapper APIs will be broken as soon as they're compiled for another interface. BUG=chromium:935038 TEST=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f --- M src/ec/google/chromeec/ec.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31613/1 diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 70b2b52..7a38336 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -155,6 +155,12 @@ int crosec_command_proto(struct chromeec_command *cec_command, crosec_io_t crosec_io, void *context); +/** + * Send a command to a CrOS EC + * + * @param cec_command: CrOS EC command to send + * @return 0 for success. Non-zero for error. + */ int google_chromeec_command(struct chromeec_command *cec_command); struct google_chromeec_event_info { -- To view, visit https://review.coreboot.org/c/coreboot/+/31613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f Gerrit-Change-Number: 31613 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: flapjack: get sku_id from ec (cbi)
by Patrick Georgi (Code Review) 26 Feb '19

26 Feb '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31586 ) Change subject: flapjack: get sku_id from ec (cbi) ...................................................................... flapjack: get sku_id from ec (cbi) On flapjack, retrieve the board information via CBI interface. Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id used prior to the readiness of cbi. BUG=b:123676982 BRANCH=kukui TEST=provisioned cbi info and verify the sku_id. Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Reviewed-on: https://review.coreboot.org/c/31586 Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Daisuke Nojiri: Looks good to me, approved YH Lin: Looks good to me, approved diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index 2420e78..2af93c8 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -16,8 +16,11 @@ #include <assert.h> #include <boardid.h> #include <soc/auxadc.h> +#include <ec/google/chromeec/ec.h> #include <stddef.h> +#define FLAPJACK_UNDEF_SKU_ID 2 /* For all un-provisioned Flapjack boards */ + static uint32_t get_index(unsigned int channel, uint32_t *cached_id) { static const int voltages[] = { @@ -64,6 +67,14 @@ { static uint32_t cached_sku_id = BOARD_ID_INIT; + /* On Flapjack, getting the SKU via CBI */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_FLAPJACK)) { + if (cached_sku_id == BOARD_ID_INIT && + google_chromeec_cbi_get_sku_id(&cached_sku_id)) + cached_sku_id = FLAPJACK_UNDEF_SKU_ID; + return cached_sku_id; + } + /* Quirk for KUKUI: All P1/SKU0 had incorrectly set SKU=1. */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KUKUI)) { if (cached_sku_id == BOARD_ID_INIT && board_id() == 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Gerrit-Change-Number: 31586 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nick Sanders <nsanders(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/cavium/cn81xx: Enable RNG for DRAM init
by Patrick Rudolph (Code Review) 26 Feb '19

26 Feb '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31567 Change subject: soc/cavium/cn81xx: Enable RNG for DRAM init ...................................................................... soc/cavium/cn81xx: Enable RNG for DRAM init The Cavium DRAM init might use the RNG for pattern generation. Initialize it before running DRAM init. Tested on OpenCellular Elgon. The RNG generates non identical numbers. Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/sdram.c 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/31567/1 diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 2342b04..f434265 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -3,6 +3,7 @@ * * Copyright 2018 Facebook, Inc. * Copyright 2003-2017 Cavium Inc. <support(a)cavium.com> + * Copyright 2019 9elements Agency GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,17 +29,66 @@ #include <libbdk-hal/bdk-utils.h> #include <libbdk-hal/bdk-l2c.h> #include <libdram/libdram-config.h> +#include <soc/ecam.h> +#include <device/pci_ops.h> +#include <device/pci.h> size_t sdram_size_mb(void) { return bdk_dram_get_size_mbytes(0); } +/* Enable RNG for DRAM init */ +static void rnm_init(void) +{ + u64 *bar = NULL; + + #define BDK_RNM_CTL_STATUS 0 + #define BDK_RNM_RANDOM 0x100000 + + /* Bus numbers are hardcoded in ASIC */ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = pci_locate_device_on_bus(0xa018177d, 2); + if (dev == PCI_DEV_INVALID) { + printk(BIOS_ERR, "RNG: Failed to find PCI device\n"); + return; + } + + bar = (u64 *)ecam0_get_bar_val(dev, 0); +#endif + if (!bar) { + printk(BIOS_ERR, "RNG: Failed to get BAR0\n"); + return; + } + + printk(BIOS_DEBUG, "RNG: BAR0 at %p\n", bar); + + u64 reg = read64(&bar[BDK_RNM_CTL_STATUS]); + /** + * Enables the output of the RNG. + * Entropy enable for random number generator. + */ + reg |= 3; + write64(&bar[BDK_RNM_CTL_STATUS], reg); + + /* Read back after enable so we know it is done. */ + reg = read64(&bar[BDK_RNM_CTL_STATUS]); + /* Errata (RNM-22528) First consecutive reads to RNM_RANDOM return same + * value. Before using the random entropy, read RNM_RANDOM at least once + * and discard the data */ + reg = read64(&bar[BDK_RNM_RANDOM]); + printk(BIOS_DEBUG, "RNG: RANDOM %llx\n", reg); + reg = read64(&bar[BDK_RNM_RANDOM]); + printk(BIOS_DEBUG, "RNG: RANDOM %llx\n", reg); +} + /* based on bdk_boot_dram() */ void sdram_init(void) { printk(BIOS_DEBUG, "Initializing DRAM\n"); + rnm_init(); + /** * FIXME: second arg is actually a desired frequency if set (the * function usually obtains frequency via the config). That might -- To view, visit https://review.coreboot.org/c/coreboot/+/31567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0 Gerrit-Change-Number: 31567 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Modify I2C source clock
by wang qii (Code Review) 26 Feb '19

26 Feb '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31519 Change subject: mediatek/mt8183: Modify I2C source clock ...................................................................... mediatek/mt8183: Modify I2C source clock This patch change i2c source clock to TOPCKGEN. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569 Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/pll.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31519/1 diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 799b6ca..45cf989 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -345,6 +345,9 @@ /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + /* i2c module clock source selection */ + setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); + /* * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569 Gerrit-Change-Number: 31519 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO
by Rizwan Qureshi (Code Review) 26 Feb '19

26 Feb '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31552 Change subject: soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO ...................................................................... soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO Denote community 1 reserved group as virtual GPIOs in Cannonlake LP SoC. Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 3 files changed, 79 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31552/1 diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 1fa144f..95d28c4 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -80,7 +80,7 @@ Subtract (Arg0, GPP_A0, Local1) } /* GPIO Community 1 */ - If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52))) + If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_12))) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, GPP_D0, Local1) @@ -92,13 +92,13 @@ Subtract (Arg0, GPD0, Local1) } /* GPIO Community 3 */ - If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78))) + If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38))) { Store (PID_GPIOCOM1, Local0) Subtract (Arg0, HDA_BCLK, Local1) } /* GPIO Community 04*/ - If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67))) + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27))) { Store (PID_GPIOCOM4, Local0) Subtract (Arg0, GPP_C0, Local1) diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 701eb0b..746cd89 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -56,7 +56,7 @@ INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */ INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */ INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */ - INTEL_GPP_BASE(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52, 192),/* VGPIO */ + INTEL_GPP_BASE(GPP_D0, vGPIO_0, vGPIO_39, 192), /* VGPIO */ }; /* This community is not visible to the OS */ @@ -67,14 +67,14 @@ /* This community is not visible to the OS */ static const struct pad_group cnl_community3_groups[] = { INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */ - INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */ + INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */ }; static const struct pad_group cnl_community4_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */ - INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */ - INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */ + INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */ + INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */ }; static const struct pad_community cnl_communities[] = { @@ -97,7 +97,7 @@ }, { /* GPP D, F, H, VGPIO */ .port = PID_GPIOCOM1, .first_pad = GPP_D0, - .last_pad = GPIO_RSVD_52, + .last_pad = vGPIO_39, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -129,7 +129,7 @@ }, { /* AZA, CPU */ .port = PID_GPIOCOM3, .first_pad = HDA_BCLK, - .last_pad = GPIO_RSVD_78, + .last_pad = GPIO_RSVD_38, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -145,7 +145,7 @@ }, { /* GPP C, E, JTAG, HVMOS */ .port = PID_GPIOCOM4, .first_pad = GPP_C0, - .last_pad = GPIO_RSVD_67, + .last_pad = GPIO_RSVD_27, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index cb184c9..96463d7 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -197,48 +197,48 @@ #define GPP_H22 139 #define GPP_H23 140 /* Group VGPIO */ -#define GPIO_RSVD_13 141 -#define GPIO_RSVD_14 142 -#define GPIO_RSVD_15 143 -#define GPIO_RSVD_16 144 -#define GPIO_RSVD_17 145 -#define GPIO_RSVD_18 146 -#define GPIO_RSVD_19 147 -#define GPIO_RSVD_20 148 -#define GPIO_RSVD_21 149 -#define GPIO_RSVD_22 150 -#define GPIO_RSVD_23 151 -#define GPIO_RSVD_24 152 -#define GPIO_RSVD_25 153 -#define GPIO_RSVD_26 154 -#define GPIO_RSVD_27 155 -#define GPIO_RSVD_28 156 -#define GPIO_RSVD_29 157 -#define GPIO_RSVD_30 158 -#define GPIO_RSVD_31 159 -#define GPIO_RSVD_32 160 -#define GPIO_RSVD_33 161 -#define GPIO_RSVD_34 162 -#define GPIO_RSVD_35 163 -#define GPIO_RSVD_36 164 -#define GPIO_RSVD_37 165 -#define GPIO_RSVD_38 166 -#define GPIO_RSVD_39 167 -#define GPIO_RSVD_40 168 -#define GPIO_RSVD_41 169 -#define GPIO_RSVD_42 170 -#define GPIO_RSVD_43 171 -#define GPIO_RSVD_44 172 -#define GPIO_RSVD_45 173 -#define GPIO_RSVD_46 174 -#define GPIO_RSVD_47 175 -#define GPIO_RSVD_48 176 -#define GPIO_RSVD_49 177 -#define GPIO_RSVD_50 178 -#define GPIO_RSVD_51 179 -#define GPIO_RSVD_52 180 +#define vGPIO_0 141 +#define vGPIO_1 142 +#define vGPIO_2 143 +#define vGPIO_3 144 +#define vGPIO_4 145 +#define vGPIO_5 146 +#define vGPIO_6 147 +#define vGPIO_7 148 +#define vGPIO_8 149 +#define vGPIO_9 150 +#define vGPIO_10 151 +#define vGPIO_11 152 +#define vGPIO_12 153 +#define vGPIO_13 154 +#define vGPIO_14 155 +#define vGPIO_15 156 +#define vGPIO_16 157 +#define vGPIO_17 158 +#define vGPIO_18 159 +#define vGPIO_19 160 +#define vGPIO_20 161 +#define vGPIO_21 162 +#define vGPIO_22 163 +#define vGPIO_23 164 +#define vGPIO_24 165 +#define vGPIO_25 166 +#define vGPIO_26 167 +#define vGPIO_27 168 +#define vGPIO_28 169 +#define vGPIO_29 170 +#define vGPIO_30 171 +#define vGPIO_31 172 +#define vGPIO_32 173 +#define vGPIO_33 174 +#define vGPIO_34 175 +#define vGPIO_35 176 +#define vGPIO_36 177 +#define vGPIO_37 178 +#define vGPIO_38 179 +#define vGPIO_39 180 -#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1) +#define NUM_GPIO_COM1_PADS (vGPIO_39 - GPP_D0 + 1) /* Group C */ #define GPP_C0 181 @@ -291,24 +291,24 @@ #define GPP_E22 227 #define GPP_E23 228 /* Group Jtag */ -#define GPIO_RSVD_53 229 -#define GPIO_RSVD_54 230 -#define GPIO_RSVD_55 231 -#define GPIO_RSVD_56 232 -#define GPIO_RSVD_57 233 -#define GPIO_RSVD_58 234 -#define GPIO_RSVD_59 235 -#define GPIO_RSVD_60 236 -#define GPIO_RSVD_61 237 +#define GPIO_RSVD_13 229 +#define GPIO_RSVD_14 230 +#define GPIO_RSVD_15 231 +#define GPIO_RSVD_16 232 +#define GPIO_RSVD_17 233 +#define GPIO_RSVD_18 234 +#define GPIO_RSVD_19 235 +#define GPIO_RSVD_20 236 +#define GPIO_RSVD_21 237 /* Group HVMOS */ -#define GPIO_RSVD_62 238 -#define GPIO_RSVD_63 239 -#define GPIO_RSVD_64 240 -#define GPIO_RSVD_65 241 -#define GPIO_RSVD_66 242 -#define GPIO_RSVD_67 243 +#define GPIO_RSVD_22 238 +#define GPIO_RSVD_23 239 +#define GPIO_RSVD_24 240 +#define GPIO_RSVD_25 241 +#define GPIO_RSVD_26 242 +#define GPIO_RSVD_27 243 -#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1) +#define NUM_GPIO_COM4_PADS (GPIO_RSVD_27 - GPP_C0 + 1) /* Group GPD */ #define GPD0 244 @@ -337,19 +337,19 @@ #define SSP1_SFRM 262 #define SSP1_TXD 263 /* Group CPU */ -#define GPIO_RSVD_68 264 -#define GPIO_RSVD_69 265 -#define GPIO_RSVD_70 266 -#define GPIO_RSVD_71 267 -#define GPIO_RSVD_72 268 -#define GPIO_RSVD_73 269 -#define GPIO_RSVD_74 270 -#define GPIO_RSVD_75 271 -#define GPIO_RSVD_76 272 -#define GPIO_RSVD_77 273 -#define GPIO_RSVD_78 274 +#define GPIO_RSVD_28 264 +#define GPIO_RSVD_29 265 +#define GPIO_RSVD_30 266 +#define GPIO_RSVD_31 267 +#define GPIO_RSVD_32 268 +#define GPIO_RSVD_33 269 +#define GPIO_RSVD_34 270 +#define GPIO_RSVD_35 271 +#define GPIO_RSVD_36 272 +#define GPIO_RSVD_37 273 +#define GPIO_RSVD_38 274 -#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1) +#define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1) #define TOTAL_PADS 275 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Gerrit-Change-Number: 31552 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019