coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

1 participants
1249 discussions

Change in ...coreboot[master]: [WIP] payloads/tianocore: default to MrChromebox's working branch
by Matt DeVillier (Code Review) 26 Feb '19

26 Feb '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31543 Change subject: [WIP] payloads/tianocore: default to MrChromebox's working branch ...................................................................... [WIP] payloads/tianocore: default to MrChromebox's working branch Rather than attempt to maintain patches against upstream Tianocore, use MrChromebox's coreboot frambuffer branch as the default build target. Rework the Makefile to default to MrChromebox's coreboot_fb branch, but also allow for aribitrary commits from upstream Tianocore to be used as build targets. Ensure the branch in synced on each build, and that switching between commits or trees is handled sanely. Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched it is unlikely to boot on any device. It can easily be specified via the 'revision' option if desired. Test: build for the default stable target, for upstream/master as the specified revision, and for an arbitrary valid commit hash. TODO: - ensure display init enabled w/GENERIC_LINEAR_FRAMEBUFFER selected ? - add logic to determine if recompilation needed ? Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile D payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch D payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch D payloads/external/tianocore/patches/03_Library_EndofDXE.patch D payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch D payloads/external/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch D payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch D payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch D payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch 10 files changed, 29 insertions(+), 2,951 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31543/1 diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index a30fc31..79e09e6 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -11,28 +11,22 @@ default TIANOCORE_STABLE help Select which version of Tianocore to build (default is to build stable) - stable: a version of Tianocore that builds without any errors - master: most recent version from upstream Tianocore repository + stable: MrChromebox's customized version of Tianocore which works on most + (all?) x86_64 devices revision: use specific commit or branch to build Tianocore (specified by user) config TIANOCORE_STABLE bool "stable" help - Select this option to build the stable tianocore version - i.e. a version of Tianocore that builds without any errors - -config TIANOCORE_MASTER - bool "master" - help - Select this option to build the master tianocore version - i.e. most recent version from upstream Tianocore repository + Select this option to build using MrChromebox's custom Tianocore tree + i.e. a version of Tianocore that builds without any errors and just works config TIANOCORE_REVISION bool "git revision" help Select this option if you have a specific commit or branch - that you want to use as the revision from which to - build Tianocore. + that you want to use from either MrChromebox's tree or upstream + EDK2 from which to build Tianocore. You will be able to specify the name of a branch or a commit id later. @@ -42,7 +36,7 @@ config TIANOCORE_REVISION_ID string "Insert a commit's SHA-1 or a branch name" depends on TIANOCORE_REVISION - default "origin/master" + default "upstream/master" help The commit's SHA-1 or branch name of the revision to use. diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index bd02f48..cf22eea 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -16,15 +16,15 @@ # force the shell to bash - the edksetup.sh script doesn't work with dash export SHELL := env bash -# STABLE_COMMIT_ID represent official edk2 release, currently UDK2018 -STABLE_COMMIT_ID=3e72ffe8afdd03f1f89eba65c921cbdcb004cfee -TAG-$(CONFIG_TIANOCORE_MASTER)=origin/master -TAG-$(CONFIG_TIANOCORE_STABLE)=$(STABLE_COMMIT_ID) -TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID) - project_name=Tianocore project_dir=$(CURDIR)/tianocore -project_git_repo=https://github.com/tianocore/edk2 +project_git_repo=https://github.com/mrchromebox/edk2 +project_git_branch=coreboot_fb +upstream_git_repo=https://github.com/tianocore/edk2 + +# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch +TAG-$(CONFIG_TIANOCORE_STABLE)=origin/$(project_git_branch) +TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID) export EDK_TOOLS_PATH=$(project_dir)/BaseTools @@ -48,35 +48,25 @@ $(project_dir): echo " Cloning $(project_name) from Git" - git clone $(project_git_repo) $(project_dir) + git clone --single-branch --branch $(project_git_branch) $(project_git_repo) $(project_dir); \ + cd $(project_dir); \ + git remote add upstream $(upstream_git_repo) -fetch: $(project_dir) - cd $(project_dir); \ + +$(project_dir)/.version_$(TAG-y): $(project_dir) + cd $(project_dir); \ + echo " Fetching new commits from the $(project_name) repo"; \ + git fetch --multiple origin upstream; \ git show $(TAG-y) >/dev/null 2>&1 ; \ - if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ - echo " Fetching new commits from the $(project_name) repo"; \ - git fetch; \ - fi - -$(project_dir)/.version_$(TAG-y): fetch - if ! [[ -e $(project_dir)/.version_$(STABLE_COMMIT_ID) ]] || \ - [ "$(TAG-y)" = "origin/master" ] ; then \ - rm -f .version_*; \ - echo " Checking out $(project_name) revision $(TAG-y)"; \ - cd $(project_dir); \ - git checkout master; \ + if [ $$? -eq 0 ]; then \ + echo " Checking out $(project_name) revision $(TAG-y)"; \ + git checkout $(project_git_branch); \ git branch -D coreboot 2>/dev/null; \ git checkout -b coreboot $(TAG-y); \ - for patch in $(CURDIR)/patches/*.patch; do \ - echo "Applying $$patch"; \ - cd $(project_dir); \ - git am --keep-cr --ignore-space-change $$patch || \ - ( echo " Error when applying patches.\n"; git am --abort; exit 1; ); \ - done; \ - if ! [ "$(TAG-y)" = "origin/master" ] ; then \ - touch $(project_dir)/.version_$(STABLE_COMMIT_ID); \ - fi; \ - fi; \ + else \ + echo " $(TAG-y) is not a valid git reference"; \ + exit 1; \ + fi checktools: echo "Checking uuid-dev..." diff --git a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch b/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch deleted file mode 100644 index 7036f36..0000000 --- a/payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch +++ /dev/null @@ -1,65 +0,0 @@ -From c3da734cd08117ce2d5cd48367f5a94848aa9321 Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 11:23:38 -0800 -Subject: [PATCH] PCI: use Duet's PciNoEnumeration - ---- - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 4 ++-- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 7 ++----- - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 ++----- - 3 files changed, 6 insertions(+), 12 deletions(-) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index 7994f0c94928..d71b3ec55690 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - # - # PCI Support - # --INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf --INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf -+INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # ISA Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index ace1bc0a3726..0f4e475187ee 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -450,11 +450,8 @@ - # - # PCI Support - # -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { -- <LibraryClasses> -- PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf -- } -+ DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+ DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # SCSI/ATA/IDE/DISK Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index 2492142b972d..97bb0a8ae0a1 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -451,11 +451,8 @@ - # - # PCI Support - # -- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { -- <LibraryClasses> -- PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf -- } -+ DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -+ DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - - # - # SCSI/ATA/IDE/DISK Support --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch b/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch deleted file mode 100644 index 9c61263..0000000 --- a/payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch +++ /dev/null @@ -1,2551 +0,0 @@ -From e72cac80c845429b042c7f9c36ede642cbe9e150 Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Tue, 18 Jul 2017 15:50:38 -0600 -Subject: [PATCH] Rebasing - ---- - CorebootModulePkg/CorebootModulePkg.dec | 8 + - .../Include/Guid/LdrMemoryDescriptor.h | 33 + - .../Include/Guid/PciExpressBaseAddress.h | 46 + - .../Include/Guid/PciOptionRomTable.h | 41 + - .../Library/CorebootBdsLib/BdsPlatform.c | 1731 +++++++++++++++++ - .../Library/CorebootBdsLib/BdsPlatform.h | 288 +++ - .../Library/CorebootBdsLib/PlatformBds.inf | 65 + - .../Library/CorebootBdsLib/PlatformData.c | 161 ++ - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 5 +- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 12 +- - .../CorebootPayloadPkgIa32X64.dsc | 12 +- - 11 files changed, 2388 insertions(+), 14 deletions(-) - create mode 100644 CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h - create mode 100644 CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h - create mode 100644 CorebootModulePkg/Include/Guid/PciOptionRomTable.h - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c - -diff --git a/CorebootModulePkg/CorebootModulePkg.dec b/CorebootModulePkg/CorebootModulePkg.dec -index 7f1309bdae61..20932a1d0467 100644 ---- a/CorebootModulePkg/CorebootModulePkg.dec -+++ b/CorebootModulePkg/CorebootModulePkg.dec -@@ -33,8 +33,16 @@ - gUefiCorebootModulePkgTokenSpaceGuid = {0xe6ff49a0, 0x15df, 0x48fd, {0x9a, 0xcf, 0xd7, 0xdc, 0x27, 0x1b, 0x39, 0xd5}} - gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}} - gUefiFrameBufferInfoGuid = {0xdc2cd8bd, 0x402c, 0x4dc4, {0x9b, 0xe0, 0xc, 0x43, 0x2b, 0x7, 0xfa, 0x34}} -+ gEfiPciExpressBaseAddressGuid = {0x3677d529, 0x326f, 0x4603, {0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0 }} - gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}} - -+ ## Include/Guid/PciOptionRomTable.h -+ gEfiPciOptionRomTableGuid = { 0x7462660F, 0x1CBD, 0x48DA, { 0xAD, 0x11, 0x91, 0x71, 0x79, 0x13, 0x83, 0x1C }} -+ -+ ## Include/Guid/LdrMemoryDescriptor.h -+ gLdrMemoryDescriptorGuid = { 0x7701d7e5, 0x7d1d, 0x4432, { 0xa4, 0x68, 0x67, 0x3d, 0xab, 0x8a, 0xde, 0x60 }} -+ -+ - - [Ppis] - -diff --git a/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h -new file mode 100644 -index 000000000000..38a997deea0c ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h -@@ -0,0 +1,33 @@ -+/** @file -+ Guid is for GUIDED HOB of LDR memory descriptor. -+ -+Copyright (c) 2011, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+**/ -+ -+#ifndef __LDR_MEMORY_DESCRIPTOR__ -+#define __LDR_MEMORY_DESCRIPTOR__ -+ -+#define LDR_MEMORY_DESCRIPTOR_GUID \ -+ { 0x7701d7e5, 0x7d1d, 0x4432, {0xa4, 0x68, 0x67, 0x3d, 0xab, 0x8a, 0xde, 0x60}} -+ -+#pragma pack(1) -+ -+typedef struct { -+ EFI_HOB_GUID_TYPE Hob; -+ UINTN MemDescCount; -+ EFI_MEMORY_DESCRIPTOR *MemDesc; -+} MEMORY_DESC_HOB; -+ -+#pragma pack() -+ -+extern EFI_GUID gLdrMemoryDescriptorGuid; -+ -+#endif -diff --git a/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h -new file mode 100644 -index 000000000000..ff554383c11b ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h -@@ -0,0 +1,46 @@ -+/** @file -+ -+Copyright (c) 2006, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ PciExpressBaseAddress.h -+ -+Abstract: -+ -+ -+ GUIDs used for PciExpress Base Address -+ -+**/ -+ -+#ifndef _EFI_PCI_EXPRESS_BASE_ADDRESS_H_ -+#define _EFI_PCI_EXPRESS_BASE_ADDRESS_H_ -+ -+#define EFI_PCI_EXPRESS_BASE_ADDRESS_GUID \ -+ { \ -+ 0x3677d529, 0x326f, 0x4603, {0xa9, 0x26, 0xea, 0xac, 0xe0, 0x1d, 0xcb, 0xb0} \ -+ } -+ -+// -+// Following structure defines PCI Express Base Address information. -+// This information is platform specific, and built into hob in PEI phase. -+// It can be consumed by PEI PCI driver and DXE PCI driver. -+// -+#pragma pack(1) -+typedef struct _EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION { -+ UINT32 HostBridgeNumber; -+ UINT32 RootBridgeNumber; -+ UINT64 PciExpressBaseAddress; -+} EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION; -+#pragma pack() -+ -+extern EFI_GUID gEfiPciExpressBaseAddressGuid; -+ -+#endif -diff --git a/CorebootModulePkg/Include/Guid/PciOptionRomTable.h b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h -new file mode 100644 -index 000000000000..a2fb99710a69 ---- /dev/null -+++ b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h -@@ -0,0 +1,41 @@ -+/** @file -+ GUID and data structure used to describe the list of PCI Option ROMs present in a system. -+ -+Copyright (c) 2006, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+**/ -+ -+#ifndef __PCI_OPTION_ROM_TABLE_GUID_H_ -+#define __PCI_OPTION_ROM_TABLE_GUID_H_ -+ -+#define EFI_PCI_OPTION_ROM_TABLE_GUID \ -+ { 0x7462660f, 0x1cbd, 0x48da, {0xad, 0x11, 0x91, 0x71, 0x79, 0x13, 0x83, 0x1c } } -+ -+extern EFI_GUID gEfiPciOptionRomTableGuid; -+ -+typedef struct { -+ EFI_PHYSICAL_ADDRESS RomAddress; -+ EFI_MEMORY_TYPE MemoryType; -+ UINT32 RomLength; -+ UINT32 Seg; -+ UINT8 Bus; -+ UINT8 Dev; -+ UINT8 Func; -+ BOOLEAN ExecutedLegacyBiosImage; -+ BOOLEAN DontLoadEfiRom; -+} EFI_PCI_OPTION_ROM_DESCRIPTOR; -+ -+typedef struct { -+ UINT64 PciOptionRomCount; -+ EFI_PCI_OPTION_ROM_DESCRIPTOR *PciOptionRomDescriptors; -+} EFI_PCI_OPTION_ROM_TABLE; -+ -+#endif // __PCI_OPTION_ROM_TABLE_GUID_H_ -+ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -new file mode 100644 -index 000000000000..b6253a17f8ea ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -@@ -0,0 +1,1731 @@ -+/*++ -+ -+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ BdsPlatform.c -+ -+Abstract: -+ -+ This file include all platform action which can be customized -+ by IBV/OEM. -+ -+--*/ -+ -+#include "BdsPlatform.h" -+ -+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0) -+ -+extern BOOLEAN gConnectAllHappened; -+extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath; -+ -+EFI_GUID *gTableGuidArray[] = { -+ &gEfiAcpi20TableGuid, &gEfiAcpiTableGuid, &gEfiSmbiosTableGuid, &gEfiMpsTableGuid -+ }; -+ -+// -+// BDS Platform Functions -+// -+ -+VOID -+GetSystemTablesFromHob ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ Find GUID'ed HOBs that contain EFI_PHYSICAL_ADDRESS of ACPI, SMBIOS, MPs tables -+ -+Arguments: -+ None -+ -+Returns: -+ None. -+ -+--*/ -+{ -+ EFI_PEI_HOB_POINTERS GuidHob; -+ EFI_PEI_HOB_POINTERS HobStart; -+ EFI_PHYSICAL_ADDRESS *Table; -+ UINTN Index; -+ -+ // -+ // Get Hob List -+ // -+ HobStart.Raw = GetHobList (); -+ // -+ // Iteratively add ACPI Table, SMBIOS Table, MPS Table to EFI System Table -+ // -+ for (Index = 0; Index < ARRAY_SIZE (gTableGuidArray); ++Index) { -+ GuidHob.Raw = GetNextGuidHob (gTableGuidArray[Index], HobStart.Raw); -+ if (GuidHob.Raw != NULL) { -+ Table = GET_GUID_HOB_DATA (GuidHob.Guid); -+ if (Table != NULL) { -+ // -+ // Check if Mps Table/Smbios Table/Acpi Table exists in E/F seg, -+ // According to UEFI Spec, we should make sure Smbios table, -+ // ACPI table and Mps tables kept in memory of specified type -+ // -+ ConvertSystemTable(gTableGuidArray[Index], (VOID**)&Table); -+ gBS->InstallConfigurationTable (gTableGuidArray[Index], (VOID *)Table); -+ } -+ } -+ } -+ -+ return ; -+} -+ -+#if 0 -+VOID -+PrintMemoryMap ( -+ VOID -+ ) -+{ -+ EFI_MEMORY_DESCRIPTOR *MemMap; -+ EFI_MEMORY_DESCRIPTOR *MemMapPtr; -+ UINTN MemMapSize; -+ UINTN MapKey, DescriptorSize; -+ UINTN Index; -+ UINT32 DescriptorVersion; -+ UINT64 Bytes; -+ EFI_STATUS Status; -+ -+ MemMapSize = 0; -+ MemMap = NULL; -+ Status = gBS->GetMemoryMap (&MemMapSize, MemMap, &MapKey, &DescriptorSize, &DescriptorVersion); -+ ASSERT (Status == EFI_BUFFER_TOO_SMALL); -+ MemMapSize += EFI_PAGE_SIZE; -+ Status = gBS->AllocatePool (EfiBootServicesData, MemMapSize, &MemMap); -+ ASSERT (Status == EFI_SUCCESS); -+ Status = gBS->GetMemoryMap (&MemMapSize, MemMap, &MapKey, &DescriptorSize, &DescriptorVersion); -+ ASSERT (Status == EFI_SUCCESS); -+ MemMapPtr = MemMap; -+ -+ ASSERT (DescriptorVersion == EFI_MEMORY_DESCRIPTOR_VERSION); -+ -+ for (Index = 0; Index < MemMapSize / DescriptorSize; Index ++) { -+ Bytes = LShiftU64 (MemMap->NumberOfPages, 12); -+ DEBUG ((EFI_D_ERROR, "%lX-%lX %lX %lX %X\n", -+ MemMap->PhysicalStart, -+ MemMap->PhysicalStart + Bytes - 1, -+ MemMap->NumberOfPages, -+ MemMap->Attribute, -+ (UINTN)MemMap->Type)); -+ MemMap = (EFI_MEMORY_DESCRIPTOR *)((UINTN)MemMap + DescriptorSize); -+ } -+ -+ gBS->FreePool (MemMapPtr); -+} -+#endif -+ -+VOID -+UpdateMemoryMap ( -+ VOID -+ ) -+{ -+ EFI_STATUS Status; -+ EFI_PEI_HOB_POINTERS GuidHob; -+ VOID *Table; -+ MEMORY_DESC_HOB MemoryDescHob; -+ UINTN Index; -+ EFI_PHYSICAL_ADDRESS Memory; -+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; -+ -+ GuidHob.Raw = GetFirstGuidHob (&gLdrMemoryDescriptorGuid); -+ if (GuidHob.Raw == NULL) { -+ DEBUG ((EFI_D_ERROR, "Fail to get gEfiLdrMemoryDescriptorGuid from GUID HOB LIST!\n")); -+ return; -+ } -+ Table = GET_GUID_HOB_DATA (GuidHob.Guid); -+ if (Table == NULL) { -+ DEBUG ((EFI_D_ERROR, "Fail to get gEfiLdrMemoryDescriptorGuid from GUID HOB LIST!\n")); -+ return; -+ } -+ MemoryDescHob.MemDescCount = *(UINTN *)Table; -+ MemoryDescHob.MemDesc = *(EFI_MEMORY_DESCRIPTOR **)((UINTN)Table + sizeof(UINTN)); -+ -+ // -+ // Add ACPINVS, ACPIReclaim, and Reserved memory to MemoryMap -+ // -+ for (Index = 0; Index < MemoryDescHob.MemDescCount; Index++) { -+ if (MemoryDescHob.MemDesc[Index].PhysicalStart < 0x100000) { -+ continue; -+ } -+ if (MemoryDescHob.MemDesc[Index].PhysicalStart >= 0x100000000ULL) { -+ continue; -+ } -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiReservedMemoryType) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesCode) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIReclaimMemory) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIMemoryNVS)) { -+ DEBUG ((EFI_D_ERROR, "PhysicalStart - 0x%016lx, ", MemoryDescHob.MemDesc[Index].PhysicalStart)); -+ DEBUG ((EFI_D_ERROR, "PageNumber - 0x%016lx, ", MemoryDescHob.MemDesc[Index].NumberOfPages)); -+ DEBUG ((EFI_D_ERROR, "Attribute - 0x%016lx, ", MemoryDescHob.MemDesc[Index].Attribute)); -+ DEBUG ((EFI_D_ERROR, "Type - 0x%08x\n", MemoryDescHob.MemDesc[Index].Type)); -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesCode)) { -+ // -+ // For RuntimeSevicesData and RuntimeServicesCode, they are BFV or DxeCore. -+ // The memory type is assigned in EfiLdr -+ // -+ Status = gDS->GetMemorySpaceDescriptor (MemoryDescHob.MemDesc[Index].PhysicalStart, &Descriptor); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ if (Descriptor.GcdMemoryType != EfiGcdMemoryTypeReserved) { -+ // -+ // BFV or tested DXE core -+ // -+ continue; -+ } -+ // -+ // Untested DXE Core region, free and remove -+ // -+ Status = gDS->FreeMemorySpace ( -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT) -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "FreeMemorySpace fail - %r!\n", Status)); -+ continue; -+ } -+ Status = gDS->RemoveMemorySpace ( -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT) -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "RemoveMemorySpace fail - %r!\n", Status)); -+ continue; -+ } -+ -+ // -+ // Convert Runtime type to BootTime type -+ // -+ if (MemoryDescHob.MemDesc[Index].Type == EfiRuntimeServicesData) { -+ MemoryDescHob.MemDesc[Index].Type = EfiBootServicesData; -+ } else { -+ MemoryDescHob.MemDesc[Index].Type = EfiBootServicesCode; -+ } -+ -+ // -+ // PassThrough, let below code add and alloate. -+ // -+ } -+ // -+ // ACPI or reserved memory -+ // -+ Status = gDS->AddMemorySpace ( -+ EfiGcdMemoryTypeSystemMemory, -+ MemoryDescHob.MemDesc[Index].PhysicalStart, -+ LShiftU64 (MemoryDescHob.MemDesc[Index].NumberOfPages, EFI_PAGE_SHIFT), -+ MemoryDescHob.MemDesc[Index].Attribute -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "AddMemorySpace fail - %r!\n", Status)); -+ if ((MemoryDescHob.MemDesc[Index].Type == EfiACPIReclaimMemory) || -+ (MemoryDescHob.MemDesc[Index].Type == EfiACPIMemoryNVS)) { -+ // -+ // For EfiACPIReclaimMemory and EfiACPIMemoryNVS, it must success. -+ // For EfiReservedMemoryType, there maybe overlap. So skip check here. -+ // -+// ASSERT_EFI_ERROR (Status); -+ } -+ continue; -+ } -+ -+ Memory = MemoryDescHob.MemDesc[Index].PhysicalStart; -+ Status = gBS->AllocatePages ( -+ AllocateAddress, -+ (EFI_MEMORY_TYPE)MemoryDescHob.MemDesc[Index].Type, -+ (UINTN)MemoryDescHob.MemDesc[Index].NumberOfPages, -+ &Memory -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((EFI_D_ERROR, "AllocatePages fail - %r!\n", Status)); -+ // -+ // For the page added, it must be allocated. -+ // -+// ASSERT_EFI_ERROR (Status); -+ continue; -+ } -+ } -+ } -+ -+} -+ -+EFI_STATUS -+DisableUsbLegacySupport( -+ void -+ ) -+/*++ -+ -+Routine Description: -+ Disabble the USB legacy Support in all Ehci and Uhci. -+ This function assume all PciIo handles have been created in system. -+ -+Arguments: -+ None -+ -+Returns: -+ EFI_SUCCESS -+ EFI_NOT_FOUND -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_HANDLE *HandleArray; -+ UINTN HandleArrayCount; -+ UINTN Index; -+ EFI_PCI_IO_PROTOCOL *PciIo; -+ UINT8 Class[3]; -+ UINT16 Command; -+ UINT32 HcCapParams; -+ UINT32 ExtendCap; -+ UINT32 Value; -+ UINT32 TimeOut; -+ -+ // -+ // Find the usb host controller -+ // -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiPciIoProtocolGuid, -+ NULL, -+ &HandleArrayCount, -+ &HandleArray -+ ); -+ if (!EFI_ERROR (Status)) { -+ for (Index = 0; Index < HandleArrayCount; Index++) { -+ Status = gBS->HandleProtocol ( -+ HandleArray[Index], -+ &gEfiPciIoProtocolGuid, -+ (VOID **)&PciIo -+ ); -+ if (!EFI_ERROR (Status)) { -+ // -+ // Find the USB host controller controller -+ // -+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class); -+ if (!EFI_ERROR (Status)) { -+ if ((PCI_CLASS_SERIAL == Class[2]) && -+ (PCI_CLASS_SERIAL_USB == Class[1])) { -+ if (PCI_IF_UHCI == Class[0]) { -+ // -+ // Found the UHCI, then disable the legacy support -+ // -+ Command = 0; -+ Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0xC0, 1, &Command); -+ } else if (PCI_IF_EHCI == Class[0]) { -+ // -+ // Found the EHCI, then disable the legacy support -+ // -+ Status = PciIo->Mem.Read ( -+ PciIo, -+ EfiPciIoWidthUint32, -+ 0, //EHC_BAR_INDEX -+ (UINT64) 0x08, //EHC_HCCPARAMS_OFFSET -+ 1, -+ &HcCapParams -+ ); -+ -+ ExtendCap = (HcCapParams >> 8) & 0xFF; -+ // -+ // Disable the SMI in USBLEGCTLSTS firstly -+ // -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value); -+ Value &= 0xFFFF0000; -+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap + 0x4, 1, &Value); -+ -+ // -+ // Get EHCI Ownership from legacy bios -+ // -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ Value |= (0x1 << 24); -+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ -+ TimeOut = 40; -+ while (TimeOut--) { -+ gBS->Stall (500); -+ -+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ExtendCap, 1, &Value); -+ -+ if ((Value & 0x01010000) == 0x01000000) { -+ break; -+ } -+ } -+ } -+ } -+ } -+ } -+ } -+ } else { -+ return Status; -+ } -+ gBS->FreePool (HandleArray); -+ return EFI_SUCCESS; -+} -+ -+ -+VOID -+EFIAPI -+PlatformBdsInit ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Platform Bds init. Include the platform firmware vendor, revision -+ and so crc check. -+ -+Arguments: -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ GetSystemTablesFromHob (); -+ -+ UpdateMemoryMap (); -+ -+ // -+ // Append Usb Keyboard short form DevicePath into "ConInDev" -+ // -+ BdsLibUpdateConsoleVariable ( -+ VarConsoleInpDev, -+ (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, -+ NULL -+ ); -+} -+ -+UINT64 -+GetPciExpressBaseAddressForRootBridge ( -+ IN UINTN HostBridgeNumber, -+ IN UINTN RootBridgeNumber -+ ) -+/*++ -+ -+Routine Description: -+ This routine is to get PciExpress Base Address for this RootBridge -+ -+Arguments: -+ HostBridgeNumber - The number of HostBridge -+ RootBridgeNumber - The number of RootBridge -+ -+Returns: -+ UINT64 - PciExpressBaseAddress for this HostBridge and RootBridge -+ -+--*/ -+{ -+ EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION *PciExpressBaseAddressInfo; -+ UINTN BufferSize; -+ UINT32 Index; -+ UINT32 Number; -+ EFI_PEI_HOB_POINTERS GuidHob; -+ -+ // -+ // Get PciExpressAddressInfo Hob -+ // -+ PciExpressBaseAddressInfo = NULL; -+ BufferSize = 0; -+ GuidHob.Raw = GetFirstGuidHob (&gEfiPciExpressBaseAddressGuid); -+ if (GuidHob.Raw != NULL) { -+ PciExpressBaseAddressInfo = GET_GUID_HOB_DATA (GuidHob.Guid); -+ BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob.Guid); -+ } else { -+ return 0; -+ } -+ -+ // -+ // Search the PciExpress Base Address in the Hob for current RootBridge -+ // -+ Number = (UINT32)(BufferSize / sizeof(EFI_PCI_EXPRESS_BASE_ADDRESS_INFORMATION)); -+ for (Index = 0; Index < Number; Index++) { -+ if ((PciExpressBaseAddressInfo[Index].HostBridgeNumber == HostBridgeNumber) && -+ (PciExpressBaseAddressInfo[Index].RootBridgeNumber == RootBridgeNumber)) { -+ return PciExpressBaseAddressInfo[Index].PciExpressBaseAddress; -+ } -+ } -+ -+ // -+ // Do not find the PciExpress Base Address in the Hob -+ // -+ return 0; -+} -+ -+VOID -+PatchPciRootBridgeDevicePath ( -+ IN UINTN HostBridgeNumber, -+ IN UINTN RootBridgeNumber, -+ IN PLATFORM_ROOT_BRIDGE_DEVICE_PATH *RootBridge -+ ) -+{ -+ UINT64 PciExpressBase; -+ -+ PciExpressBase = GetPciExpressBaseAddressForRootBridge (HostBridgeNumber, RootBridgeNumber); -+ -+ DEBUG ((EFI_D_INFO, "Get PciExpress Address from Hob: 0x%X\n", PciExpressBase)); -+ -+ if (PciExpressBase != 0) { -+ RootBridge->PciRootBridge.HID = EISA_PNP_ID(0x0A08); -+ } -+} -+ -+EFI_STATUS -+ConnectRootBridge ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect RootBridge -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ EFI_SUCCESS - Connect RootBridge successfully. -+ EFI_STATUS - Connect RootBridge fail. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_HANDLE RootHandle; -+ -+ // -+ // Patch Pci Root Bridge Device Path -+ // -+ PatchPciRootBridgeDevicePath (0, 0, &gPlatformRootBridge0); -+ -+ // -+ // Make all the PCI_IO protocols on PCI Seg 0 show up -+ // -+ BdsLibConnectDevicePath (gPlatformRootBridges[0]); -+ -+ Status = gBS->LocateDevicePath ( -+ &gEfiDevicePathProtocolGuid, -+ &gPlatformRootBridges[0], -+ &RootHandle -+ ); -+ DEBUG ((EFI_D_INFO, "Pci Root bridge handle is 0x%X\n", RootHandle)); -+ -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PrepareLpcBridgeDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add IsaKeyboard to ConIn, -+ add IsaSerial to ConOut, ConIn, ErrOut. -+ LPC Bridge: 06 01 00 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - LPC bridge is added to ConOut, ConIn, and ErrOut. -+ EFI_STATUS - No LPC bridge is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; -+ -+ DevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ TempDevicePath = DevicePath; -+ -+ // -+ // Register Keyboard -+ // -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnpPs2KeyboardDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ -+ // -+ // Register COM1 -+ // -+ DevicePath = TempDevicePath; -+ gPnp16550ComPortDeviceNode.UID = 0; -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ // -+ // Register COM2 -+ // -+ DevicePath = TempDevicePath; -+ gPnp16550ComPortDeviceNode.UID = 1; -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+GetGopDevicePath ( -+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath, -+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath -+ ) -+{ -+ UINTN Index; -+ EFI_STATUS Status; -+ EFI_HANDLE PciDeviceHandle; -+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath; -+ UINTN GopHandleCount; -+ EFI_HANDLE *GopHandleBuffer; -+ -+ if (PciDevicePath == NULL || GopDevicePath == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // -+ // Initialize the GopDevicePath to be PciDevicePath -+ // -+ *GopDevicePath = PciDevicePath; -+ TempPciDevicePath = PciDevicePath; -+ -+ Status = gBS->LocateDevicePath ( -+ &gEfiDevicePathProtocolGuid, -+ &TempPciDevicePath, -+ &PciDeviceHandle -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ // -+ // Try to connect this handle, so that GOP driver could start on this -+ // device and create child handles with GraphicsOutput Protocol installed -+ // on them, then we get device paths of these child handles and select -+ // them as possible console device. -+ // -+ gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE); -+ -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiGraphicsOutputProtocolGuid, -+ NULL, -+ &GopHandleCount, -+ &GopHandleBuffer -+ ); -+ if (!EFI_ERROR (Status)) { -+ // -+ // Add all the child handles as possible Console Device -+ // -+ for (Index = 0; Index < GopHandleCount; Index++) { -+ Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ if (CompareMem ( -+ PciDevicePath, -+ TempDevicePath, -+ GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH -+ ) == 0) { -+ // -+ // In current implementation, we only enable one of the child handles -+ // as console device, i.e. sotre one of the child handle's device -+ // path to variable "ConOut" -+ // In future, we could select all child handles to be console device -+ // -+ -+ *GopDevicePath = TempDevicePath; -+ -+ // -+ // Delete the PCI device's path that added by GetPlugInPciVgaDevicePath() -+ // Add the integrity GOP device path. -+ // -+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, NULL, PciDevicePath); -+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, TempDevicePath, NULL); -+ } -+ } -+ gBS->FreePool (GopHandleBuffer); -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PreparePciVgaDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add PCI VGA to ConOut. -+ PCI VGA: 03 00 00 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI VGA is added to ConOut. -+ EFI_STATUS - No PCI VGA device is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath; -+ -+ DevicePath = NULL; -+ GopDevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ GetGopDevicePath (DevicePath, &GopDevicePath); -+ DevicePath = GopDevicePath; -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PreparePciSerialDevicePath ( -+ IN EFI_HANDLE DeviceHandle -+ ) -+/*++ -+ -+Routine Description: -+ -+ Add PCI Serial to ConOut, ConIn, ErrOut. -+ PCI Serial: 07 00 02 -+ -+Arguments: -+ -+ DeviceHandle - Handle of PCIIO protocol. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut. -+ EFI_STATUS - No PCI Serial device is added. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ EFI_DEVICE_PATH_PROTOCOL *DevicePath; -+ -+ DevicePath = NULL; -+ Status = gBS->HandleProtocol ( -+ DeviceHandle, -+ &gEfiDevicePathProtocolGuid, -+ (VOID*)&DevicePath -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode); -+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode); -+ -+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL); -+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+DetectAndPreparePlatformPciDevicePath ( -+ BOOLEAN DetectVgaOnly -+ ) -+/*++ -+ -+Routine Description: -+ -+ Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut -+ -+Arguments: -+ -+ DetectVgaOnly - Only detect VGA device if it's TRUE. -+ -+Returns: -+ -+ EFI_SUCCESS - PCI Device check and Console variable update successfully. -+ EFI_STATUS - PCI Device check or Console variable update fail. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINTN HandleCount; -+ EFI_HANDLE *HandleBuffer; -+ UINTN Index; -+ EFI_PCI_IO_PROTOCOL *PciIo; -+ PCI_TYPE00 Pci; -+ -+ // -+ // Start to check all the PciIo to find all possible device -+ // -+ HandleCount = 0; -+ HandleBuffer = NULL; -+ Status = gBS->LocateHandleBuffer ( -+ ByProtocol, -+ &gEfiPciIoProtocolGuid, -+ NULL, -+ &HandleCount, -+ &HandleBuffer -+ ); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ for (Index = 0; Index < HandleCount; Index++) { -+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID*)&PciIo); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ -+ // -+ // Check for all PCI device -+ // -+ Status = PciIo->Pci.Read ( -+ PciIo, -+ EfiPciIoWidthUint32, -+ 0, -+ sizeof (Pci) / sizeof (UINT32), -+ &Pci -+ ); -+ if (EFI_ERROR (Status)) { -+ continue; -+ } -+ -+ if (!DetectVgaOnly) { -+ // -+ // Here we decide whether it is LPC Bridge -+ // -+ if ((IS_PCI_LPC (&Pci)) || -+ ((IS_PCI_ISA_PDECODE (&Pci)) && (Pci.Hdr.VendorId == 0x8086) && (Pci.Hdr.DeviceId == 0x7110))) { -+ // -+ // Add IsaKeyboard to ConIn, -+ // add IsaSerial to ConOut, ConIn, ErrOut -+ // -+ DEBUG ((EFI_D_INFO, "Find the LPC Bridge device\n")); -+ PrepareLpcBridgeDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ // -+ // Here we decide which Serial device to enable in PCI bus -+ // -+ if (IS_PCI_16550SERIAL (&Pci)) { -+ // -+ // Add them to ConOut, ConIn, ErrOut. -+ // -+ DEBUG ((EFI_D_INFO, "Find the 16550 SERIAL device\n")); -+ PreparePciSerialDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ } -+ -+ // -+ // Here we decide which VGA device to enable in PCI bus -+ // -+ if (IS_PCI_VGA (&Pci)) { -+ // -+ // Add them to ConOut. -+ // -+ DEBUG ((EFI_D_INFO, "Find the VGA device\n")); -+ PreparePciVgaDevicePath (HandleBuffer[Index]); -+ continue; -+ } -+ } -+ -+ gBS->FreePool (HandleBuffer); -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+PlatformBdsConnectConsole ( -+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect the predefined platform default console device. Always try to find -+ and enable the vga device if have. -+ -+Arguments: -+ -+ PlatformConsole - Predefined platform default console device array. -+ -+Returns: -+ -+ EFI_SUCCESS - Success connect at least one ConIn and ConOut -+ device, there must have one ConOut device is -+ active vga device. -+ -+ EFI_STATUS - Return the status of -+ BdsLibConnectAllDefaultConsoles () -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINTN Index; -+ EFI_DEVICE_PATH_PROTOCOL *VarConout; -+ EFI_DEVICE_PATH_PROTOCOL *VarConin; -+ UINTN DevicePathSize; -+ -+ // -+ // Connect RootBridge -+ // -+ ConnectRootBridge (); -+ -+ VarConout = BdsLibGetVariableAndSize ( -+ VarConsoleOut, -+ &gEfiGlobalVariableGuid, -+ &DevicePathSize -+ ); -+ VarConin = BdsLibGetVariableAndSize ( -+ VarConsoleInp, -+ &gEfiGlobalVariableGuid, -+ &DevicePathSize -+ ); -+ -+ if (VarConout == NULL || VarConin == NULL) { -+ // -+ // Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut -+ // -+ DetectAndPreparePlatformPciDevicePath (FALSE); -+ -+ // -+ // Have chance to connect the platform default console, -+ // the platform default console is the minimum device group -+ // the platform should support -+ // -+ for (Index = 0; PlatformConsole[Index].DevicePath != NULL; ++Index) { -+ // -+ // Update the console variable with the connect type -+ // -+ if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) { -+ BdsLibUpdateConsoleVariable (VarConsoleInp, PlatformConsole[Index].DevicePath, NULL); -+ } -+ if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) { -+ BdsLibUpdateConsoleVariable (VarConsoleOut, PlatformConsole[Index].DevicePath, NULL); -+ } -+ if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) { -+ BdsLibUpdateConsoleVariable (VarErrorOut, PlatformConsole[Index].DevicePath, NULL); -+ } -+ } -+ } else { -+ // -+ // Only detect VGA device and add them to ConOut -+ // -+ DetectAndPreparePlatformPciDevicePath (TRUE); -+ } -+ -+ // -+ // The ConIn devices connection will start the USB bus, should disable all -+ // Usb legacy support firstly. -+ // Caution: Must ensure the PCI bus driver has been started. Since the -+ // ConnectRootBridge() will create all the PciIo protocol, it's safe here now -+ // -+ Status = DisableUsbLegacySupport(); -+ -+ // -+ // Connect the all the default console with current cosole variable -+ // -+ Status = BdsLibConnectAllDefaultConsoles (); -+ if (EFI_ERROR (Status)) { -+ return Status; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+VOID -+PlatformBdsConnectSequence ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ Connect with predefined platform connect sequence, -+ the OEM/IBV can customize with their own connect sequence. -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ UINTN Index; -+ -+ Index = 0; -+ -+ // -+ // Here we can get the customized platform connect sequence -+ // Notes: we can connect with new variable which record the -+ // last time boots connect device path sequence -+ // -+ while (gPlatformConnectSequence[Index] != NULL) { -+ // -+ // Build the platform boot option -+ // -+ BdsLibConnectDevicePath (gPlatformConnectSequence[Index]); -+ Index++; -+ } -+ -+} -+ -+VOID -+PlatformBdsGetDriverOption ( -+ IN OUT LIST_ENTRY *BdsDriverLists -+ ) -+/*++ -+ -+Routine Description: -+ -+ Load the predefined driver option, OEM/IBV can customize this -+ to load their own drivers -+ -+Arguments: -+ -+ BdsDriverLists - The header of the driver option link list. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ UINTN Index; -+ -+ Index = 0; -+ -+ // -+ // Here we can get the customized platform driver option -+ // -+ while (gPlatformDriverOption[Index] != NULL) { -+ // -+ // Build the platform boot option -+ // -+ BdsLibRegisterNewOption (BdsDriverLists, gPlatformDriverOption[Index], NULL, L"DriverOrder"); -+ Index++; -+ } -+ -+} -+ -+VOID -+PlatformBdsDiagnostics ( -+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel, -+ IN BOOLEAN QuietBoot, -+ IN BASEM_MEMORY_TEST BaseMemoryTest -+ ) -+/*++ -+ -+Routine Description: -+ -+ Perform the platform diagnostic, such like test memory. OEM/IBV also -+ can customize this fuction to support specific platform diagnostic. -+ -+Arguments: -+ -+ MemoryTestLevel - The memory test intensive level -+ -+ QuietBoot - Indicate if need to enable the quiet boot -+ -+ BaseMemoryTest - A pointer to BdsMemoryTest() -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ -+ // -+ // Here we can decide if we need to show -+ // the diagnostics screen -+ // Notes: this quiet boot code should be remove -+ // from the graphic lib -+ // -+ if (QuietBoot) { -+ Status = EnableQuietBoot (PcdGetPtr(PcdLogoFile)); -+ if (EFI_ERROR (Status)) { -+ DisableQuietBoot (); -+ return; -+ } -+ -+ // -+ // Perform system diagnostic -+ // -+ Status = BaseMemoryTest (MemoryTestLevel); -+ if (EFI_ERROR (Status)) { -+ DisableQuietBoot (); -+ } -+ -+ return ; -+ } -+ // -+ // Perform system diagnostic -+ // -+ Status = BaseMemoryTest (MemoryTestLevel); -+} -+ -+VOID -+EFIAPI -+PlatformBdsPolicyBehavior ( -+ IN OUT LIST_ENTRY *DriverOptionList, -+ IN OUT LIST_ENTRY *BootOptionList, -+ IN PROCESS_CAPSULES ProcessCapsules, -+ IN BASEM_MEMORY_TEST BaseMemoryTest -+ ) -+/*++ -+ -+Routine Description: -+ -+ The function will execute with as the platform policy, current policy -+ is driven by boot mode. IBV/OEM can customize this code for their specific -+ policy action. -+ -+Arguments: -+ -+ DriverOptionList - The header of the driver option link list -+ -+ BootOptionList - The header of the boot option link list -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ UINT16 Timeout; -+ EFI_EVENT UserInputDurationTime; -+ UINTN Index; -+ EFI_INPUT_KEY Key; -+ EFI_BOOT_MODE BootMode; -+ -+ // -+ // Init the time out value -+ // -+ Timeout = PcdGet16 (PcdPlatformBootTimeOut); -+ -+ // -+ // Load the driver option as the driver option list -+ // -+ PlatformBdsGetDriverOption (DriverOptionList); -+ -+ // -+ // Get current Boot Mode -+ // -+ Status = BdsLibGetBootMode (&BootMode); -+ DEBUG ((EFI_D_ERROR, "Boot Mode:%x\n", BootMode)); -+ -+ // -+ // Go the different platform policy with different boot mode -+ // Notes: this part code can be change with the table policy -+ // -+ ASSERT (BootMode == BOOT_WITH_FULL_CONFIGURATION); -+ // -+ // Connect platform console -+ // -+ Status = PlatformBdsConnectConsole (gPlatformConsole); -+ if (EFI_ERROR (Status)) { -+ // -+ // Here OEM/IBV can customize with defined action -+ // -+ PlatformBdsNoConsoleAction (); -+ } -+ // -+ // Create a 300ms duration event to ensure user has enough input time to enter Setup -+ // -+ Status = gBS->CreateEvent ( -+ EVT_TIMER, -+ 0, -+ NULL, -+ NULL, -+ &UserInputDurationTime -+ ); -+ ASSERT (Status == EFI_SUCCESS); -+ Status = gBS->SetTimer (UserInputDurationTime, TimerRelative, 3000000); -+ ASSERT (Status == EFI_SUCCESS); -+ // -+ // Memory test and Logo show -+ // -+ PlatformBdsDiagnostics (IGNORE, TRUE, BaseMemoryTest); -+ -+ // -+ // Perform some platform specific connect sequence -+ // -+ PlatformBdsConnectSequence (); -+ -+ // -+ // Give one chance to enter the setup if we -+ // have the time out -+ // -+ // BUGBUG: hard code timeout to 5 second to show logo in graphic mode. -+ Timeout = 5; -+ if (Timeout != 0) { -+ PlatformBdsEnterFrontPage (Timeout, FALSE); -+ } -+ -+ // -+ //BdsLibConnectAll (); -+ //BdsLibEnumerateAllBootOption (BootOptionList); -+ -+ // -+ // Please uncomment above ConnectAll and EnumerateAll code and remove following first boot -+ // checking code in real production tip. -+ // -+ // In BOOT_WITH_FULL_CONFIGURATION boot mode, should always connect every device -+ // and do enumerate all the default boot options. But in development system board, the boot mode -+ // cannot be BOOT_ASSUMING_NO_CONFIGURATION_CHANGES because the machine box -+ // is always open. So the following code only do the ConnectAll and EnumerateAll at first boot. -+ // -+ Status = BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder"); -+ if (EFI_ERROR(Status)) { -+ // -+ // If cannot find "BootOrder" variable, it may be first boot. -+ // Try to connect all devices and enumerate all boot options here. -+ // -+ BdsLibConnectAll (); -+ BdsLibEnumerateAllBootOption (BootOptionList); -+ } -+ -+ // -+ // To give the User a chance to enter Setup here, if user set TimeOut is 0. -+ // BDS should still give user a chance to enter Setup -+ // Check whether the user input after the duration time has expired -+ // -+ gBS->WaitForEvent (1, &UserInputDurationTime, &Index); -+ gBS->CloseEvent (UserInputDurationTime); -+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key); -+ -+ if (!EFI_ERROR (Status)) { -+ // -+ // Enter Setup if user input -+ // -+ Timeout = 0xffff; -+ PlatformBdsEnterFrontPage (Timeout, FALSE); -+ } -+ -+ return ; -+ -+} -+ -+VOID -+EFIAPI -+PlatformBdsBootSuccess ( -+ IN BDS_COMMON_OPTION *Option -+ ) -+/*++ -+ -+Routine Description: -+ -+ Hook point after a boot attempt succeeds. We don't expect a boot option to -+ return, so the EFI 1.0 specification defines that you will default to an -+ interactive mode and stop processing the BootOrder list in this case. This -+ is alos a platform implementation and can be customized by IBV/OEM. -+ -+Arguments: -+ -+ Option - Pointer to Boot Option that succeeded to boot. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ CHAR16 *TmpStr; -+ -+ // -+ // If Boot returned with EFI_SUCCESS and there is not in the boot device -+ // select loop then we need to pop up a UI and wait for user input. -+ // -+ TmpStr = Option->StatusString; -+ if (TmpStr != NULL) { -+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL); -+ gBS->FreePool (TmpStr); -+ } -+} -+ -+VOID -+EFIAPI -+PlatformBdsBootFail ( -+ IN BDS_COMMON_OPTION *Option, -+ IN EFI_STATUS Status, -+ IN CHAR16 *ExitData, -+ IN UINTN ExitDataSize -+ ) -+/*++ -+ -+Routine Description: -+ -+ Hook point after a boot attempt fails. -+ -+Arguments: -+ -+ Option - Pointer to Boot Option that failed to boot. -+ -+ Status - Status returned from failed boot. -+ -+ ExitData - Exit data returned from failed boot. -+ -+ ExitDataSize - Exit data size returned from failed boot. -+ -+Returns: -+ -+ None. -+ -+--*/ -+{ -+ CHAR16 *TmpStr; -+ -+ // -+ // If Boot returned with failed status then we need to pop up a UI and wait -+ // for user input. -+ // -+ TmpStr = Option->StatusString; -+ if (TmpStr != NULL) { -+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL); -+ gBS->FreePool (TmpStr); -+ } -+ -+} -+ -+EFI_STATUS -+PlatformBdsNoConsoleAction ( -+ VOID -+ ) -+/*++ -+ -+Routine Description: -+ -+ This function is remained for IBV/OEM to do some platform action, -+ if there no console device can be connected. -+ -+Arguments: -+ -+ None. -+ -+Returns: -+ -+ EFI_SUCCESS - Direct return success now. -+ -+--*/ -+{ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertSystemTable ( -+ IN EFI_GUID *TableGuid, -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ Convert ACPI Table /Smbios Table /MP Table if its location is lower than Address:0x100000 -+ Assumption here: -+ As in legacy Bios, ACPI/Smbios/MP table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIReclaimMemory/EfiACPIMemoryNVS -+ -+Arguments: -+ TableGuid - Guid of the table -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ EFI_STATUS Status; -+ VOID *AcpiHeader; -+ UINTN AcpiTableLen; -+ -+ // -+ // If match acpi guid (1.0, 2.0, or later), Convert ACPI table according to version. -+ // -+ AcpiHeader = (VOID*)(UINTN)(*(UINT64 *)(*Table)); -+ -+ if (CompareGuid(TableGuid, &gEfiAcpiTableGuid) || CompareGuid(TableGuid, &gEfiAcpi20TableGuid)){ -+ if (((EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Reserved == 0x00){ -+ // -+ // If Acpi 1.0 Table, then RSDP structure doesn't contain Length field, use structure size -+ // -+ AcpiTableLen = sizeof (EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER); -+ } else if (((EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Reserved >= 0x02){ -+ // -+ // If Acpi 2.0 or later, use RSDP Length fied. -+ // -+ AcpiTableLen = ((EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)AcpiHeader)->Length; -+ } else { -+ // -+ // Invalid Acpi Version, return -+ // -+ return EFI_UNSUPPORTED; -+ } -+ Status = ConvertAcpiTable (AcpiTableLen, Table); -+ return Status; -+ } -+ -+ // -+ // If matches smbios guid, convert Smbios table. -+ // -+ if (CompareGuid(TableGuid, &gEfiSmbiosTableGuid)){ -+ Status = ConvertSmbiosTable (Table); -+ return Status; -+ } -+ -+ // -+ // If the table is MP table? -+ // -+ if (CompareGuid(TableGuid, &gEfiMpsTableGuid)){ -+ Status = ConvertMpsTable (Table); -+ return Status; -+ } -+ -+ return EFI_UNSUPPORTED; -+} -+ -+ -+EFI_STATUS -+ConvertAcpiTable ( -+ IN UINTN TableLen, -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ Convert RSDP of ACPI Table if its location is lower than Address:0x100000 -+ Assumption here: -+ As in legacy Bios, ACPI table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIReclaimMemory/EfiACPIMemoryNVS -+ -+Arguments: -+ TableLen - Acpi RSDP length -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ VOID *AcpiTableOri; -+ VOID *AcpiTableNew; -+ EFI_STATUS Status; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ -+ AcpiTableOri = (VOID *)(UINTN)(*(UINT64*)(*Table)); -+ if (((UINTN)AcpiTableOri < 0x100000) && ((UINTN)AcpiTableOri > 0xE0000)) { -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(TableLen), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ AcpiTableNew = (VOID *)(UINTN)BufferPtr; -+ CopyMem (AcpiTableNew, AcpiTableOri, TableLen); -+ } else { -+ AcpiTableNew = AcpiTableOri; -+ } -+ // -+ // Change configuration table Pointer -+ // -+ *Table = AcpiTableNew; -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertSmbiosTable ( -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ -+ Convert Smbios Table if the Location of the SMBios Table is lower than Addres 0x100000 -+ Assumption here: -+ As in legacy Bios, Smbios table is required to place in E/F Seg, -+ So here we just check if the range is F seg, -+ and if Not, assume the Memory type is EfiACPIMemoryNVS/EfiRuntimeServicesData -+Arguments: -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ SMBIOS_TABLE_ENTRY_POINT *SmbiosTableNew; -+ SMBIOS_TABLE_ENTRY_POINT *SmbiosTableOri; -+ EFI_STATUS Status; -+ UINT32 SmbiosEntryLen; -+ UINT32 BufferLen; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ SmbiosTableNew = NULL; -+ SmbiosTableOri = NULL; -+ -+ // -+ // Get Smibos configuration Table -+ // -+ SmbiosTableOri = (SMBIOS_TABLE_ENTRY_POINT *)(UINTN)(*(UINT64*)(*Table)); -+ -+ if ((SmbiosTableOri == NULL) || -+ ((UINTN)SmbiosTableOri > 0x100000) || -+ ((UINTN)SmbiosTableOri < 0xF0000)){ -+ return EFI_SUCCESS; -+ } -+ // -+ // Relocate the Smibos memory -+ // -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ if (SmbiosTableOri->SmbiosBcdRevision != 0x21) { -+ SmbiosEntryLen = SmbiosTableOri->EntryPointLength; -+ } else { -+ // -+ // According to Smbios Spec 2.4, we should set entry point length as 0x1F if version is 2.1 -+ // -+ SmbiosEntryLen = 0x1F; -+ } -+ BufferLen = SmbiosEntryLen + SYS_TABLE_PAD(SmbiosEntryLen) + SmbiosTableOri->TableLength; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(BufferLen), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ SmbiosTableNew = (SMBIOS_TABLE_ENTRY_POINT *)(UINTN)BufferPtr; -+ CopyMem ( -+ SmbiosTableNew, -+ SmbiosTableOri, -+ SmbiosEntryLen -+ ); -+ // -+ // Get Smbios Structure table address, and make sure the start address is 32-bit align -+ // -+ BufferPtr += SmbiosEntryLen + SYS_TABLE_PAD(SmbiosEntryLen); -+ CopyMem ( -+ (VOID *)(UINTN)BufferPtr, -+ (VOID *)(UINTN)(SmbiosTableOri->TableAddress), -+ SmbiosTableOri->TableLength -+ ); -+ SmbiosTableNew->TableAddress = (UINT32)BufferPtr; -+ SmbiosTableNew->IntermediateChecksum = 0; -+ SmbiosTableNew->IntermediateChecksum = -+ CalculateCheckSum8 ((UINT8*)SmbiosTableNew + 0x10, SmbiosEntryLen -0x10); -+ // -+ // Change the SMBIOS pointer -+ // -+ *Table = SmbiosTableNew; -+ -+ return EFI_SUCCESS; -+} -+ -+EFI_STATUS -+ConvertMpsTable ( -+ IN OUT VOID **Table -+ ) -+/*++ -+ -+Routine Description: -+ -+ Convert MP Table if the Location of the SMBios Table is lower than Addres 0x100000 -+ Assumption here: -+ As in legacy Bios, MP table is required to place in E/F Seg, -+ So here we just check if the range is E/F seg, -+ and if Not, assume the Memory type is EfiACPIMemoryNVS/EfiRuntimeServicesData -+Arguments: -+ Table - pointer to the table -+ -+Returns: -+ EFI_SUCEESS - Convert Table successfully -+ Other - Failed -+ -+--*/ -+{ -+ UINT32 Data32; -+ UINT32 FPLength; -+ EFI_LEGACY_MP_TABLE_FLOATING_POINTER *MpsFloatingPointerOri; -+ EFI_LEGACY_MP_TABLE_FLOATING_POINTER *MpsFloatingPointerNew; -+ EFI_LEGACY_MP_TABLE_HEADER *MpsTableOri; -+ EFI_LEGACY_MP_TABLE_HEADER *MpsTableNew; -+ VOID *OemTableOri; -+ VOID *OemTableNew; -+ EFI_STATUS Status; -+ EFI_PHYSICAL_ADDRESS BufferPtr; -+ -+ // -+ // Get MP configuration Table -+ // -+ MpsFloatingPointerOri = (EFI_LEGACY_MP_TABLE_FLOATING_POINTER *)(UINTN)(*(UINT64*)(*Table)); -+ if (!(((UINTN)MpsFloatingPointerOri <= 0x100000) && -+ ((UINTN)MpsFloatingPointerOri >= 0xF0000))){ -+ return EFI_SUCCESS; -+ } -+ // -+ // Get Floating pointer structure length -+ // -+ FPLength = MpsFloatingPointerOri->Length * 16; -+ Data32 = FPLength + SYS_TABLE_PAD (FPLength); -+ MpsTableOri = (EFI_LEGACY_MP_TABLE_HEADER *)(UINTN)(MpsFloatingPointerOri->PhysicalAddress); -+ if (MpsTableOri != NULL) { -+ Data32 += MpsTableOri->BaseTableLength; -+ Data32 += MpsTableOri->ExtendedTableLength; -+ if (MpsTableOri->OemTablePointer != 0x00) { -+ Data32 += SYS_TABLE_PAD (Data32); -+ Data32 += MpsTableOri->OemTableSize; -+ } -+ } else { -+ return EFI_SUCCESS; -+ } -+ // -+ // Relocate memory -+ // -+ BufferPtr = EFI_SYSTEM_TABLE_MAX_ADDRESS; -+ Status = gBS->AllocatePages ( -+ AllocateMaxAddress, -+ EfiACPIMemoryNVS, -+ EFI_SIZE_TO_PAGES(Data32), -+ &BufferPtr -+ ); -+ ASSERT_EFI_ERROR (Status); -+ MpsFloatingPointerNew = (EFI_LEGACY_MP_TABLE_FLOATING_POINTER *)(UINTN)BufferPtr; -+ CopyMem (MpsFloatingPointerNew, MpsFloatingPointerOri, FPLength); -+ // -+ // If Mp Table exists -+ // -+ if (MpsTableOri != NULL) { -+ // -+ // Get Mps table length, including Ext table -+ // -+ BufferPtr = BufferPtr + FPLength + SYS_TABLE_PAD (FPLength); -+ MpsTableNew = (EFI_LEGACY_MP_TABLE_HEADER *)(UINTN)BufferPtr; -+ CopyMem (MpsTableNew, MpsTableOri, MpsTableOri->BaseTableLength + MpsTableOri->ExtendedTableLength); -+ -+ if ((MpsTableOri->OemTableSize != 0x0000) && (MpsTableOri->OemTablePointer != 0x0000)){ -+ BufferPtr += MpsTableOri->BaseTableLength + MpsTableOri->ExtendedTableLength; -+ BufferPtr += SYS_TABLE_PAD (BufferPtr); -+ OemTableNew = (VOID *)(UINTN)BufferPtr; -+ OemTableOri = (VOID *)(UINTN)MpsTableOri->OemTablePointer; -+ CopyMem (OemTableNew, OemTableOri, MpsTableOri->OemTableSize); -+ MpsTableNew->OemTablePointer = (UINT32)(UINTN)OemTableNew; -+ } -+ MpsTableNew->Checksum = 0; -+ MpsTableNew->Checksum = CalculateCheckSum8 ((UINT8*)MpsTableNew, MpsTableOri->BaseTableLength); -+ MpsFloatingPointerNew->PhysicalAddress = (UINT32)(UINTN)MpsTableNew; -+ MpsFloatingPointerNew->Checksum = 0; -+ MpsFloatingPointerNew->Checksum = CalculateCheckSum8 ((UINT8*)MpsFloatingPointerNew, FPLength); -+ } -+ // -+ // Change the pointer -+ // -+ *Table = MpsFloatingPointerNew; -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Lock the ConsoleIn device in system table. All key -+ presses will be ignored until the Password is typed in. The only way to -+ disable the password is to type it in to a ConIn device. -+ -+ @param Password Password used to lock ConIn device. -+ -+ @retval EFI_SUCCESS lock the Console In Spliter virtual handle successfully. -+ @retval EFI_UNSUPPORTED Password not found -+ -+**/ -+EFI_STATUS -+EFIAPI -+LockKeyboards ( -+ IN CHAR16 *Password -+ ) -+{ -+ return EFI_UNSUPPORTED; -+} -+ -+/** -+ This function locks platform flash that is not allowed to be updated during normal boot path. -+ The flash layout is platform specific. -+ -+ **/ -+VOID -+EFIAPI -+PlatformBdsLockNonUpdatableFlash ( -+ VOID -+ ) -+{ -+ return; -+} -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h -new file mode 100644 -index 000000000000..d447f77747e3 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h -@@ -0,0 +1,288 @@ -+/*++ -+ -+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ BdsPlatform.h -+ -+Abstract: -+ -+ Head file for BDS Platform specific code -+ -+--*/ -+ -+#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -+#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -+ -+ -+#include <PiDxe.h> -+ -+#include <IndustryStandard/Pci.h> -+#include <IndustryStandard/Acpi.h> -+#include <IndustryStandard/SmBios.h> -+#include <IndustryStandard/LegacyBiosMpTable.h> -+ -+#include <Library/DebugLib.h> -+#include <Library/BaseMemoryLib.h> -+#include <Library/UefiBootServicesTableLib.h> -+#include <Library/MemoryAllocationLib.h> -+#include <Library/BaseLib.h> -+#include <Library/PcdLib.h> -+#include <Library/GenericBdsLib.h> -+#include <Library/PlatformBdsLib.h> -+#include <Library/HobLib.h> -+#include <Library/UefiLib.h> -+#include <Library/DxeServicesTableLib.h> -+#include <Library/DevicePathLib.h> -+ -+#include <Protocol/PciIo.h> -+ -+#include <Guid/Acpi.h> -+#include <Guid/SmBios.h> -+#include <Guid/Mps.h> -+#include <Guid/HobList.h> -+#include <Guid/PciExpressBaseAddress.h> -+#include <Guid/GlobalVariable.h> -+#include <Guid/LdrMemoryDescriptor.h> -+ -+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[]; -+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[]; -+extern ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode; -+extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode; -+extern UART_DEVICE_PATH gUartDeviceNode; -+extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode; -+// -+// -+// -+#define VarConsoleInpDev L"ConInDev" -+#define VarConsoleInp L"ConIn" -+#define VarConsoleOutDev L"ConOutDev" -+#define VarConsoleOut L"ConOut" -+#define VarErrorOutDev L"ErrOutDev" -+#define VarErrorOut L"ErrOut" -+ -+#define PCI_DEVICE_PATH_NODE(Func, Dev) \ -+ { \ -+ { \ -+ HARDWARE_DEVICE_PATH, \ -+ HW_PCI_DP, \ -+ { \ -+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ (Func), \ -+ (Dev) \ -+ } -+ -+#define PNPID_DEVICE_PATH_NODE(PnpId) \ -+ { \ -+ { \ -+ ACPI_DEVICE_PATH, \ -+ ACPI_DP, \ -+ { \ -+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ EISA_PNP_ID((PnpId)), \ -+ 0 \ -+ } -+ -+#define gPciRootBridge \ -+ PNPID_DEVICE_PATH_NODE(0x0A03) -+ -+#define gPciIsaBridge \ -+ PCI_DEVICE_PATH_NODE(0, 0x1f) -+ -+#define gP2PBridge \ -+ PCI_DEVICE_PATH_NODE(0, 0x1e) -+ -+#define gPnpPs2Keyboard \ -+ PNPID_DEVICE_PATH_NODE(0x0303) -+ -+#define gPnp16550ComPort \ -+ PNPID_DEVICE_PATH_NODE(0x0501) -+ -+#define gUart \ -+ { \ -+ { \ -+ MESSAGING_DEVICE_PATH, \ -+ MSG_UART_DP, \ -+ { \ -+ (UINT8) (sizeof (UART_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ 0, \ -+ 115200, \ -+ 8, \ -+ 1, \ -+ 1 \ -+ } -+ -+#define gPcAnsiTerminal \ -+ { \ -+ { \ -+ MESSAGING_DEVICE_PATH, \ -+ MSG_VENDOR_DP, \ -+ { \ -+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \ -+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \ -+ } \ -+ }, \ -+ DEVICE_PATH_MESSAGING_PC_ANSI \ -+ } -+ -+#define gEndEntire \ -+ { \ -+ END_DEVICE_PATH_TYPE, \ -+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \ -+ { \ -+ END_DEVICE_PATH_LENGTH, \ -+ 0 \ -+ } \ -+ } -+ -+#define PCI_CLASS_SCC 0x07 -+#define PCI_SUBCLASS_SERIAL 0x00 -+#define PCI_IF_16550 0x02 -+#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550) -+ -+#define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF -+#define SYS_TABLE_PAD(ptr) (((~ptr) +1) & 0x07 ) -+// -+// Platform Root Bridge -+// -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH IsaBridge; -+ ACPI_HID_DEVICE_PATH Keyboard; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_ISA_KEYBOARD_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH IsaBridge; -+ ACPI_HID_DEVICE_PATH IsaSerial; -+ UART_DEVICE_PATH Uart; -+ VENDOR_DEVICE_PATH TerminalType; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_ISA_SERIAL_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH VgaDevice; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_PCI_VGA_DEVICE_PATH; -+ -+typedef struct { -+ ACPI_HID_DEVICE_PATH PciRootBridge; -+ PCI_DEVICE_PATH PciBridge; -+ PCI_DEVICE_PATH SerialDevice; -+ UART_DEVICE_PATH Uart; -+ VENDOR_DEVICE_PATH TerminalType; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} PLATFORM_DUMMY_PCI_SERIAL_DEVICE_PATH; -+ -+// -+// the short form device path for Usb keyboard -+// -+#define CLASS_HID 3 -+#define SUBCLASS_BOOT 1 -+#define PROTOCOL_KEYBOARD 1 -+ -+typedef struct { -+ USB_CLASS_DEVICE_PATH UsbClass; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} USB_CLASS_FORMAT_DEVICE_PATH; -+ -+extern PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0; -+ -+// -+// Platform BDS Functions -+// -+VOID -+PlatformBdsGetDriverOption ( -+ IN LIST_ENTRY *BdsDriverLists -+ ); -+ -+EFI_STATUS -+BdsMemoryTest ( -+ EXTENDMEM_COVERAGE_LEVEL Level -+ ); -+ -+EFI_STATUS -+PlatformBdsShowProgress ( -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground, -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground, -+ CHAR16 *Title, -+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor, -+ UINTN Progress, -+ UINTN PreviousValue -+ ); -+ -+VOID -+PlatformBdsConnectSequence ( -+ VOID -+ ); -+ -+EFI_STATUS -+ProcessCapsules ( -+ EFI_BOOT_MODE BootMode -+ ); -+ -+EFI_STATUS -+PlatformBdsConnectConsole ( -+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole -+ ); -+ -+EFI_STATUS -+PlatformBdsNoConsoleAction ( -+ VOID -+ ); -+ -+EFI_STATUS -+ConvertMpsTable ( -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertSmbiosTable ( -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertAcpiTable ( -+ IN UINTN TableLen, -+ IN OUT VOID **Table -+ ); -+ -+EFI_STATUS -+ConvertSystemTable ( -+ IN EFI_GUID *TableGuid, -+ IN OUT VOID **Table -+ ); -+ -+VOID -+PlatformBdsEnterFrontPage ( -+ IN UINT16 TimeoutDefault, -+ IN BOOLEAN ConnectAllHappened -+ ); -+ -+#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -new file mode 100644 -index 000000000000..578c74afae22 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -@@ -0,0 +1,65 @@ -+## @file -+# -+# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved. -+# This program and the accompanying materials -+# are licensed and made available under the terms and conditions of the BSD License -+# which accompanies this distribution. The full text of the license may be found at -+# http://opensource.org/licenses/bsd-license.php -+# -+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+# -+# Module Name: -+# -+# PlatformBds.inf -+# -+# Abstract: -+# -+# Component description file for Bds module. -+# -+## -+ -+[Defines] -+ INF_VERSION = 0x00010005 -+ BASE_NAME = CorebootBds -+ FILE_GUID = A6F691AC-31C8-4444-854C-E2C1A6950F92 -+ MODULE_TYPE = DXE_DRIVER -+ VERSION_STRING = 1.0 -+ LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER -+ -+[Sources] -+ BdsPlatform.c -+ PlatformData.c -+ BdsPlatform.h -+ -+[Packages] -+ MdePkg/MdePkg.dec -+ MdeModulePkg/MdeModulePkg.dec -+ CorebootModulePkg/CorebootModulePkg.dec -+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec -+ -+[LibraryClasses] -+ BaseLib -+ MemoryAllocationLib -+ UefiBootServicesTableLib -+ BaseMemoryLib -+ DebugLib -+ PcdLib -+ GenericBdsLib -+ HobLib -+ UefiLib -+ DevicePathLib -+ -+[Guids] -+ gEfiGlobalVariableGuid -+ gEfiPciExpressBaseAddressGuid -+ gEfiAcpi20TableGuid -+ gEfiMpsTableGuid -+ gEfiSmbiosTableGuid -+ gEfiAcpiTableGuid -+ gLdrMemoryDescriptorGuid -+ -+[Pcd] -+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut -+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile -+ -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c -new file mode 100644 -index 000000000000..fbdcc7de8166 ---- /dev/null -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c -@@ -0,0 +1,161 @@ -+/*++ -+ -+Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved. -+This program and the accompanying materials -+are licensed and made available under the terms and conditions of the BSD License -+which accompanies this distribution. The full text of the license may be found at -+http://opensource.org/licenses/bsd-license.php -+ -+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -+ -+Module Name: -+ -+ PlatformData.c -+ -+Abstract: -+ -+ Defined the platform specific device path which will be used by -+ platform Bbd to perform the platform policy connect. -+ -+--*/ -+ -+#include "BdsPlatform.h" -+ -+// -+// Predefined platform default time out value -+// -+UINT16 gPlatformBootTimeOutDefault = 3; -+ -+ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode = gPnpPs2Keyboard; -+ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort; -+UART_DEVICE_PATH gUartDeviceNode = gUart; -+VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal; -+ -+// -+// Predefined platform root bridge -+// -+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = { -+ gPciRootBridge, -+ gEndEntire -+}; -+ -+EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = { -+ (EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0, -+ NULL -+}; -+ -+USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = { -+ { -+ { -+ MESSAGING_DEVICE_PATH, -+ MSG_USB_CLASS_DP, -+ { -+ (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), -+ (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) -+ } -+ }, -+ 0xffff, // VendorId -+ 0xffff, // ProductId -+ CLASS_HID, // DeviceClass -+ SUBCLASS_BOOT, // DeviceSubClass -+ PROTOCOL_KEYBOARD // DeviceProtocol -+ }, -+ -+ { -+ END_DEVICE_PATH_TYPE, -+ END_ENTIRE_DEVICE_PATH_SUBTYPE, -+ { -+ END_DEVICE_PATH_LENGTH, -+ 0 -+ } -+ } -+}; -+ -+/* -+// -+// Platform specific Dummy ISA keyboard device path -+// -+PLATFORM_DUMMY_ISA_KEYBOARD_DEVICE_PATH gDummyIsaKeyboardDevicePath = { -+ gPciRootBridge, -+ gPciIsaBridge, -+ gPnpPs2Keyboard, -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy ISA serial device path -+// -+PLATFORM_DUMMY_ISA_SERIAL_DEVICE_PATH gDummyIsaSerialDevicePath = { -+ gPciRootBridge, -+ gPciIsaBridge, -+ gPnp16550ComPort, -+ gUart, -+ gPcAnsiTerminal, -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy PCI VGA device path -+// -+PLATFORM_DUMMY_PCI_VGA_DEVICE_PATH gDummyPciVgaDevicePath = { -+ gPciRootBridge, -+ PCI_DEVICE_PATH_NODE(0, 0x2), -+ gEndEntire -+}; -+ -+// -+// Platform specific Dummy PCI serial device path -+// -+PLATFORM_DUMMY_PCI_SERIAL_DEVICE_PATH gDummyPciSerialDevicePath = { -+ gPciRootBridge, -+ gP2PBridge, -+ PCI_DEVICE_PATH_NODE(0, 0x0), -+ gUart, -+ gPcAnsiTerminal, -+ gEndEntire -+}; -+*/ -+// -+// Predefined platform default console device path -+// -+BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = { -+ // -+ // need update dynamically -+ // -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyIsaSerialDevicePath, -+// (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyIsaKeyboardDevicePath, -+// (CONSOLE_IN | STD_ERROR) -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyPciVgaDevicePath, -+// CONSOLE_OUT -+// }, -+// { -+// (EFI_DEVICE_PATH_PROTOCOL *) &gDummyPciSerialDevicePath, -+// (CONSOLE_OUT | CONSOLE_IN | STD_ERROR) -+// }, -+ { -+ (EFI_DEVICE_PATH_PROTOCOL*) &gUsbClassKeyboardDevicePath, -+ CONSOLE_IN -+ }, -+ { -+ NULL, -+ 0 -+ } -+}; -+ -+// -+// Predefined platform specific driver option -+// -+EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[] = { NULL }; -+ -+// -+// Predefined platform connect sequence -+// -+EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = { NULL }; -+ -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index d71b3ec55690..22987093da58 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -95,8 +95,9 @@ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntime - - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF UefiCpuPkg/CpuDxe/CpuDxe.inf --INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf --INF MdeModulePkg/Application/UiApp/UiApp.inf -+ -+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf -+ - !if $(USE_HPET_TIMER) == TRUE - INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index 0f4e475187ee..053f380a8608 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -165,6 +165,7 @@ - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf -+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf -@@ -183,7 +184,7 @@ - ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf -- PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf -+ PlatformBdsLib|CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf - CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf - -@@ -396,13 +397,12 @@ - # - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - UefiCpuPkg/CpuDxe/CpuDxe.inf -- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf -- MdeModulePkg/Application/UiApp/UiApp.inf { -+ -+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf { - <LibraryClasses> -- NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf -+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } -+ - !if $(USE_HPET_TIMER) == TRUE - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index 97bb0a8ae0a1..bb328349b44a 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -165,6 +165,7 @@ - UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf - UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf - OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf -+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf - UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf -@@ -183,7 +184,7 @@ - ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf - PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf -- PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf -+ PlatformBdsLib|CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf - IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf - CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf - -@@ -397,13 +398,12 @@ - # - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - UefiCpuPkg/CpuDxe/CpuDxe.inf -- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf -- MdeModulePkg/Application/UiApp/UiApp.inf { -+ -+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf { - <LibraryClasses> -- NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf -- NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf -+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } -+ - !if $(USE_HPET_TIMER) == TRUE - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - !else --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch b/payloads/external/tianocore/patches/03_Library_EndofDXE.patch deleted file mode 100644 index cca3eea..0000000 --- a/payloads/external/tianocore/patches/03_Library_EndofDXE.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 1e9c5c97a55f3ad3c0d6d5dde380b4d73bd15860 Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 12:07:30 -0800 -Subject: [PATCH] CorebootBdsLib: Call End of DXE event to allow booting 3rd - party efi binaries. - ---- - .../Library/CorebootBdsLib/BdsPlatform.c | 42 +++++++++++++++++++ - .../Library/CorebootBdsLib/PlatformBds.inf | 1 + - 2 files changed, 43 insertions(+) - -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -index b6253a17f8ea..cf3e5320cbe8 100644 ---- a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c -@@ -1129,6 +1129,46 @@ Returns: - Status = BaseMemoryTest (MemoryTestLevel); - } - -+VOID -+EFIAPI -+InternalBdsEmptyCallbackFuntion ( -+ IN EFI_EVENT Event, -+ IN VOID *Context -+ ) -+{ -+ return; -+} -+ -+VOID -+InstallReadyToLock ( -+ VOID -+ ) -+{ -+ EFI_STATUS Status; -+ EFI_EVENT EndOfDxeEvent; -+ -+ DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n")); -+ // -+ // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter -+ // Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth -+ // -+ Status = gBS->CreateEventEx ( -+ EVT_NOTIFY_SIGNAL, -+ TPL_CALLBACK, -+ InternalBdsEmptyCallbackFuntion, -+ NULL, -+ &gEfiEndOfDxeEventGroupGuid, -+ &EndOfDxeEvent -+ ); -+ ASSERT_EFI_ERROR (Status); -+ gBS->SignalEvent (EndOfDxeEvent); -+ gBS->CloseEvent (EndOfDxeEvent); -+ DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n")); -+ -+ DEBUG((DEBUG_INFO,"InstallReadyToLock end\n")); -+ return; -+} -+ - VOID - EFIAPI - PlatformBdsPolicyBehavior ( -@@ -1164,6 +1204,8 @@ Returns: - EFI_INPUT_KEY Key; - EFI_BOOT_MODE BootMode; - -+ InstallReadyToLock(); -+ - // - // Init the time out value - // -diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -index 578c74afae22..992bd846bdc4 100644 ---- a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf -@@ -58,6 +58,7 @@ - gEfiSmbiosTableGuid - gEfiAcpiTableGuid - gLdrMemoryDescriptorGuid -+ gEfiEndOfDxeEventGroupGuid - - [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch b/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch deleted file mode 100644 index 2b7da9d..0000000 --- a/payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch +++ /dev/null @@ -1,56 +0,0 @@ -From e8d6ed35c15b92497cd3ede6cd35523b0e7366ac Mon Sep 17 00:00:00 2001 -From: CoolStar <coolstarorganization(a)gmail.com> -Date: Sun, 4 Dec 2016 11:50:00 -0800 -Subject: [PATCH] CorebootPayloadPkg: Add PS/2 keyboard drivers. - ---- - CorebootPayloadPkg/CorebootPayloadPkg.fdf | 3 +++ - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 3 +++ - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +++ - 3 files changed, 9 insertions(+) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -index 22987093da58..0961e96c250d 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf -+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf -@@ -132,6 +132,9 @@ INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - # ISA Support - # - INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index 053f380a8608..6ddd64faf7a5 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -492,6 +492,9 @@ - # ISA Support - # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index bb328349b44a..19c203e6cbb6 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -493,6 +493,9 @@ - # ISA Support - # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf -+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf -+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf -+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf - - # - # Console Support --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch b/payloads/external/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch deleted file mode 100644 index a581a8c..0000000 --- a/payloads/external/tianocore/patches/05_CorebootPayloadPkg-don-t-use-serial-output-for-Release-build.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 147174ea833e14ef68a8c5f1366cfbd1468dd1c8 Mon Sep 17 00:00:00 2001 -From: Wonkyu Kim <wonkyu.kim(a)intel.com> -Date: Wed, 10 Oct 2018 10:59:51 -0700 -Subject: [PATCH] CorebootPayloadPkg: don't use serial output for Release build - -Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> ---- - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 4 ++++ - CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -index 6ddd64faf7a5..2e7055815add 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -@@ -261,7 +261,11 @@ - # - ################################################################################ - [PcdsFeatureFlag] -+!if $(TARGET) == DEBUG - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -+!else -+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -+!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE -diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -index 19c203e6cbb6..b00b7b0e1134 100644 ---- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -@@ -261,7 +261,11 @@ - # - ################################################################################ - [PcdsFeatureFlag] -+!if $(TARGET) == DEBUG - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -+!else -+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -+!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE --- -2.17.1 - diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch deleted file mode 100644 index 10024d8..0000000 --- a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 9c28ac87eb2df7319d4f5a48124c837b8bf123b3 Mon Sep 17 00:00:00 2001 -From: ReddestDream <reddestdream(a)gmail.com> -Date: Wed, 3 May 2017 00:13:28 -0400 -Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being - overwritten - -Exclude the bottom 4kb from being included in System Memory HoB ---- - CorebootModulePkg/CbSupportPei/CbSupportPei.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -index 831de89b21d1..e84b9b55288a 100755 ---- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c -+++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -@@ -261,8 +261,9 @@ CbPeiEntryPoint ( - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ), -- (EFI_PHYSICAL_ADDRESS)(0), -- (UINT64)(0xA0000) -+ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides -+ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000), -+ (UINT64)(0xA0000 - 0x1000) - ); - - --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch b/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch deleted file mode 100644 index 9b2569a..0000000 --- a/payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 2e75f9ad6ef625575185dfc262c6803a89850dd5 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur(a)aheymans.xyz> -Date: Wed, 24 Jan 2018 10:07:08 +0100 -Subject: [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine - -Fetch BytesPerScanLine from coreboot table to reflect how the actual -framebuffer is set up instead of guessing it from the horizontal -resolution. - -This fixes a garbled display when HorizontalResolution * (BitsPerPixel -/ 8) and pFbInfo->BytesPerScanLine don't match. - -Contributed-under: TianoCore Contribution Agreement 1.1 -Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> ---- - CorebootPayloadPkg/FbGop/FbGop.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c -index 37d6def7f780..679061703358 100644 ---- a/CorebootPayloadPkg/FbGop/FbGop.c -+++ b/CorebootPayloadPkg/FbGop/FbGop.c -@@ -822,7 +822,7 @@ FbGopCheckForVbe ( - BitsPerPixel = pFbInfo->BitsPerPixel; - HorizontalResolution = pFbInfo->HorizontalResolution; - VerticalResolution = pFbInfo->VerticalResolution; -- BytesPerScanLine = HorizontalResolution * (BitsPerPixel / 8); -+ BytesPerScanLine = pFbInfo->BytesPerScanLine; - - ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool ( - ModeNumber * sizeof (FB_VIDEO_MODE_DATA) --- -2.17.0 - diff --git a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch b/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch deleted file mode 100644 index 4881fff..0000000 --- a/payloads/external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 8cb365e9ec90420e3d04b77f6e7999a65d5983a6 Mon Sep 17 00:00:00 2001 -From: Patrick Rudolph <siro(a)das-labor.org> -Date: Sun, 17 Jun 2018 08:44:51 +0200 -Subject: [PATCH] BaseTools: Fix building with -Werror=stringop-truncation - -Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> ---- - BaseTools/Source/C/GenVtf/GenVtf.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/BaseTools/Source/C/GenVtf/GenVtf.c b/BaseTools/Source/C/GenVtf/GenVtf.c -index 65ae08eeceb8..d4200621457c 100644 ---- a/BaseTools/Source/C/GenVtf/GenVtf.c -+++ b/BaseTools/Source/C/GenVtf/GenVtf.c -@@ -129,9 +129,9 @@ Returns: - } else { - Length = strlen(Str); - if (Length < 4) { -- strncpy (TemStr + 4 - Length, Str, Length); -+ memcpy (TemStr + 4 - Length, Str, Length); - } else { -- strncpy (TemStr, Str + Length - 4, 4); -+ memcpy (TemStr, Str + Length - 4, 4); - } - - sscanf ( -@@ -1521,7 +1521,7 @@ Returns: - // - FitStartPtr = (FIT_TABLE *) RelativeAddress; - -- strncpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " -+ memcpy ((CHAR8 *) &FitStartPtr->CompAddress, FIT_SIGNATURE, 8); // "_FIT_ " - assert (((VtfInfo->CompSize & 0x00FFFFFF) % 16) == 0); - FitStartPtr->CompSize = (VtfInfo->CompSize & 0x00FFFFFF) / 16; - FitStartPtr->CompVersion = MAKE_VERSION (VtfInfo->MajorVer, VtfInfo->MinorVer); --- -2.17.0 - -- To view, visit https://review.coreboot.org/c/coreboot/+/31543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88 Gerrit-Change-Number: 31543 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: util/amdfwtool: Add script to verify signature of PSP firmware file
by Kyösti Mälkki (Code Review) 26 Feb '19

26 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17363 ) Change subject: util/amdfwtool: Add script to verify signature of PSP firmware file ...................................................................... Patch Set 2: Martin, Marshall; please convince someone at AMD to push the file format header to our repositories, if you want me to evaluate the individual fields. The only doc I have on this NDA. -- To view, visit https://review.coreboot.org/c/coreboot/+/17363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3610235a6ca7989f2e3594ca036b6afce70f5fb0 Gerrit-Change-Number: 17363 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Feb 2019 09:24:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: util/amdfwtool: Add script to verify signature of PSP firmware file
by Kyösti Mälkki (Code Review) 26 Feb '19

26 Feb '19

Kyösti Mälkki has removed Zheng Bao from this change. ( https://review.coreboot.org/c/coreboot/+/17363 ) Change subject: util/amdfwtool: Add script to verify signature of PSP firmware file ...................................................................... Removed reviewer Zheng Bao. -- To view, visit https://review.coreboot.org/c/coreboot/+/17363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3610235a6ca7989f2e3594ca036b6afce70f5fb0 Gerrit-Change-Number: 17363 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: deleteReviewer

1 0

Change in ...coreboot[master]: mainboard/intel/saddlebrook: add support for Saddle Brook
by Kyösti Mälkki (Code Review) 26 Feb '19

26 Feb '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21436 ) Change subject: mainboard/intel/saddlebrook: add support for Saddle Brook ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/21436/9/src/mainboard/intel/saddlebrook/rom… File src/mainboard/intel/saddlebrook/romstage.c: https://review.coreboot.org/#/c/21436/9/src/mainboard/intel/saddlebrook/rom… PS9, Line 62: memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2]; I believe this should have changed to spd_array[1] after blk.add_map was modified after patchset 7. I would asssume 2nd DIMM slot to currently not work. -- To view, visit https://review.coreboot.org/c/coreboot/+/21436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Gerrit-Change-Number: 21436 Gerrit-PatchSet: 9 Gerrit-Owner: Anuj Mittal <anujx.mittal(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anuj Mittal <anujx.mittal(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Feb 2019 08:25:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/common: Include cometlake PCH IDs
by Subrata Banik (Code Review) 26 Feb '19

26 Feb '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31234 ) Change subject: soc/intel/common: Include cometlake PCH IDs ...................................................................... soc/intel/common: Include cometlake PCH IDs Add cometlake specific PCH IDs Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31234 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 17 files changed, 100 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 81654bc..3046031 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2720,6 +2720,11 @@ #define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 #define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 #define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 +#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 +#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 +#define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 +#define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2839,6 +2844,23 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23 0xa32e #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24 0xa32f +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1 0x02b8 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2 0x02b9 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3 0x02ba +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4 0x02bb +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5 0x02bc +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6 0x02bd +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7 0x02be +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8 0x02bf +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9 0x02b0 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10 0x02b1 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11 0x02b2 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12 0x02b3 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13 0x02b4 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6 +#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7 + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 @@ -2847,10 +2869,13 @@ #define PCI_DEVICE_ID_INTEL_GLK_SATA 0x31e3 #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5 #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7 -#define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA 0x282a #define PCI_DEVICE_ID_INTEL_CNP_H_SATA 0xa352 #define PCI_DEVICE_ID_INTEL_CNP_LP_SATA 0x9dd3 #define PCI_DEVICE_ID_INTEL_ICP_U_SATA 0x34d3 +#define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 +#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 +#define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2861,6 +2886,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1 #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 +#define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -2905,6 +2931,12 @@ #define PCI_DEVICE_ID_INTEL_ICP_I2C3 0x34eb #define PCI_DEVICE_ID_INTEL_ICP_I2C4 0x34c5 #define PCI_DEVICE_ID_INTEL_ICP_I2C5 0x34c6 +#define PCI_DEVICE_ID_INTEL_CMP_I2C0 0x02e8 +#define PCI_DEVICE_ID_INTEL_CMP_I2C1 0x02e9 +#define PCI_DEVICE_ID_INTEL_CMP_I2C2 0x02ea +#define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb +#define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 +#define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -2933,6 +2965,9 @@ #define PCI_DEVICE_ID_INTEL_ICP_UART0 0x34a8 #define PCI_DEVICE_ID_INTEL_ICP_UART1 0x34a9 #define PCI_DEVICE_ID_INTEL_ICP_UART2 0x34c7 +#define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 +#define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 +#define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -2953,6 +2988,10 @@ #define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab #define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb #define PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI 0x34a4 +#define PCI_DEVICE_ID_INTEL_CMP_SPI0 0x02aa +#define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab +#define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb +#define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3060,6 +3099,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3 #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 +#define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3070,6 +3110,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed +#define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3077,6 +3118,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0 #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 +#define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3084,6 +3126,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef +#define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3094,6 +3137,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71 #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 +#define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3102,6 +3146,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 +#define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3110,6 +3155,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee +#define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca @@ -3118,6 +3164,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5 #define PCI_DEVICE_ID_INTEL_CNP_H_SD 0xa375 #define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8 +#define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5 /* Intel EMMC device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index faa4924..1c239ab 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -75,6 +75,11 @@ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, + { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, + { PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" }, + { PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" }, }; static struct { diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9c35342..1d48b82 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -520,6 +520,7 @@ PCI_DEVICE_ID_INTEL_SKL_CSE0, PCI_DEVICE_ID_INTEL_CNP_H_CSE0, PCI_DEVICE_ID_INTEL_ICL_CSE0, + PCI_DEVICE_ID_INTEL_CMP_CSE0, 0, }; diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 4de3137..da0ad53 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -78,6 +78,7 @@ PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, PCI_DEVICE_ID_INTEL_ICL_AUDIO, + PCI_DEVICE_ID_INTEL_CMP_AUDIO, 0 }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index b7f240e..70a4406 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -223,6 +223,12 @@ PCI_DEVICE_ID_INTEL_ICP_I2C3, PCI_DEVICE_ID_INTEL_ICP_I2C4, PCI_DEVICE_ID_INTEL_ICP_I2C5, + PCI_DEVICE_ID_INTEL_CMP_I2C0, + PCI_DEVICE_ID_INTEL_CMP_I2C1, + PCI_DEVICE_ID_INTEL_CMP_I2C2, + PCI_DEVICE_ID_INTEL_CMP_I2C3, + PCI_DEVICE_ID_INTEL_CMP_I2C4, + PCI_DEVICE_ID_INTEL_CMP_I2C5, 0, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ad004ef..1a38a6c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,6 +156,11 @@ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, + PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, + PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index f9930c1..24f3a69 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -167,6 +167,7 @@ PCI_DEVICE_ID_INTEL_CNL_P2SB, PCI_DEVICE_ID_INTEL_CNP_H_P2SB, PCI_DEVICE_ID_INTEL_ICL_P2SB, + PCI_DEVICE_ID_INTEL_CMP_P2SB, 0, }; diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 3ebb4f6..c191ad0 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -206,6 +206,22 @@ PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 9f1b94f..7f6d249 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -128,6 +128,7 @@ PCI_DEVICE_ID_INTEL_GLK_PMC, PCI_DEVICE_ID_INTEL_CNP_H_PMC, PCI_DEVICE_ID_INTEL_ICP_PMC, + PCI_DEVICE_ID_INTEL_CMP_PMC, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 936fc9b..a39ef52 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -75,10 +75,13 @@ PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, PCI_DEVICE_ID_INTEL_CNL_SATA, PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, - PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, PCI_DEVICE_ID_INTEL_CNP_H_SATA, PCI_DEVICE_ID_INTEL_CNP_LP_SATA, PCI_DEVICE_ID_INTEL_ICP_U_SATA, + PCI_DEVICE_ID_INTEL_CMP_SATA, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CMP_LP_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index c8dc7d1..ea8d1b0 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -72,6 +72,7 @@ PCI_DEVICE_ID_INTEL_SKL_SD, PCI_DEVICE_ID_INTEL_CNP_H_SD, PCI_DEVICE_ID_INTEL_ICL_SD, + PCI_DEVICE_ID_INTEL_CMP_SD, 0 }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 2287138..31bcc97 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -93,6 +93,7 @@ PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_KBP_H_SMBUS, PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, + PCI_DEVICE_ID_INTEL_CMP_SMBUS, 0 }; diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 69449e7..c02cfed 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -71,6 +71,10 @@ PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, PCI_DEVICE_ID_INTEL_ICP_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CMP_SPI0, + PCI_DEVICE_ID_INTEL_CMP_SPI1, + PCI_DEVICE_ID_INTEL_CMP_SPI2, + PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI, 0 }; diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 507ff58..720b736 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -50,6 +50,7 @@ PCI_DEVICE_ID_INTEL_APL_SRAM, PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, + PCI_DEVICE_ID_INTEL_CMP_SRAM, 0, }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 57d9ebe..7f105d7 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -268,6 +268,9 @@ PCI_DEVICE_ID_INTEL_ICP_UART0, PCI_DEVICE_ID_INTEL_ICP_UART1, PCI_DEVICE_ID_INTEL_ICP_UART2, + PCI_DEVICE_ID_INTEL_CMP_UART0, + PCI_DEVICE_ID_INTEL_CMP_UART1, + PCI_DEVICE_ID_INTEL_CMP_UART2, 0, }; diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 0ee6365..9eb6e1d 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -43,6 +43,7 @@ PCI_DEVICE_ID_INTEL_SPT_LP_XDCI, PCI_DEVICE_ID_INTEL_CNP_H_XDCI, PCI_DEVICE_ID_INTEL_ICP_LP_XDCI, + PCI_DEVICE_ID_INTEL_CMP_LP_XDCI, 0 }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index ab87f36..95360ce 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -44,6 +44,7 @@ PCI_DEVICE_ID_INTEL_KBP_H_XHCI, PCI_DEVICE_ID_INTEL_CNP_H_XHCI, PCI_DEVICE_ID_INTEL_ICP_LP_XHCI, + PCI_DEVICE_ID_INTEL_CMP_LP_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Gerrit-Change-Number: 31234 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status handling ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/31585/2/src/ec/google/chromeec/ec.c File src/ec/google/chromeec/ec.c: https://review.coreboot.org/#/c/31585/2/src/ec/google/chromeec/ec.c@598 PS2, Line 598: != > If we're defining negative integers as error code (as written in the CL description), 'rv < 0' is pr […] Updated in the new patchsets. -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Feb 2019 01:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

Hello Aaron Durbin, Daisuke Nojiri, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31585 to look at the new patch set (#5). Change subject: ec/google/chromeec: fix the error status handling ...................................................................... ec/google/chromeec: fix the error status handling Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error, which causes confusion for the caller. This patch attempts to address the issue by using only negative number for errors. In addition, the patch modifies the direct/indirect callers of google_chromeec_command() such so they will treat negative number as error. BUG=b:123676982,chromium:935038 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/mainboard/google/gru/mainboard.c M src/security/vboot/vboot_logic.c 9 files changed, 30 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31585/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by build bot (Jenkins) (Code Review) 26 Feb '19

26 Feb '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31585 ) Change subject: ec/google/chromeec: fix the error status handling ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/31585/4/src/mainboard/google/gru/mainboard.c File src/mainboard/google/gru/mainboard.c: https://review.coreboot.org/#/c/31585/4/src/mainboard/google/gru/mainboard.… PS4, Line 260: if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK) < 0) line over 80 characters https://review.coreboot.org/#/c/31585/4/src/mainboard/google/gru/mainboard.… PS4, Line 265: if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON) < 0) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Feb 2019 01:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

Hello Daisuke Nojiri, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31585 to look at the new patch set (#4). Change subject: ec/google/chromeec: fix the error status handling ...................................................................... ec/google/chromeec: fix the error status handling Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error, which causes confusion for the caller. This patch attempts to address the issue by using only negative number for errors. In addition, the patch modifies the callers of google_chromeec_command() (direct or indirect callers) such so they will treat negative number as error. BUG=b:123676982,chromium:935038 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/mainboard/google/gru/mainboard.c M src/security/vboot/vboot_logic.c 9 files changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31585/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 4 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: ec/google/chromeec: fix the error status handling
by YH Lin (Code Review) 26 Feb '19

26 Feb '19

Hello Daisuke Nojiri, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31585 to look at the new patch set (#3). Change subject: ec/google/chromeec: fix the error status handling ...................................................................... ec/google/chromeec: fix the error status handling Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error, which causes confusion for the caller. This patch attempts to address the issue by using only negative number for errors. In addition, the patch modifies the callers of google_chromeec_command() such so they will check negative number as error. BUG=b:123676982,chromium:935038 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/vstore.c 5 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31585/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Gerrit-Change-Number: 31585 Gerrit-PatchSet: 3 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2019