coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: Revert "mb/google/poppy/variants/atlas: Update DPTF parameters"
by Puthikorn Voravootivat (Code Review) 04 Mar '19

04 Mar '19

Hello Aaron Durbin, Todd Broch, Sumeet R Pawnikar, build bot (Jenkins), Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31655 to review the following change. Change subject: Revert "mb/google/poppy/variants/atlas: Update DPTF parameters" ...................................................................... Revert "mb/google/poppy/variants/atlas: Update DPTF parameters" This reverts commit 5e90ef8c356099e42612bc97976c67092d0810ff. Reason for revert: The 1s internal causes early throttle in usage spike. (log in b/123895423#comment3) BUG=b:113101335 BRANCH=None TEST=learning from Nocturne Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176 --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31655/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 85eb891..685f4dd 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -50,7 +50,7 @@ Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, /* CPU Throttle Effect on TSR0 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176 Gerrit-Change-Number: 31655 Gerrit-PatchSet: 1 Gerrit-Owner: Puthikorn Voravootivat <puthik(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: sb/intel/common: Fix SMBUs block commands
by Kyösti Mälkki (Code Review) 04 Mar '19

04 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31622 Change subject: sb/intel/common: Fix SMBUs block commands ...................................................................... sb/intel/common: Fix SMBUs block commands Fix regression after commit c38d543 sb/intel/common: SMBus complete_command() When evaluating HSTSTS register, BYTE_DONE bit must be excluded from transaction completion and error criteria. Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31622/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index a842a61..9ae01ad 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -74,7 +74,10 @@ { if (status & SMBHSTSTS_HOST_BUSY) return 0; - status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); + + /* These status bits do not imply completion of transaction. */ + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | + SMBHSTSTS_SMBALERT_STS); return status != 0; } @@ -89,8 +92,9 @@ static int cb_err_from_stat(u8 status) { - /* Ignore the "In Use" status... */ - status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); + /* These status bits do not imply errors. */ + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | + SMBHSTSTS_SMBALERT_STS); if (status == SMBHSTSTS_INTR) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6 Gerrit-Change-Number: 31622 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p
by Iru Cai (vimacs) (Code Review) 04 Mar '19

04 Mar '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30936 to review the following change. Change subject: mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p ...................................................................... mainboard/hp: Add HP Elitebook 8760w as a variant of 8460p Tested: - i7-2630QM, 4G - boots Arch Linux on USB drive from SeaBIOS payload with VGA option ROM added Issues: - it takes longer time to boot, and the fan is noisier in the boot process Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8460p/Kconfig.name M src/mainboard/hp/8460p/Makefile.inc M src/mainboard/hp/8460p/romstage.c R src/mainboard/hp/8460p/variants/8460p/devicetree.cb R src/mainboard/hp/8460p/variants/8460p/gpio.c A src/mainboard/hp/8460p/variants/8460p/romstage.c A src/mainboard/hp/8460p/variants/8760w/board_info.txt A src/mainboard/hp/8460p/variants/8760w/devicetree.cb A src/mainboard/hp/8460p/variants/8760w/gpio.c A src/mainboard/hp/8460p/variants/8760w/romstage.c 11 files changed, 495 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30936/1 diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index 57e6268..5f0d827 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -13,45 +13,57 @@ # GNU General Public License for more details. # -if BOARD_HP_8460P - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_HP_BASEBOARD_8460P + def_bool n select BOARD_ROMSIZE_KB_8192 select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS + select SANDYBRIDGE_IVYBRIDGE_LVDS if !BOARD_HP_8760W select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT - select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LIBGFXINIT if !BOARD_HP_8760W select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_INTERNAL_IS_LVDS if !BOARD_HP_8760W select EC_HP_KBC1126 select SUPERIO_SMSC_LPC47N217 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT +if BOARD_HP_BASEBOARD_8460P + +config VARIANT_DIR + string + default "8460p" if BOARD_HP_8460P + default "8760w" if BOARD_HP_8760W + config MAINBOARD_DIR string default hp/8460p +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_PART_NUMBER string - default "EliteBook 8460p" + default "EliteBook 8460p" if BOARD_HP_8460P + default "EliteBook 8760w" if BOARD_HP_8760W config VGA_BIOS_FILE string - default "pci8086,0116.rom" + default "pci8086,0116.rom" if BOARD_HP_8460P + default "pci10de,0e3a.rom" if BOARD_HP_8760W config VGA_BIOS_ID string - default "8086,0116" + default "8086,0116" if BOARD_HP_8460P + default "10de,0e3a" if BOARD_HP_8760W config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex diff --git a/src/mainboard/hp/8460p/Kconfig.name b/src/mainboard/hp/8460p/Kconfig.name index 94f2fe9..8d48d43 100644 --- a/src/mainboard/hp/8460p/Kconfig.name +++ b/src/mainboard/hp/8460p/Kconfig.name @@ -1,2 +1,7 @@ config BOARD_HP_8460P bool "EliteBook 8460p" + select BOARD_HP_BASEBOARD_8460P + +config BOARD_HP_8760W + bool "EliteBook 8760w" + select BOARD_HP_BASEBOARD_8460P diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00cce..5819ac0 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c index b97d5e4..899ffab 100644 --- a/src/mainboard/hp/8460p/romstage.c +++ b/src/mainboard/hp/8460p/romstage.c @@ -42,23 +42,6 @@ { } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* USB0, eSATA */ - { 1, 0, 0 }, /* USB charger */ - { 0, 1, 1 }, - { 1, 1, 1 }, /* camera */ - { 1, 0, 2 }, /* USB4 expresscard */ - { 1, 0, 2 }, /* bluetooth */ - { 0, 0, 3 }, - { 1, 0, 3 }, /* smartcard */ - { 1, 1, 4 }, /* fingerprint */ - { 1, 1, 4 }, /* WWAN */ - { 1, 0, 5 }, /* CONN */ - { 1, 0, 5 }, /* docking */ - { 1, 0, 6 }, /* CONN */ - { 1, 0, 6 }, /* docking */ -}; - void mainboard_early_init(int s3resume) { } @@ -73,9 +56,3 @@ kbc1126_pm1_init(); kbc1126_exit_conf(); } - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/variants/8460p/devicetree.cb similarity index 100% rename from src/mainboard/hp/8460p/devicetree.cb rename to src/mainboard/hp/8460p/variants/8460p/devicetree.cb diff --git a/src/mainboard/hp/8460p/gpio.c b/src/mainboard/hp/8460p/variants/8460p/gpio.c similarity index 100% rename from src/mainboard/hp/8460p/gpio.c rename to src/mainboard/hp/8460p/variants/8460p/gpio.c diff --git a/src/mainboard/hp/8460p/variants/8460p/romstage.c b/src/mainboard/hp/8460p/variants/8460p/romstage.c new file mode 100644 index 0000000..2221046 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8460p/romstage.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0, eSATA */ + { 1, 0, 0 }, /* USB charger */ + { 0, 1, 1 }, + { 1, 1, 1 }, /* camera */ + { 1, 0, 2 }, /* USB4 expresscard */ + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, /* smartcard */ + { 1, 1, 4 }, /* fingerprint */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, /* CONN */ + { 1, 0, 5 }, /* docking */ + { 1, 0, 6 }, /* CONN */ + { 1, 0, 6 }, /* docking */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/hp/8460p/variants/8760w/board_info.txt b/src/mainboard/hp/8460p/variants/8760w/board_info.txt new file mode 100644 index 0000000..887ec7b --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/8460p/variants/8760w/devicetree.cb b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb new file mode 100644 index 0000000..7d4ba42 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/devicetree.cb @@ -0,0 +1,139 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x103c 0x1630 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x8086 0x2010 + end + device pci 02.0 off # Internal graphics + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + # HDD(0, 1), ODD(2), eSATA(4) + register "sata_port_map" = "0x3f" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x1630 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x1630 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x1630 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x1630 + end + device pci 1c.0 on # PCIe Port #1, WWAN + subsystemid 0x103c 0x1630 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x103c 0x1630 + end + device pci 1c.2 on # PCIe Port #3, SD/MMC + subsystemid 0x103c 0x1630 + end + device pci 1c.3 on # PCIe Port #4, WLAN + subsystemid 0x103c 0x1630 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller + subsystemid 0x103c 0x1630 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x1630 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x1630 + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x9a" + device pnp ff.1 off end + end # kbc1126 + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off # Com2 + end + end #chip superio/smsc/lpc47n217 + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x1630 + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/hp/8460p/variants/8760w/gpio.c b/src/mainboard/hp/8460p/variants/8760w/gpio.c new file mode 100644 index 0000000..bed7996 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/gpio.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/8460p/variants/8760w/romstage.c b/src/mainboard/hp/8460p/variants/8760w/romstage.c new file mode 100644 index 0000000..7648c12 --- /dev/null +++ b/src/mainboard/hp/8460p/variants/8760w/romstage.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB charger */ + { 1, 1, 0 }, /* CONN */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 1, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, /* fingerprint */ + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd49f5c9e17cf8f5ef8c73e73bea111188427590 Gerrit-Change-Number: 30936 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: cpu/intel/model_1067x: Implement microcode loading
by Nico Huber (Code Review) 03 Mar '19

03 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31664 Change subject: cpu/intel/model_1067x: Implement microcode loading ...................................................................... cpu/intel/model_1067x: Implement microcode loading We load it once for the BSP in advance and let the MP init handle it for the APs. The BSP load could also be done earlier, e.g. before CAR setup, to align with other platforms. TEST=Booted ThinkPad X200s and checked log: Microcode is loaded correctly on the BSP before SMM setup, and reported to be up to date on all cores after. Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31664/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index acd56c8..b8b3159 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -42,6 +42,12 @@ return cores; } +static void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = microcode_patch; + *parallel = 1; +} + /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL to enable SMRR so configure IA32_FEATURE_CONTROL early on */ static void pre_mp_smm_init(void) @@ -98,6 +104,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = pre_mp_smm_init, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, @@ -106,6 +113,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) { + microcode_patch = intel_microcode_find(); + intel_microcode_load_unlocked(microcode_patch); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c Gerrit-Change-Number: 31664 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: superio/ite/common: add option for enabling 5 FANs
by Krystian Hebel (Code Review) 02 Mar '19

02 Mar '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31616 Change subject: superio/ite/common: add option for enabling 5 FANs ...................................................................... superio/ite/common: add option for enabling 5 FANs Some ITEs have more than 3 independent FAN controller outputs. As the initial implementation assumed only 3 outputs some registers are not consequently numbered. This change adds macros for accessing those registers. Additionally some chips have SmartGuardian always enabled, without the option for turning it off. For these chips bits that were responsible for ON/OFF control are either reserved or have different meaning. Another Kconfig option was added to disable ON/OFF functionality on platforms that do not support it. Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 4 files changed, 132 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31616/1 diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 8e52cf4..a4b7ece 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -4,6 +4,7 @@ ## Copyright (C) 2009 Ronald G. Minnich ## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2019 Protectli ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -41,4 +42,13 @@ help The second FAN controller has a separate frequency setting. +config SUPERIO_ITE_ENV_CTRL_NO_ONOFF + bool + help + FAN controller always works in SmartGuardian mode + +config SUPERIO_ITE_ENV_CTRL_5FANS + bool + help + ITE FAN controller has 5 independent outputs endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1dc5bb6..29a9b94 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -191,7 +192,9 @@ { u8 reg; - if (conf->mode == FAN_IGNORE) + if (conf->mode == FAN_IGNORE || + (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF) && + conf->mode <= FAN_MODE_OFF)) return; /* FAN_CTL2 might have its own frequency setting */ @@ -213,23 +216,36 @@ ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); } - reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); - if (conf->mode >= FAN_MODE_ON) - reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); - else - reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); - if (conf->mode >= FAN_SMART_SOFTWARE) - reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan); - else - reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); - ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { + reg = ite_ec_read(base, ITE_EC_FAN_SEC_CTL); + if (conf->mode >= FAN_MODE_ON) + reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan); + else + reg &= ~ITE_EC_FAN_SEC_CTL_TAC_EN(fan); + ite_ec_write(base, ITE_EC_FAN_SEC_CTL, reg); + } else { + reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); + if (conf->mode >= FAN_MODE_ON) + reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); + else + reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); + + /* Some ITEs have SmartGuardian always enabled */ + if (!IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF)) { + if (conf->mode >= FAN_SMART_SOFTWARE) + reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan); + else + reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); + } + ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + } } static void enable_beeps(const u16 base, const struct ite_ec_config *const conf) diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 11316db..a265458 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,8 +53,26 @@ #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_SEC_CTL 0x0c +#define ITE_EC_FAN_SEC_CTL_TAC_EN(x) (1 << (x)) +#define ITE_EC_FAN_TAC_LIMIT(x) \ + ({ \ + (x > 3) \ + ? (0x84 + ((x)-4) * 2) \ + : (0x10 + ((x)-1)); \ + }) +#define ITE_EC_FAN_TAC_EXT_LIMIT(x) \ + ({ \ + (x > 3) \ + ? (0x85 + ((x)-4) * 2) \ + : (0x1b + ((x)-1)); \ + }) +#else #define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1)) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1)) +#endif #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) @@ -72,7 +91,22 @@ #define ITE_EC_FAN_PWM_CLOCK_51KHZ (7 << 4) #define ITE_EC_FAN_PWM_MIN_DUTY_20 (1 << 3) #define ITE_EC_FAN_CTL_ON(x) (1 << ((x)-1)) + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CTL_PWM_CONTROL(x) \ + ({ \ + (x > 3) \ + ? (0x1e + ((x)-4)) \ + : (0x15 + ((x)-1)); \ + }) +#define ITE_EC_FAN_CTL_TEMPIN_MASK (7 << 3) +#define ITE_EC_FAN_CTL_TEMPIN(x) ((((x)-1) & 7) << 3) +#else #define ITE_EC_FAN_CTL_PWM_CONTROL(x) (0x15 + ((x)-1)) +#define ITE_EC_FAN_CTL_TEMPIN_MASK (3 << 0) +#define ITE_EC_FAN_CTL_TEMPIN(x) (((x)-1) & 3) +#endif + #define ITE_EC_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) #define ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) #define ITE_EC_FAN_CTL_PWM_DUTY_MASK (ITE_EC_FAN_MAX_PWM << 0) @@ -83,8 +117,6 @@ ? ITE_EC_FAN_MAX_PWM \ : (_p * ITE_EC_FAN_MAX_PWM) / 100; \ }) -#define ITE_EC_FAN_CTL_TEMPIN_MASK (3 << 0) -#define ITE_EC_FAN_CTL_TEMPIN(x) (((x)-1) & 3) #define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) #define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) @@ -119,16 +151,64 @@ #define ITE_EC_BEEP_TONE_DIVISOR(x) (((x) & 0x0f) << 4) #define ITE_EC_BEEP_FREQ_DIVISOR(x) (((x) & 0x0f) << 0) +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) \ + ({ \ + (x == 5) \ + ? (0xa0) \ + : (0x60 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) \ + ({ \ + (x == 5) \ + ? (0xa1) \ + : (0x61 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) \ + ({ \ + (x == 5) \ + ? (0xa2) \ + : (0x62 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_PWM_START(x) \ + ({ \ + (x == 5) \ + ? (0xa3) \ + : (0x63 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_PWM_AUTO(x) \ + ({ \ + (x == 5) \ + ? (0xa4) \ + : (0x64 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_DELTA_TEMP(x) \ + ({ \ + (x == 5) \ + ? (0xa5) \ + : (0x65 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) + +#else + #define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_PWM_START(x) (0x63 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_PWM_AUTO(x) (0x64 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) +#endif + +/* Common for ITE_EC_FAN_CTL_PWM_START */ #define ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(s) (((s) & 0x40) << 1) #define ITE_EC_FAN_CTL_PWM_START_DUTY(p) ITE_EC_FAN_CTL_PWM_DUTY(p) -#define ITE_EC_FAN_CTL_PWM_AUTO(x) (0x64 + ((x)-1) * 8) + +/* Common for ITE_EC_FAN_CTL_PWM_AUTO */ #define ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) #define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f) -#define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) + +/* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) #define ITE_EC_EXTEMP_STATUS 0x88 diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f8f2e1e..5069b45 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +20,12 @@ #define SUPERIO_ITE_ENV_CTRL_CHIP_H #define ITE_EC_TMPIN_CNT 3 + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CNT 5 +#else #define ITE_EC_FAN_CNT 3 +#endif /* Supported thermal mode on TMPINx */ enum ite_ec_thermal_mode { @@ -105,5 +111,9 @@ #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define FAN4 ec.fan[3] +#define FAN5 ec.fan[4] +#endif #endif /* SUPERIO_ITE_ENV_CTRL_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f Gerrit-Change-Number: 31616 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

5 18

Change in ...coreboot[master]: Revert "mb/google/sarien: Update GPIOs for next build"
by Lijian Zhao (Code Review) 02 Mar '19

02 Mar '19

Hello Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30940 to review the following change. Change subject: Revert "mb/google/sarien: Update GPIOs for next build" ...................................................................... Revert "mb/google/sarien: Update GPIOs for next build" This reverts commit 025a03f6164b4f24e36aea39688b39abdec28fee. Reason for revert: <INSERT REASONING HERE> Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 27 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30940/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index a29fd06..0ffd029 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -30,23 +30,18 @@ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), - /* ISH_LID_CL#_TAB */ -/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), - /* ISH_ACC1_INT# */ -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - /* ISH_ACC2_INT# */ -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), - /* ISH_NB_MODE */ -/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - /* ISH_LID_CL#_NB */ -/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ /* CORE_VID1 */ @@ -54,17 +49,12 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ - /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), - /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -73,7 +63,7 @@ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -122,10 +112,8 @@ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), - /* ISH_CPU_UART0_RX */ -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), - /* ISH_CPU_UART0_TX */ -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ @@ -156,10 +144,10 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -191,9 +179,9 @@ /* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ /* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 38d21c8..a41d940 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -49,11 +49,11 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -63,7 +63,8 @@ /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ +/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* HDD_FALL_INT */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -100,7 +101,7 @@ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), @@ -134,7 +135,7 @@ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ @@ -142,7 +143,8 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ +/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST, + EDGE_SINGLE, INVERT), /* FFS_INT2 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), @@ -235,7 +237,7 @@ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ }; @@ -252,10 +254,7 @@ } static const struct cros_gpio cros_gpios[] = { - /* - * TODO: re-enable recovery mode when boards are updated: - * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), - */ + CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe Gerrit-Change-Number: 30940 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD
by Duncan Laurie (Code Review) 02 Mar '19

02 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31659 Change subject: mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD ...................................................................... mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD In order to prevent keyboard keys pressed at boot from causing issues in the payload remove the PS2 keyboard driver so it does not get initialized until it is needed in libpayload. BUG=b:126633269 TEST=boot on sarien while pressing keys and ensure libpayload and/or the kernel does not have any issues initializing the keyboard. Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31659/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index a976d36..ce6b810 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -5,7 +5,6 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI - select DRIVERS_PS2_KEYBOARD select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select GENERIC_SPD_BIN -- To view, visit https://review.coreboot.org/c/coreboot/+/31659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4 Gerrit-Change-Number: 31659 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: i8042: Only test PS/2 AUX port when enabled
by Duncan Laurie (Code Review) 02 Mar '19

02 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31658 Change subject: libpayload: i8042: Only test PS/2 AUX port when enabled ...................................................................... libpayload: i8042: Only test PS/2 AUX port when enabled If a PS/2 AUX device is not present then the AUX test command during i8042_probe() will time out and add ~500ms to the boot time. In order to avoid this only test the PS/2 AUX port if CONFIG_LP_PC_MOUSE is enabled. BUG=b:126633269 TEST=boot on device without AUX port and check that this command does not get executed, saving ~500ms at boot. Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M payloads/libpayload/drivers/i8042/i8042.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31658/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 69740d9..4cdd0be 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -229,8 +229,10 @@ } /* Test secondary port */ - if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0) - aux_fifo = fifo_init(4 * 32); + if (IS_ENABLED(CONFIG_LP_PC_MOUSE)) { + if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0) + aux_fifo = fifo_init(4 * 32); + } /* Test first PS/2 port */ if (i8042_cmd_with_response(I8042_CMD_KB_TEST) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/31658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa Gerrit-Change-Number: 31658 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: libpayload: keyboard: Add option to ignore failures during init
by Duncan Laurie (Code Review) 02 Mar '19

02 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31657 Change subject: libpayload: keyboard: Add option to ignore failures during init ...................................................................... libpayload: keyboard: Add option to ignore failures during init If keys are pressed at boot some keyboard controllers will not properly respond with an ACK to commands, which results in the keyboard_init function aborting before it adds the keyboard to the input device list. This same keyboard controller will manage to properly return keyboard data when keys are pressed later, so it is possible for it to be functional in the payload even if it does not respond properly to every command during initialization. In order to allow payloads to use the keyboard when this happens a new Kconfig option is added to ignore the keyboard ACK response and always add the keyboard to the input device list. This option is disabled by default and must be enabled by the specific boards that need it. BUG=b:126633269 TEST=boot on device with this controller and press keys during boot and see that the keyboard is still functional in the payload. Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/i8042/keyboard.c 2 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31657/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index a79269f..6aa5b61 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -344,6 +344,10 @@ default y if ARCH_X86 # uses IO default n +config PC_KEYBOARD_IGNORE_FAILURE + bool "Ignore keyboard failures during init and always add input device" + default n + config PC_KEYBOARD_LAYOUT_US bool "English (US) keyboard layout" depends on PC_KEYBOARD diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 062aec2..918cafa 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -309,16 +309,16 @@ /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret) + if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE)) return; ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret) + if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE)) return; /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret) + if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE)) return; console_add_input_driver(&cons); -- To view, visit https://review.coreboot.org/c/coreboot/+/31657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f Gerrit-Change-Number: 31657 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/common/firmware: Add an option to use IFDTOOL
by Mario Scheithauer (Code Review) 01 Mar '19

01 Mar '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31639 Change subject: sb/intel/common/firmware: Add an option to use IFDTOOL ...................................................................... sb/intel/common/firmware: Add an option to use IFDTOOL This patch makes the use of the IFDTOOL to modify the flash descriptor region selectable via a Kconfig option. This option is selected by default so that nothing changes for all mainboards that have activate 'Lock ME/TXE section'. If you don't want to use IFDTOOL for modification of flash descriptor, disable it. In this case, the preset values are retained. Change-Id: I46ec6339008edcc78fe76682eed5714f85354937 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31639/1 diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 31a3df3..7a1bd82 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -141,6 +141,18 @@ depends on HAVE_EC_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin" +config MOD_INTEL_FLASH_DESCRIPTOR + bool "Use IFDTOOL to modifiy descriptor region" + default y + help + Read and write access permissions to different regions in the flash + can be controlled via dedicated bitfields in the flash descriptor. + These permissions can be modified with the Intel Flash Descriptor + Tool (IFDTOOL). If you don't want to change these permissions and + keep the ones provided in the initial descriptor, disable this switch. + +if MOD_INTEL_FLASH_DESCRIPTOR + config LOCK_MANAGEMENT_ENGINE bool "Lock ME/TXE section" default n @@ -154,6 +166,8 @@ If unsure, say N. +endif #MOD_INTEL_FLASH_DESCRIPTOR + config CBFS_SIZE hex default 0x100000 diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 774bb23..331382e 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -68,6 +68,8 @@ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif + +ifeq ($(CONFIG_MOD_INTEL_FLASH_DESCRIPTOR),y) ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool \ @@ -79,6 +81,11 @@ $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif +else + printf " Don't touch Intel Flash Descriptor\n" + cp $(obj)/coreboot.pre $(obj)/coreboot.pre.new + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/31639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46ec6339008edcc78fe76682eed5714f85354937 Gerrit-Change-Number: 31639 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019