coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/skylake: Add H110 PCH series
by Maxim Polyakov (Code Review) 06 Mar '19

06 Mar '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31602 Change subject: soc/intel/skylake: Add H110 PCH series ...................................................................... soc/intel/skylake: Add H110 PCH series This patch adds support H110 chipset (Sunrise Point) for Skylake and Kabylake processor families. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31602/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ba740fc..b2e7b62 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2690,6 +2690,7 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e +#define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 #define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ad004ef..f78d194 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -126,6 +126,7 @@ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, + PCI_DEVICE_ID_INTEL_SPT_H_H110, PCI_DEVICE_ID_INTEL_SPT_H_QM170, PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index ae74489..0da1dbc 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -70,6 +70,7 @@ { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_H_H110, "Skylake PCH-H H110" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Gerrit-Change-Number: 31602 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Add a new desktop i5 CPU
by Maxim Polyakov (Code Review) 06 Mar '19

06 Mar '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31601 Change subject: soc/intel/skylake: Add a new desktop i5 CPU ...................................................................... soc/intel/skylake: Add a new desktop i5 CPU This patch adds support HB: Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host Bridge/DRAM Registers - 191F IGD: HD Graphics 530 Skylake GT2 - Intel integrated graphics processor https://en.wikichip.org/wiki/intel/hd_graphics/530 This is required to run the Coreboot on the Intel Core i5-6600 (Skylake) decktop processor. It has been tested on ASRock H110M-DVS motherboard. Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 4 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31601/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 81654bc..ba740fc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2956,6 +2956,7 @@ /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 +#define PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1 0x1912 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM 0x191E #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM 0x1916 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM 0x191B @@ -3029,6 +3030,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index da2b25f..124d367 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -128,6 +128,7 @@ PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, PCI_DEVICE_ID_INTEL_AML_GT2_ULX, PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 69c1232..0d21250 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -310,6 +310,7 @@ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, + PCI_DEVICE_ID_INTEL_SKL_ID_DT, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index c245523..ae74489 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -52,6 +52,7 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, @@ -95,6 +96,7 @@ const char *name; } igd_table[] = { { PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1"}, + { PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, "Skylake DT GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, "Skylake HALO GT2" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Gerrit-Change-Number: 31601 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT
by Kyösti Mälkki (Code Review) 06 Mar '19

06 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31150 Change subject: [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT ...................................................................... [WIP] nb/intel/sandybridge: Reserve CAR region with !NATIVE_RAMINIT Fail builds if MRC blobs pool heap would get corrupted by CAR relocatable data from coreboot proper. Patch the blob instead: https://review.coreboot.org/c/blobs/+/31149 Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31150/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 7b10f43..fe55071 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -89,6 +89,13 @@ _car_global_end = .; _car_relocatable_data_end = .; +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) + . = ABSOLUTE(0xff7e1000); + _mrc_var_heap_start = .; + . += 0x3000; + _mrc_var_heap_end = .; +#endif + #if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; _car_stack_end = _car_region_end; -- To view, visit https://review.coreboot.org/c/coreboot/+/31150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87 Gerrit-Change-Number: 31150 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: Add multiple device IDs of Intel GPUs
by Felix Singer (Code Review) 06 Mar '19

06 Mar '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30610 Change subject: inteltool: Add multiple device IDs of Intel GPUs ...................................................................... inteltool: Add multiple device IDs of Intel GPUs * Intel UHD Graphics 615 * Intel UHD Graphics 620 (2x) * Intel UHD Graphics 630 (2x) * Intel Iris Graphics 655 Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30610/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 9a58ed8..bace49e 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -347,6 +347,18 @@ "Intel(R) HD 5000 Graphics" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_5000_2, "Intel(R) HD 5000 Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615, + "Intel(R) UHD Graphics 615" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_1, + "Intel(R) UHD Graphics 620" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_620_2, + "Intel(R) UHD Graphics 620" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_1, + "Intel(R) UHD Graphics 630" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_630_2, + "Intel(R) UHD Graphics 630" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655, + "Intel(R) Iris Plus Graphics 655" }, }; #ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index d86ba35..8a36333 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -301,6 +301,15 @@ #define PCI_DEVICE_ID_INTEL_HD_5000 0x0422 #define PCI_DEVICE_ID_INTEL_HD_5000_1 0x0426 #define PCI_DEVICE_ID_INTEL_HD_5000_2 0x042A +#define PCI_DEVICE_ID_INTEL_UHD_615 0x591C +#define PCI_DEVICE_ID_INTEL_UHD_620_1 0x5917 +#define PCI_DEVICE_ID_INTEL_UHD_620_2 0x3EA0 +#define PCI_DEVICE_ID_INTEL_UHD_630_1 0x3E92 +#define PCI_DEVICE_ID_INTEL_UHD_630_2 0x3E9B +#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 + + + #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/30610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Gerrit-Change-Number: 30610 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/superiotool/ite.c: add support for IT8613E
by Krystian Hebel (Code Review) 06 Mar '19

06 Mar '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31620 Change subject: util/superiotool/ite.c: add support for IT8613E ...................................................................... util/superiotool/ite.c: add support for IT8613E Based on not publicly available IT8613E Preliminary Specification V0.3. Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M util/superiotool/ite.c 1 file changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31620/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 06efc57..eebcc0a 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -328,6 +328,40 @@ {0x19, "Power Channel 5", {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x7a,0x00,0x7c,0x01,0x01,EOT}}, + {0x8613, "IT8613E", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {0x86,0x13,0x05,0x40,0x00,0x48,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x00,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,0xfa,0xfb,0xfc,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00, + 0x00,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x2d,0x60,0x61, + 0x62,0x63,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,0xb2, + 0xb3,0xb4,0xb8,0xba,0xbb,0xbc,0xbd,0xc0,0xc1,0xc2, + 0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xda,0xdb, + 0xe0,0xe1,0xe2,0xe3,0xe4,0xec,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0xF3,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x20,0x38,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, + 0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x0e,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, {EOT}}}, {0x8623, "IT8623E", { /* Defaults are not specified as no datasheet available */ @@ -1032,6 +1066,37 @@ }; static const struct superio_registers ec_table[] = { + {0x8613, "IT8613E", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0e,0x0f,0x11,0x12,0x13,0x14,0x16, + 0x17,0x19,0x1a,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22, + 0x24,0x25,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e, + 0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x38,0x39,0x3a, + 0x3b,0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x50, + 0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a, + 0x5b,0x5c,0x5d,0x5e,0x5f,0x68,0x69,0x6a,0x6b,0x6c, + 0x6d,0x6e,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x78, + 0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x80,0x81,0x82,0x83, + 0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x8b,0x8c,0x8d, + 0x8e,0x8f,0x90,0x91,0x98,0x99,0x9c,0x9d,0x9e,0x9f, + 0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xb4,0xb5,0xb6, + 0xb7,0xb8,0xb9,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0, + 0x44,0x00,0x00,MISC,MISC,NANA,NANA,0x00,0x40,0x00, + 0x00,MISC,MISC,NANA,NANA,0x00,0x00,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00, + 0x00,0x7f,0x7f,0x7f,0x40,0x00,0x00,0x90,0x00,0x00, + 0x12,0x60,0x00,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00, + 0x7f,0x0f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x0f,MISC,MISC,MISC,MISC, + NANA,NANA,NANA,NANA,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,MISC,0x00,0x00,0x00,0x00,0x00,NANA,0x00,NANA, + 0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x0f,NANA,NANA,NANA, + NANA,NANA,NANA,EOT}}, + {EOT}}}, {0x8716, "IT8716F", { {NOLDN, NULL, {0x00,0x04,0x05,0x06,0x07,0x08,0x09,0x0b,0x0c,0x10, -- To view, visit https://review.coreboot.org/c/coreboot/+/31620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4 Gerrit-Change-Number: 31620 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30499 to review the following change. Change subject: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage ...................................................................... mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage Qemu does not have a real CAR but postcar stage is still useful to setup pagetables for x86_64 ramstage. Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/lib/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc A src/mainboard/emulation/qemu-i440fx/exit_car.S M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/romstage.c 8 files changed, 75 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30499/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..48dc664 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -132,6 +132,7 @@ ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c +postcar-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index eb9f011..3a507d3 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -14,6 +14,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index 9e2880a..de790e6 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += fw_cfg.c romstage-y += memory.c ramstage-y += memory.c +postcar-y += memory.c +postcar-y += exit_car.S diff --git a/src/mainboard/emulation/qemu-i440fx/exit_car.S b/src/mainboard/emulation/qemu-i440fx/exit_car.S new file mode 100644 index 0000000..74f6ed2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/exit_car.S @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +/* jump directly to the main function, as there is no real CAR to tear down. */ +.text +.global chipset_teardown_car +chipset_teardown_car: + /* Set up new stack. */ + mov post_car_stack_top, %esp + /* Call C code */ + call main diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e31394c..137dfbf 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -20,14 +20,35 @@ #include <cpu/intel/romstage.h> #include <timestamp.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; + console_init(); cbmem_recovery(0); timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 1cc7148..07c15f3 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -13,6 +13,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select BOOTBLOCK_CONSOLE select NO_CAR_GLOBAL_MIGRATION + select POSTCAR_STAGE + select POSTCAR_CONSOLE config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index 1c06d77..a0ac5dd 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -3,4 +3,6 @@ ramstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/memory.c +postcar-y += ../qemu-i440fx/exit_car.S bootblock-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 2b8d935..badafdd 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -21,9 +21,13 @@ #include <timestamp.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <program_loading.h> +#include <cpu/x86/mtrr.h> + +#include "../qemu-i440fx/memory.h" asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; i82801ix_early_init(); console_init(); @@ -31,5 +35,21 @@ timestamp_add_now(TS_START_ROMSTAGE); - run_ramstage(); + if (postcar_frame_init(&pcf, 5 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache memory below 4 GiB */ + postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + /* Cache memory beyond 4 GiB */ + if (qemu_get_high_memory_size() > 0) + postcar_frame_add_mtrr(&pcf, (4ULL * GiB), + qemu_get_high_memory_size() * KiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80 Gerrit-Change-Number: 30499 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: Add SMBus support
by Frans Hendriks (Code Review) 05 Mar '19

05 Mar '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31661 Change subject: soc/intel/braswell: Add SMBus support ...................................................................... soc/intel/braswell: Add SMBus support Intel Braswell SoC contains SMBus controller but not support is available for this controller. This controller is compatible with the Intel SMBus support in the southbridge directory. This smbus.c file in that directory is included. This smbus.c file can be included in build using config SOUTHBRIDGE_INTEL_COMMON and SOUTHBRIDGE_INTEL_COMMON_SMBUS also. This results into build errors, caused by pmbase.c and rtc.c which is include always.. BUG=N/A TEST= Facebook FBG-1710 LCD panel Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31661/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index d5fe1ab..c7d0c6e 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -39,6 +39,7 @@ ramstage-y += sata.c ramstage-y += scc.c ramstage-y += sd.c +ramstage-y += ../../../southbridge/intel/common/smbus.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3 Gerrit-Change-Number: 31661 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: SMBIOS: Update Processor Information structure to v3.2.0
by HAOUAS Elyes (Code Review) 05 Mar '19

05 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31420 Change subject: SMBIOS: Update Processor Information structure to v3.2.0 ...................................................................... SMBIOS: Update Processor Information structure to v3.2.0 Change-Id: I1861615eff904f13029b8d038ffcf3de2d2bfc2a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/31420/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 6498e64..2efd5f0 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -374,6 +374,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/31420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1861615eff904f13029b8d038ffcf3de2d2bfc2a Gerrit-Change-Number: 31420 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus: Add 6GB dual-channel memory configuration
by shkim (Code Review) 05 Mar '19

05 Mar '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31460 to review the following change. Change subject: mb/google/octopus: Add 6GB dual-channel memory configuration ...................................................................... mb/google/octopus: Add 6GB dual-channel memory configuration Add 6GB dual-channel memory configuration for future use. BUG=NONE BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/octopus/variants/baseboard/memory.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31460/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index d81d31f..0ff376f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -189,6 +189,12 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .ch1_dual_rank = 1, }, + /* Dual Channel Config 6GiB System Capacity */ + [7] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_12Gb_DENSITY, + .ch1_rank_density = LP4_12Gb_DENSITY, + }, }; static const struct lpddr4_cfg cbi_lp4cfg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36d6c704ac6708b29cc570a2209eeb32de6148b3 Gerrit-Change-Number: 31460 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: soc/intel/cannonlake: Move common definitions to a header file
by Rizwan Qureshi (Code Review) 04 Mar '19

04 Mar '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31621 Change subject: soc/intel/cannonlake: Move common definitions to a header file ...................................................................... soc/intel/cannonlake: Move common definitions to a header file Move common definitions for PCH H and LP to a common header. Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- A src/soc/intel/cannonlake/include/soc/gpio_common.h M src/soc/intel/cannonlake/include/soc/gpio_defs.h M src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h 3 files changed, 27 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31621/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h new file mode 100644 index 0000000..722637d --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpio_common.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ +#define _SOC_CANNONLAKE_GPIO_COMMON_H_ +#define GPIORXSTATE_MASK 0x1 +#define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 +#define GPIOPADMODE_MASK 0xC00 +#define GPIOPADMODE_SHIFT 10 +#define GPIOTXBUFDIS_MASK 0x100 +#define GPIORXBUFDIS_MASK 0x200 + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 3399526..8a944b1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -19,9 +19,9 @@ #ifndef __ACPI__ #include <stddef.h> #endif +#include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h> - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ @@ -250,13 +250,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIOTXBUFDIS_SHIFT 8 -#define GPIORXBUFDIS_MASK 0x200 -#define GPIORXBUFDIS_SHIFT 9 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index c7f3c81..e77dbf8 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -19,9 +19,9 @@ #ifndef __ACPI__ #include <stddef.h> #endif +#include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h> - #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ @@ -324,13 +324,4 @@ #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIOTXBUFDIS_SHIFT 8 -#define GPIORXBUFDIS_MASK 0x200 -#define GPIORXBUFDIS_SHIFT 9 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127 Gerrit-Change-Number: 31621 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019