coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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1249 discussions

Change in ...coreboot[master]: mb/google/hatch: Reconfigure SD card detect GPIO host software ownership
by Krishna P Bhat D (Code Review) 18 Mar '19

18 Mar '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31178 Change subject: mb/google/hatch: Reconfigure SD card detect GPIO host software ownership ...................................................................... mb/google/hatch: Reconfigure SD card detect GPIO host software ownership This implementation reconfigures SD card detect GPIO(GPP_G5) host ownership to GPIO driver mode. BUG=b:123432607 BRANCH=None TEST=Check SD card gets detected and data transfer working. Change-Id: Id214184f3e183f6feb6887484cd4ccd3bab65b1a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/31178/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index a078997..4b923829 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -138,7 +138,7 @@ /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ - PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_GPI_GPIO_DRIVER(GPP_G5, NONE, DEEP), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP => NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id214184f3e183f6feb6887484cd4ccd3bab65b1a Gerrit-Change-Number: 31178 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: select VMX configurabiltity
by Rizwan Qureshi (Code Review) 18 Mar '19

18 Mar '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31442 Change subject: soc/intel/cannonlake: select VMX configurabiltity ...................................................................... soc/intel/cannonlake: select VMX configurabiltity Select VMX configuration config and implement required soc side API. Also, run vmx_configure() on all CPUs BUG=b:124518711 Change-Id: If9a49deb52e33c1c400a7e2cfab6337b62ecc08e Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cpu.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31442/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..bacbe7b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f987f8b..5f73681 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -24,6 +24,7 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/smm.h> +#include <intelblocks/vmx.h> #include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -31,6 +32,7 @@ #include <soc/pm.h> #include <soc/smm.h> #include <soc/systemagent.h> +#include <timer.h> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -458,6 +460,8 @@ /* Lock down the SMRAM space. */ smm_lock(); + + mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC); } static const struct mp_ops mp_ops = { @@ -484,3 +488,23 @@ /* Thermal throttle activation offset */ configure_thermal_target(); } + +int soc_fill_vmx_param(struct vmx_param *vmx_param) +{ + struct device *dev = SA_DEV_ROOT; + config_t *conf; + + if (!dev) { + printk(BIOS_ERR, "Failed to get root dev for checking VMX param\n"); + return -1; + } + + conf = dev->chip_info; + if (!conf) { + printk(BIOS_ERR, "Failed to get chip_info for VMX param\n"); + return -1; + } + + vmx_param->enable = conf->VmxEnable; + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9a49deb52e33c1c400a7e2cfab6337b62ecc08e Gerrit-Change-Number: 31442 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML
by Maulik V Vaghela (Code Review) 16 Mar '19

16 Mar '19

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31284 to review the following change. Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML ...................................................................... soc/intel/cannonlake: Add required FSP UPD changes for CML This patch adds required FSP UPD changes for CometLake SoC. Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/serialio.h M src/soc/intel/cannonlake/romstage/fsp_params.c 4 files changed, 62 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31284/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cb9ad38..f30116b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,8 @@ #include <soc/gpio_defs.h> #endif +#define SOC_INTEL_UART_DEV_MAX 3 + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -101,7 +103,7 @@ * For CNL, options are as following * When enabled, memory will be training at three different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled - * For WHL/CFL options are as following + * For WHL/CFL/CML options are as following * When enabled, memory will be training at two different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ enum { @@ -286,6 +288,19 @@ DebugConsent_XDP, /* XDP/Mipi60 */ DebugConsent_USB2_DBC, } DebugConsent; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + /* + * SerialIO device mode selection: + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[SOC_INTEL_UART_DEV_MAX]; +#else /* * SerialIO device mode selection: * @@ -310,7 +325,7 @@ * PchSerialIoHidden */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; - +#endif /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 866d9c8..ecd22d4 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,6 +34,16 @@ } const config_t *config = dev->chip_info; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + + for (int i = 0; i < SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +#else const int SerialIoDev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -60,6 +70,7 @@ config->SerialIoDevMode[i] == PchSerialIoHidden) params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; } +#endif } /* UPD parameters to be initialized before SiliconInit */ @@ -165,8 +176,11 @@ /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + params->CnviMode = dev->enabled; +#else params->PchCnviMode = dev->enabled; - +#endif /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index e152770..fad7283 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,8 +22,33 @@ PchSerialIoPci, PchSerialIoAcpi, PchSerialIoHidden, +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) + PchSerialIoSkipInit +#endif } PCH_SERIAL_IO_MODE; +#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +}; + +enum { + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2 +}; +#else typedef enum { PchSerialIoIndexI2C0, PchSerialIoIndexI2C1, @@ -39,5 +64,6 @@ PchSerialIoIndexUART2, PchSerialIoIndexMAX } PCH_SERIAL_IO_CONTROLLER; +#endif #endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index b8b2c17..c436e50 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -- To view, visit https://review.coreboot.org/c/coreboot/+/31284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Gerrit-Change-Number: 31284 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lint/clang-format: set to 96 chars per line
by Patrick Georgi (Code Review) 15 Mar '19

15 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31651 Change subject: lint/clang-format: set to 96 chars per line ...................................................................... lint/clang-format: set to 96 chars per line 80 chars + 2 tabs was the compromise we got to in the last round of discussion. Change-Id: I9293a69d1bea900da36501cde512004d0695ad37 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M .clang-format M util/lint/lint-007-checkpatch 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31651/1 diff --git a/.clang-format b/.clang-format index d853f50..5c8aa3c 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 96 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index afa593e..a7b63e8 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -28,6 +28,8 @@ ^src/vendorcode\|\ ^Documentation" +opts="--max-line-length 96" + # default: test src and util if [ "$1" = "" ]; then INCLUDED_DIRS="src util" @@ -35,7 +37,7 @@ elif [ "$1" = "diff" ]; then args=$( echo $EXCLUDED_DIRS | \ sed -e 's,\\|, ,g' -e 's,\^,--exclude=,g' ) - util/lint/checkpatch.pl --quiet --no-signoff $args - + util/lint/checkpatch.pl --quiet --no-signoff $opts $args - exit $? # Space separated list of directories to test else @@ -49,5 +51,5 @@ grep -v $EXCLUDED_DIRS ) for FILE in $FILELIST; do - util/lint/checkpatch.pl --show-types --file --quiet "$FILE" + util/lint/checkpatch.pl --show-types --file --quiet $opts "$FILE" done -- To view, visit https://review.coreboot.org/c/coreboot/+/31651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9293a69d1bea900da36501cde512004d0695ad37 Gerrit-Change-Number: 31651 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: add 300 Series and C240 Series Northbridge (Coffeelake)
by Thomas Heijligen (Code Review) 15 Mar '19

15 Mar '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31500 Change subject: inteltool: add 300 Series and C240 Series Northbridge (Coffeelake) ...................................................................... inteltool: add 300 Series and C240 Series Northbridge (Coffeelake) Values from Intel doc 337347 rev4 Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31500/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..37b3f2a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -250,6 +250,16 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q370, "Q370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B360, "B360" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C246, "C246" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C242, "C242" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM370, "QM370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM370, "HM370" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM246, "CM246" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, "C8 Mobile"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, "C8 Desktop"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87"}, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..6cf15fc 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -165,6 +165,18 @@ #define PCI_DEVICE_ID_INTEL_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_CM238 0xa154 + +#define PCI_DEVICE_ID_INTEL_H310 0xa303 +#define PCI_DEVICE_ID_INTEL_H370 0xa304 +#define PCI_DEVICE_ID_INTEL_Z390 0xa305 +#define PCI_DEVICE_ID_INTEL_Q370 0xa306 +#define PCI_DEVICE_ID_INTEL_B360 0xa308 +#define PCI_DEVICE_ID_INTEL_C246 0xa309 +#define PCI_DEVICE_ID_INTEL_C242 0xa30a +#define PCI_DEVICE_ID_INTEL_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_HM370 0xa30d +#define PCI_DEVICE_ID_INTEL_CM246 0xa30e + #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 -- To view, visit https://review.coreboot.org/c/coreboot/+/31500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Gerrit-Change-Number: 31500 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asu...
by Balázs Vinarz (Code Review) 15 Mar '19

15 Mar '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30895 Change subject: 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m ...................................................................... 1st version 1:1 copy from old wiki https://www.coreboot.org/Board:asus/f2a85-m Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> --- A Documentation/mainboard/asus/f2a85-m.md 1 file changed, 271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30895/1 diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md new file mode 100644 index 0000000..c4ee0cf --- /dev/null +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -0,0 +1,271 @@ +Disclaimer: This board is not widely sold any longer. However, refer to F2A85 series status for newer models. ASUS F2A85 PRO should be work in progress (WIP). +Contents + + 1 Status + 1.1 Supported processing units + 1.1.1 CPUs + 1.1.2 APUs + 1.2 Notes + 1.3 TODOs + 2 UEFI builds that allow flash chip access + 3 Hardware info + 3.1 DDR voltage controller + 3.2 The ASUS digi VRM + 3.3 Memory + 4 See also + 4.1 F2A85 series status + 5 References + +Status +Device/functionality Status Comments +CPU +CPU works OK the board will start with an AMD A8-5500 +L1 cache enabled OK +L2 cache enabled OK +L3 cache enabled N/A +Multiple CPU support OK +Multi-core support OK +Hardware virtualization Untested +RAM +EDO N/A +SDRAM N/A +SO-DIMM N/A +DDR N/A +DDR2 N/A +DDR3 OK Please select right voltage in menuconfig! Default is 1.5V but some DIMMs need more or less! +Dual channel support OK +ECC support N/A +On-board Hardware +On-board IDE 3.5" N/A +On-board IDE 2.5" N/A +On-board SATA OK Tested all ports of sixpack. +On-board SCSI N/A +On-board USB OK Issues with XHCI exist with Asus' BIOS as well +On-board VGA OK Use dd to extract the legacy BIOS, HDMI untested +On-board Ethernet OK +On-board Audio OK tested with headphones in line-out (lime colored) +On-board Modem N/A +On-board FireWire N/A +On-board Smartcard reader N/A +On-board CompactFlash N/A +On-board PCMCIA N/A +On-board Wifi N/A +On-board Bluetooth N/A +On-board SD card reader N/A +Add-on slots/cards +ISA add-on cards N/A +Audio/Modem-Riser (AMR/CNR) cards N/A +PCI add-on cards OK +Mini-PCI add-on cards N/A +Mini-PCI-Express add-on cards Unknown +PCI-X add-on cards N/A +AGP graphics cards N/A +PCI Express x1 add-on cards OK +PCI Express x2 add-on cards N/A +PCI Express x4 add-on cards OK +PCI Express x8 add-on cards N/A +PCI Express x16 add-on cards OK +PCI Express x32 add-on cards N/A +HTX add-on cards N/A +Legacy / Super I/O +Floppy N/A +Serial port 1 (COM1) OK +Serial port 2 (COM2) N/A +Parallel port N/A +PS/2 keyboard OK +PS/2 mouse Untested +Game port N/A +Infrared ? +PC speaker OK +DiskOnChip N/A +Input +Trackpoint N/A +Touchpad N/A +Fn Hotkeys N/A +Fingerprint Reader N/A +Laptop +Docking VGA N/A +Docking LAN N/A +Docking USB N/A +Docking Audio N/A +Docking Displayport N/A +Thinklight N/A +Webcam N/A +Miscellaneous +Sensors / fan control Untested +Hardware watchdog Unknown +SMBus Unknown +CAN bus N/A +CPU frequency scaling OK +Other powersaving features ? +ACPI OK ACPI power button event works, suspend is WIP (work in progress). +Reboot OK warm reboot from Asus' BIOS to coreboot does not work, use reset button after the first time you flash coreboot +Poweroff OK +Suspend OK +Nonstandard LEDs OK +High precision event timers (HPET) OK +Random number generator (RNG) ? +Wake on modem ring Untested +Wake on LAN Untested +Wake on keyboard Untested +Wake on mouse Untested +TPM Unknown +Flashrom OK +Supported processing units + +ASUS F2A85-M CPU specification:[1] + + AMD Socket FM2 Athlon�/A- Series Processors + Supports CPU up to 4 cores + Supports AMD� Turbo Core 3.0 Technology + Addenum: AMD Sempron X2 250[2] + +Note: Only AMD Virgo: "Trinity" desktop processing units are supported (see list below) but with a hack also Richland desktop processing units might work (contact via mailing list for details). Wikipedia's list of Trinity processors might be more actively maintained. +CPUs + + AMD Athlon X2 340 + AMD Athlon X4 740 + AMD Athlon X4 750k + +APUs + +The CPU architecture in these APUs are Piledriver, and their GPU is TeraScale 3 (VLIW4-based). + + AMD A4-5300 + AMD A4-5300B + AMD A6-5400K + AMD A6-5400B + AMD A8-5500 + AMD A8-5500B + AMD A8-5600K + AMD A10-5700 + AMD A10-5800B + AMD A10-5800K + AMD FirePro A300 - Only sold by OEM + AMD FirePro A320 - Only sold by OEM + +Notes + + Retrieve the VGA optionrom from the vendor EFI binary by running: + +dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +(source) + +For internal VGA: Boot the legacy BIOS, and use VGA_support chapter + + Add the extracted VGA optionrom in menuconfig. The device ID for the APU graphics varies, run 'lspci -nn | grep VGA' to find the right ID. + If you use PS/2 de-select legacy free + De-select running option ROMs, Seabios will run the ROMs that coreboot loads into memory so you should get a text display from Seabios + It is required that seabios is the coreboot payload for the F2A85-M or the internal VGA will not be initialized. But read SeaBIOS for how to add payloads to SeaBIOS and set SeaBIOS' boot order to run your payload. + its internal VGA comes up just fine (using Change ID I9e0df1669d73863c95c36a3a7fee40d58f6f097e), with unpatched SeaBIOS and these settings: + CONFIG_VGA_ROM_RUN=y + CONFIG_PCI_ROM_RUN=y + CONFIG_ON_DEVICE_ROM_RUN=y + Hotswapping the PDIP BIOS chip has some issues (most likely USB3 XHCI, disable it in original bios before hot-flashing to coreboot). Drop a mail to mailing list if you have issues. + +TODOs + + test virtualization + test IOMMU + test HDMI: video over hdmi works with the extracted vga optionrom, audio is untested. + blink in suspend mode (GP43, program LDN7 F8=23 and blink with F9=2 for 1s blinks) + fix mptable + fix resume with USB3.0 used (perhaps there is a bug in resume.c) + fix immediate resume after suspend (perhaps PCIe STS needs to be cleared) + +UEFI builds that allow flash chip access + + v5016 is untested, but expected to work as well + v5018 + v5103 + v5104 + v5107 + v5202 + v6002 + v6004 + v6102 + v6402 + v6404 (requires downgrading to v6402 to flash coreboot) + v6501 (requires downgrading to v6402 to flash coreboot) + v6502 (requires downgrading to v6402 to flash coreboot) + +Build v6502, v6501 and v6404 do not allow access to the flash chip. + +Fortunately it is possible to downgrade build v6502, v6501 and v6404 to v6402, with EZFlash. + +Downgrading is done by downloading build v6402 from ASUS' F2A85-M download page and copying it to (the root directory of) a FAT32 formatted USB flash drive. + +Enter the EFI setup, switch to advanced mode if necessary, open the 'Tool' tab and select "ASUS EZ Flash 2 Utility". +Hardware info + +This board ships with a socketed Winbond 25Q64F, 64 Mbit (8 Mbyte) chip, in PDIP 300 mil package: +Winbond 25Q64F + +The chip manual is available here + +For out of band flashing, I use a + + 3M test clip model 923739-08-ND + +It has .300" spacing, 8 pin DIP clip, gold finish and 'headless heads'. I hook this up to a bus pirate. This works but reading and writing take forever: + +\# time /usr/src/flashrom/flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w 20130826-coreboot.rom +flashrom v0.9.6.1-r1669 on Linux 3.8-2-amd64 (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +Calibrating delay loop... OK. +Found Winbond flash chip "W25Q64" (8192 kB, SPI) on buspirate_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... Erase/write done. +Verifying flash... VERIFIED. + +real 35m35.409s +user 0m55.976s +sys 0m12.920s + +DDR voltage controller + +The DDR voltage controller is accessible through the AUX SMBUS device 0x15 and it is most likely driven by programmable current source NCT3933U (datasheet on nuvoton website). +The ASUS digi VRM + +The ASUS digi voltage controller is accessible through the SMBUS device 0x20 and it is most likely driven by CHL8318 or similar chip (re-branded) +Memory + +If you use single dimm plug it to DIMM_A2 or DIMM_B2. + +I use: + +2x 2GB DDR3 modules in blue slots: + +\#modprobe i2c-piix4 +\#modprobe eeprom +\#decode-dimms + +---=== Memory Characteristics ===--- +Fine time base 2.500 ps +Medium time base 0.125 ns +Maximum module speed 1333MHz (PC3-10666) +Size 2048 MB +Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 +Ranks 2 +SDRAM Device Width 8 bits +tCL-tRCD-tRP-tRAS 8-8-8-24 +Supported CAS Latencies (tCL) 9T, 8T, 7T, 6T + +See also +F2A85 series status + +Only boards with internal wiki page links are Supported Motherboards. + + ASUS F2A85-M + ASUS F2A85-M LE + ASUS F2A85-M PRO[3] - the most available model in the entire F2A85 series. Be sure to check its status to see what works and what doesn't. + ASUS F2A85-M2 - Confirmed working in the #coreboot IRC channel 2015-03-04. Unsure if WIP. + ASUS F2A85-M/CSM - Unsure if WIP. + +References + + Jump up ↑ https://www.asus.com/Motherboards/F2A85M/specifications/ + Jump up ↑ http://support.asus.com/Cpusupport/List.aspx?SLanguage=en&m=F2A85-M&p=1&s=43 + Jump up ↑ http://www.asus.com/Motherboards/F2A85M_PRO/ -- To view, visit https://review.coreboot.org/c/coreboot/+/30895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Gerrit-Change-Number: 30895 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

5 29

Change in ...coreboot[master]: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant
by Raymond Chung (Code Review) 15 Mar '19

15 Mar '19

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31023 Change subject: [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant ...................................................................... [TEST_ONLY, DO_NOT_MERGE] mb/google/octopus: Create phasal variant This creates a phasal variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:None TEST=None Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e Signed-off-by: “raymondchung” <“raymondchung(a)ami.corp-partner.google.xn--com-9o0a> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/phasal/Makefile.inc A src/mainboard/google/octopus/variants/phasal/gpio.c A src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/phasal/include/variant/ec.h A src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h A src/mainboard/google/octopus/variants/phasal/overridetree.cb A src/mainboard/google/octopus/variants/phasal/variant.c 9 files changed, 358 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31023/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index a237741..a62cd19 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -56,6 +56,7 @@ default "meep" if BOARD_GOOGLE_MEEP default "ampton" if BOARD_GOOGLE_AMPTON default "casta" if BOARD_GOOGLE_CASTA + default "phasal" if BOARD_GOOGLE_PHASAL default "octopus" if BOARD_GOOGLE_OCTOPUS config DEVICETREE @@ -76,6 +77,7 @@ default "Meep" if BOARD_GOOGLE_MEEP default "Ampton" if BOARD_GOOGLE_AMPTON default "Casta" if BOARD_GOOGLE_CASTA + default "Phasal" if BOARD_GOOGLE_PHASAL default "Octopus" if BOARD_GOOGLE_OCTOPUS config MAINBOARD_FAMILY @@ -93,6 +95,7 @@ default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA + default "PHASAL TEST 7167" if BOARD_GOOGLE_PHASAL default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS config MAX_CPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 498da36..71e5197 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -52,3 +52,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_PHASAL + bool "-> Phasal" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/phasal/Makefile.inc b/src/mainboard/google/octopus/variants/phasal/Makefile.inc new file mode 100644 index 0000000..d54ed40 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/phasal/gpio.c b/src/mainboard/google/octopus/variants/phasal/gpio.c new file mode 100644 index 0000000..322b44b --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/gpio.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +#include <console/console.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config sku1_default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + google_chromeec_cbi_get_sku_id(&sku_id); + if (sku_id == 1) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/phasal/overridetree.cb b/src/mainboard/google/octopus/variants/phasal/overridetree.cb new file mode 100644 index 0000000..b131173 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/overridetree.cb @@ -0,0 +1,164 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + end # - I2C 7 + end +end diff --git a/src/mainboard/google/octopus/variants/phasal/variant.c b/src/mainboard/google/octopus/variants/phasal/variant.c new file mode 100644 index 0000000..22f4f71 --- /dev/null +++ b/src/mainboard/google/octopus/variants/phasal/variant.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1 does not have a touchscreen device, hence disable it. */ + google_chromeec_cbi_get_sku_id(&sku_id); + if (sku_id == 1) + touchscreen_i2c_host->enabled = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c26195d44a268df2aff64b224c4376f0e9059e Gerrit-Change-Number: 31023 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/arcada: Update USB2 port6 AFE setting
by Lijian Zhao (Code Review) 14 Mar '19

14 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31632 Change subject: mb/google/arcada: Update USB2 port6 AFE setting ...................................................................... mb/google/arcada: Update USB2 port6 AFE setting Accoriding to 574354, we need to tune each port to pass eye diagram other than just use recommanded setting as they are base guidence only. Bug=b:124407280 TEST=Build and boot up on sarien board. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I587695809b368edd33852c4241de097ca31e9d66 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31632/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 244ba7a..cded5ff 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -125,7 +125,14 @@ register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[6]" = "{ + .enable = 1, \ + .ocpin = OC_SKIP, \ + .tx_bias = USB2_BIAS_0MV, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_28P15MV, \ + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + }" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth -- To view, visit https://review.coreboot.org/c/coreboot/+/31632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I587695809b368edd33852c4241de097ca31e9d66 Gerrit-Change-Number: 31632 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: copy data structures to cbmem for downstream use
by Joel Kitching (Code Review) 14 Mar '19

14 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31329 Change subject: vboot: copy data structures to cbmem for downstream use ...................................................................... vboot: copy data structures to cbmem for downstream use For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot verification occurs before cbmem is brought online. In order to make vboot data structures available downstream, copy vb2_working_data from SRAM into cbmem when cbmem comes online. BUG=b:124141368, b:124192753 TEST=Build locally TEST=util/lint/checkpatch.pl --ignore GERRIT_CHANGE_ID -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: I62c11268a83927bc00ae9bd93b1b31363b38e8cf Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/common.c 1 file changed, 32 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31329/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 747644a..8b73697 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -40,47 +40,32 @@ uint32_t buffer_size; }; -static const size_t vb_work_buf_size = 16 * KiB; +static struct vb2_working_data *vb2_wd = NULL; static struct vb2_working_data * const vboot_get_working_data(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - /* cbmem_add() does a cbmem_find() first. */ - return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); - else - return (struct vb2_working_data *)_vboot2_work; + if (vb2_wd == NULL) { +#if ENV_POSTCAR || ENV_RAMSTAGE + /* cbmem_find is linked from romstage onward */ + vb2_wd = cbmem_find(CBMEM_ID_VBOOT_WORKBUF); +#else + /* _vboot2_work is accessible until end of romstage */ + vb2_wd = (struct vb2_working_data *)_vboot2_work; +#endif + } + assert(vb2_wd != NULL); + return vb2_wd; } static size_t vb2_working_data_size(void) { - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - return vb_work_buf_size; - else - return _vboot2_work_size; + /* _vboot2_work_size is accessible until end of romstage */ + return _vboot2_work_size; } static struct selected_region *vb2_selected_region(void) { - struct selected_region *sel_reg = NULL; - - /* Ramstage and postcar always uses cbmem as a source of truth. */ - if (ENV_RAMSTAGE || ENV_POSTCAR) - sel_reg = cbmem_find(CBMEM_ID_VBOOT_SEL_REG); - else if (ENV_ROMSTAGE) { - /* Try cbmem first. Fall back on working data if not found. */ - sel_reg = cbmem_find(CBMEM_ID_VBOOT_SEL_REG); - - if (sel_reg == NULL) { - struct vb2_working_data *wd = vboot_get_working_data(); - sel_reg = &wd->selected_region; - } - } else { - /* Stages such as bootblock and verstage use working data. */ - struct vb2_working_data *wd = vboot_get_working_data(); - sel_reg = &wd->selected_region; - } - - return sel_reg; + return &vboot_get_working_data()->selected_region; } void vb2_init_work_context(struct vb2_context *ctx) @@ -104,7 +89,6 @@ memset(ctx, 0, sizeof(*ctx)); ctx->workbuf = (void *)vb2_get_shared_data(); ctx->workbuf_size = wd->buffer_size; - } struct vb2_shared_data *vb2_get_shared_data(void) @@ -148,33 +132,30 @@ return reg->size > 0; } -void vb2_store_selected_region(void) +void vb2_store_working_data(void) { - const struct vb2_working_data *wd; - struct selected_region *sel_reg; + struct vb2_working_data *wd; + struct vb2_working_data *wd_cbmem; - /* Always use the working data in this path since it's the object - * which has the result.. */ + wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb2_working_data_size()); + assert(wd_cbmem != NULL); + +#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) wd = vboot_get_working_data(); + /* No data to copy yet on platforms with VBOOT_STARTS_IN_ROMSTAGE. */ + memcpy(wd_cbmem, wd, vb2_working_data_size()); +#endif - sel_reg = cbmem_add(CBMEM_ID_VBOOT_SEL_REG, sizeof(*sel_reg)); - - assert(sel_reg != NULL); - - sel_reg->offset = wd->selected_region.offset; - sel_reg->size = wd->selected_region.size; + vb2_wd = wd_cbmem; } /* - * For platforms that employ VBOOT_STARTS_IN_ROMSTAGE, the vboot - * verification doesn't happen until after cbmem is brought online. - * Therefore, the selected region contents would not be initialized - * so don't automatically add results when cbmem comes online. + * For platforms that do not employ VBOOT_STARTS_IN_ROMSTAGE, vboot verification + * occurs before cbmem is brought online. In order to make vboot data + * structures available downstream, copy vb2_working_data from SRAM into cbmem. */ -#if !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE) -static void vb2_store_selected_region_cbmem(int unused) +static void vb2_store_cbmem(int unused) { - vb2_store_selected_region(); + vb2_store_working_data(); } -ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_selected_region_cbmem) -#endif +ROMSTAGE_CBMEM_INIT_HOOK(vb2_store_cbmem) -- To view, visit https://review.coreboot.org/c/coreboot/+/31329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62c11268a83927bc00ae9bd93b1b31363b38e8cf Gerrit-Change-Number: 31329 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku
by Shelley Chen (Code Review) 14 Mar '19

14 Mar '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31358 Change subject: mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku ...................................................................... mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize MemorySpdPrt pointers based on the value read from MEM_CH_SEL, which is read from GPP_F2. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/hatch/variants/baseboard/memory.c 4 files changed, 47 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31358/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..b2db7ee 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg memcfg; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; + variant_memory_params(&memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + &memcfg, &spd); } diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index f8d5d7d..b87cfa8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -115,6 +115,8 @@ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), + /* MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), /* UART_WWANTX_WLANRX_COEX1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* UART_WWANRX_WLANTX_COEX2 */ @@ -185,6 +187,8 @@ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), }; const struct pad_config *__weak variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 038ec6e..aa7c67d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ #ifndef BASEBOARD_VARIANTS_H #define BASEBOARD_VARIANTS_H +#include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -29,7 +30,7 @@ int variant_memory_sku(void); /* Return board specific memory configuration */ -const struct cnl_mb_cfg *variant_memory_params(void); +void variant_memory_params(struct cnl_mb_cfg *bcfg); /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index 80f3ba4..977573d 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -18,33 +18,46 @@ #include <gpio.h> #include <soc/cnl_memcfg_init.h> -static const struct cnl_mb_cfg baseboard_memcfg = { - /* - * The dqs_map arrays map the ddr4 pins to the SoC pins - * for both channels. - * - * the index = pin number on ddr4 part - * the value = pin number on SoC - */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - - /* Baseboard uses 120, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 120, 81, 100 }, - - /* Baseboard Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* Set CaVref config to 2 */ - .vref_ca_config = 2, - - /* Enable Early Command Training */ - .ect = 1, +/* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ +static const uint8_t dqs_map_ddr4[][8] = { + { 0, 1, 4, 5, 2, 3, 6, 7 }, + { 0, 1, 4, 5, 2, 3, 6, 7 } }; +/* Baseboard uses 120, 81 and 100 rcomp resistors */ +const static uint16_t rcomp_resistor_ddr4[] = { 120, 81, 100 }; +/* Baseboard Rcomp target values */ +const static uint16_t rcomp_targets_ddr4[] = { 100, 40, 20, 20, 26 }; -const struct cnl_mb_cfg *__weak variant_memory_params(void) +void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { - return &baseboard_memcfg; + int i; + + for (i = 0; i < sizeof(dqs_map_ddr4[DDR_CH0])/sizeof(uint8_t); i++) { + bcfg->dqs_map[DDR_CH0][i] = dqs_map_ddr4[DDR_CH0][i]; + bcfg->dqs_map[DDR_CH1][i] = dqs_map_ddr4[DDR_CH1][i]; + } + + for (i = 0; i < sizeof(rcomp_resistor_ddr4)/sizeof(uint16_t); i++) + bcfg->rcomp_resistor[i] = rcomp_resistor_ddr4[i]; + + for (i = 0; i < sizeof(rcomp_targets_ddr4)/sizeof(uint16_t); i++) + bcfg->rcomp_targets[i] = rcomp_targets_ddr4[i]; + + bcfg->vref_ca_config = 2; + bcfg->ect = 1; + + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + if (gpio_get(GPP_F2) == 1) + bcfg->single_channel = 1; } int __weak variant_memory_sku(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Gerrit-Change-Number: 31358 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019