coreboot-gerrit February 2019

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Change in ...coreboot[master]: mistral: qcs405: copy calibration data to CBMEM
by Name of user not set (Code Review) 20 Mar '19

20 Mar '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30714 Change subject: mistral: qcs405: copy calibration data to CBMEM ...................................................................... mistral: qcs405: copy calibration data to CBMEM This pacth adds support to copy the wifi calibration data to CBMEM so that the depthcharge can use it to populate the data into wifi dt node. Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30714/1 diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index f4fc31e..3605fba 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -17,6 +17,7 @@ #include <bootblock_common.h> #include <timestamp.h> #include <soc/usb.h> +#include <vendorcode/google/chromeos/chromeos.h> #if 0 static struct usb_board_data usb0_board_data = { @@ -46,6 +47,10 @@ static void mainboard_init(device_t dev) { setup_usb(); + if (IS_ENABLED(CONFIG_CHROMEOS)) { + /* Copy WIFI calibration data into CBMEM. */ + cbmem_add_vpd_calibration_data(); + } } static void mainboard_enable(device_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/30714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Gerrit-Change-Number: 30714 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard: Add ASRock H110M-DVS
by Maxim Polyakov (Code Review) 19 Mar '19

19 Mar '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31603 Change subject: mainboard: Add ASRock H110M-DVS ...................................................................... mainboard: Add ASRock H110M-DVS This board is compatible with Intel Skylake and Kabylake generation processors. This patch contains the minimum configuration for booting and stable operation of the OS. It is based on Intel RVP8 mainboard. Intel FSP2.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Work: - Integrated graphics (only DVI port); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console. TODO: - onboard audio; - other SuperIO functions; - onboard network chip; - documentation. Tested on Intel Core i5-6600 processor with Seabios and Tianocore as a payload; booting Ubuntu 16.04.2 with Linux kernel 4.15 Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c A src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb A src/mainboard/asrock/h110m/variants/dvs/data.vbt A src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h A src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb 26 files changed, 1,477 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig new file mode 100644 index 0000000..3629d7c --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig @@ -0,0 +1,93 @@ +if BOARD_ASROCK_H110M_DVS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_DESKTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select GENERIC_SPD_BIN + select TSC_MONOTONIC_TIMER + select SERIRQ_CONTINUOUS_MODE + select SUPERIO_NUVOTON_NCT6791D + select SUPERIO_NUVOTON_NCT6776_COM_A + select HAVE_SMI_HANDLER + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +choice + prompt "Processor family" + default USE_SOC_INTEL_SKYLAKE + +config USE_SOC_INTEL_SKYLAKE + bool "Skylake" + select SOC_INTEL_SKYLAKE + +config USE_SOC_INTEL_KABYLAKE + bool "Kabylake" + select SOC_INTEL_KABYLAKE + +endchoice + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asrock/h110m" + +config VARIANT_DIR + string + default "dvs" if BOARD_ASROCK_H110M_DVS + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAINBOARD_FAMILY + string + default "ASROCK" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.dvs.bin" if BOARD_ASROCK_H110M_DVS + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.dvs.bin" if BOARD_ASROCK_H110M_DVS + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name new file mode 100644 index 0000000..34c1a3c --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H110M_DVS + bool "H110M-DVS" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc new file mode 100644 index 0000000..558af91 --- /dev/null +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/asrock/h110m/acpi/dptf.asl b/src/mainboard/asrock/h110m/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/h110m/acpi/ec.asl b/src/mainboard/asrock/h110m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/ec.asl diff --git a/src/mainboard/asrock/h110m/acpi/mainboard.asl b/src/mainboard/asrock/h110m/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/mainboard.asl diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/acpi_tables.c b/src/mainboard/asrock/h110m/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi_tables.c diff --git a/src/mainboard/asrock/h110m/board_info.txt b/src/mainboard/asrock/h110m/board_info.txt new file mode 100644 index 0000000..7b7f3d4 --- /dev/null +++ b/src/mainboard/asrock/h110m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n +Release year: 2015 diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c new file mode 100644 index 0000000..771ce13 --- /dev/null +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <console/console.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); + printk(BIOS_INFO, "Early init console SIO!\n"); +} diff --git a/src/mainboard/asrock/h110m/cmos.default b/src/mainboard/asrock/h110m/cmos.default new file mode 100644 index 0000000..cd8bd47 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl new file mode 100644 index 0000000..ca8c327 --- /dev/null +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asrock/h110m/gma-mainboard.ads b/src/mainboard/asrock/h110m/gma-mainboard.ads new file mode 100644 index 0000000..b217608 --- /dev/null +++ b/src/mainboard/asrock/h110m/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c new file mode 100644 index 0000000..b219987 --- /dev/null +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c new file mode 100644 index 0000000..155d347 --- /dev/null +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c new file mode 100644 index 0000000..64c5468 --- /dev/null +++ b/src/mainboard/asrock/h110m/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" +#include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/asrock/h110m/spd/Makefile.inc b/src/mainboard/asrock/h110m/spd/Makefile.inc new file mode 100644 index 0000000..cdf469e --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c \ No newline at end of file diff --git a/src/mainboard/asrock/h110m/spd/spd.h b/src/mainboard/asrock/h110m/spd/spd.h new file mode 100644 index 0000000..c24baa0 --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/spd.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include <variant/gpio.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/asrock/h110m/spd/spd_util.c b/src/mainboard/asrock/h110m/spd/spd_util.c new file mode 100644 index 0000000..64c92cc --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/spd_util.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <console/console.h> +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb b/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..edff72c --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb @@ -0,0 +1,251 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "SerialIrqConfigSirqMode" = "0x01" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C3] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C5] = PchSerialIoSkipInit, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x191f + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 off end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asrock/h110m/variants/dvs/data.vbt b/src/mainboard/asrock/h110m/variants/dvs/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/data.vbt Binary files differ diff --git a/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h b/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h new file mode 100644 index 0000000..77a11bd --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_D3H_H +#define _GPIO_D3H_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h b/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h new file mode 100644 index 0000000..746f0ef --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb new file mode 100644 index 0000000..9c3cd6d --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb @@ -0,0 +1,187 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C3] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C5] = PchSerialIoSkipInit, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6..8 + device pnp 2e.8 off end # WDT1, WDT_MEM, GPIO 0, GPIO 1 + device pnp 2e.9 off end # GPIO 2, GPIO 3, GPIO 4, GPIO 5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # Deep sleep + + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/31603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Gerrit-Change-Number: 31603 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov Gerrit-MessageType: newchange

8 30

Change in ...coreboot[master]: util/autoport: Rewrite readme.md
by Angel Pons (Code Review) 18 Mar '19

18 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30969 Change subject: util/autoport: Rewrite readme.md ...................................................................... util/autoport: Rewrite readme.md The last part of the file has not been modified much. Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/readme.md 1 file changed, 195 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30969/1 diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 226fcda..4683d8d 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -6,23 +6,27 @@ For any Sandy Bridge or Ivy Bridge platform the generated result should be bootable, possibly with minor fixes. -### EC +### EC / SuperIO EC support is likely to work on Intel-based thinkpads. Other laptops are -likely to miss EC support. +likely to miss EC support. SuperIO support on desktops is more likely to +work out of the box than any EC. -## How to use +## How to use autoport -* Go into BIOS setup on the target machine and enable all devices. -This will allow autoport to detect as much as possible. -* Boot into target machine under GNU/Linux -* Make sure that the following components are installed: - * GCC - * golang - * lspci - * dmidecode - * acpidump -* Grab coreboot tree -* Execute following commands starting from coreboot tree +Enable as many devices as possible in the firmware setup of your system. +This is useful to detect as many devices as possible and make the port +more complete, as disabled devices cannot be detected. + +Boot into target machine under any Linux-based distribution and install +the following tools on it: +* `gcc` +* `golang` +* `lspci` +* `dmidecode` +* `acpidump` (part of `acpica` on some distros) + +Clone the coreboot tree and `cd` into it. For more detailed steps, refer +to Rookie Guide, Lesson 1. Afterwards, run these commands: cd util/ectool make @@ -34,60 +38,89 @@ go build sudo ./autoport --input_log=logs --make_logs --coreboot_dir=../.. - Note: in case you have problems getting gcc and golang to target machine - you can just compile on another machine and transfer the binaries - `autoport`, `inteltool` and `ectool`. You'll still need other prerequisites - but you may place them in the same directory as autoport. + Note: in case you have problems getting gcc and golang on the target + machine, you can compile the utilities on another computer and copy + the binaries to the target machine. You will still need the other + listed programs on the target machine, but you may place them in the + same directory as autoport. -* Look for output unknown PCI devices. E.g. +Check for unknown detected PCI devices, e.g.: Unknown PCI device 8086:0085, assuming removable -If autoport says `assuming removable` then you're fine. If it doesn't -then you may want to add relevant PCIIDs to autoport. When rerunning -you can skip argument `--make_logs` to reuse the same logs +If autoport says `assuming removable`, you are fine. If it doesn't, +you may want to add the relevant PCI IDs to autoport. Run `lspci -nn` +and check which device this is using the PCI ID. Devices which are not +part of the chipset, such as GPUs or network cards, can be considered +removable, whereas devices inside the CPU or the PCH such as integrated +GPUs and bus controllers (SATA, USB, LPC, SMBus...) are non-removable. -* At this point the new board is added to the tree but don't flash it -yet as it will brick your machine. Instead keep this new port and the logs -from `util/autoport/logs` somewhere safe. +Your board has now been added to the tree. However, do not flash it +in its current state. It can brick your machine. Instead, keep this +new port and the logs from `util/autoport/logs` somewhere safe. The +following steps will back up your current firmware, which is always +recommended, since coreboot may not boot on the first try. -* Disassemble your laptop and locate flash chip <http://flashrom.org/Technology> -is a great resource. The flash chip is usually in `SOIC-8` (2x4 pins) or `SOIC-16` -(2x8 chips). You'll probably have several candidates. Look up what's written on -them and look up what's this chip on the web. +Disassemble your computer and find the flash chip(s). Since there could be +more than one, this guide will refer to "flash chips" as one or more chips. +Refer to <http://flashrom.org/Technology> as a reference. The flash chip is +usually in a `SOIC-8` (2x4 pins, 200mil) or `SOIC-16` (2x8 pins) package. As +it can be seen on flashrom's wiki, the former package is like any other 8-pin +chip on the mainboard, but it is slightly larger. The latter package is much +easier to locate. Always make sure it is a flash chip by looking up what its +model, printed on it, refers to. -* Once you know what's the chip is, get an external flasher and read it. Twice. Compare -the results and retry if they differ. Save the result somewhere safe, in preference -copy it to read-only storage as backup. +There may be a smaller flash chip for the EC on some laptops, and other chips +such as network cards may use similar flash chips. These should be left as-is. +If in doubt, ask! -* Compile coreboot with console enabled (EHCI debug or serial if present are recommended) +Once located, use an external flasher to read the flash chips with `flashrom -r`. +Verify with `flashrom -v` several times that reading is consistent. If it is not, +troubleshoot your flashing setup. Save the results somewhere safe, preferably on +media that cannot be easily overwritten and on several devices. You may need this +later. The write process erases the flash chips first, and erased data on a flash +chip is lost for a very long time, usually forever! -* For recent Intel chipsets you need to avoid overwriting ME firmware. Recommended procedure is -(replace 8 with your flash size in MiB): +Compile coreboot for your ported mainboard with some console enabled. The most +common ones are EHCI debug, serial port and SPI flash console as a last resort. +If your system is a laptop and has a dedicated video card, you may need to add +a video BIOS (VBIOS) to coreboot to be able to see any video output. Desktop +video cards, as well as some MXM video cards, have this VBIOS on a flash chip +on the card's PCB, so this step is not necessary for them. - cp backup.rom flash.rom - dd if=coreboot/build/coreboot.rom skip=$[8-1] seek=$[8-1] bs=1M of=flash.rom +Flash coreboot on the machine. On recent Intel chipsets, the flash space is split +in several regions. Only the one known as "BIOS region" should be flashed. If +there is only one flash chip present, this is best done by adding the `--ifd` +and `-i bios` parameters flashrom has (from v1.0 onwards) to specify what flash +descriptor region it should operate on. If the ME (Management Engine) region is +not readable, which is the case on most systems, use the `--noverify-all` +parameter as well. -* Flash the result -* Boot and grab the log and fix the issues. See next section for useful info. -* grep your board for FIXME. autoport adds comments when it's unsure. Sometimes it's just -a minor check and sometimes it needs more involvment. See next section. -* Send new board to review.coreboot.org. I mean it, your effort is very appreciated. +For systems with two flash chips, this is not so easy. It is probably better to +ask in coreboot or flashrom communication channels, such as via IRC or on the +mailing lists. + +Once flashed, try to boot. Anything is possible. If a log is generated, save it +and use it to address any issues. See the next section for useful information. +Find all the sections marked with `FIXME` and correct them. + +Send your work to review.coreboot.org. I mean it, your effort is very appreciated. +Refer to Rookie Guide, Lesson 2 for instructions on how to submit a patch. ## Manual fixes ### SPD -If you're able to use full memory with any combination of inserted modules than this is -most likely correct. In order to initialize the memory coreboot needs to know RAM timings. -For socketed RAM it's stored in a small EEPROM chip which can be accessed through SPD. Unfortunately -mapping between SPD addresses and RAM slots differs and cannot always be detected automatically. -Resulting SPD map is encoded in function `mainboard_get_spd` in `romstage.c`. -autoport uses the most common map `0x50, 0x51, 0x52, 0x53` except for lenovos which are -known to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map the easiest way is with -vendor BIOS to boot with just one module in channel 0 slot 0 and then see where does it show -up in SPD. Under Linux you can see present SPD addresses with following commands: +In order to initialize the RAM memory, coreboot needs to know its timings, which vary between +modules. Socketed RAM has a small EEPROM chip, which is accessible via SMBus and contains the +timing data. This data is usually known as SPD. Unfortunately, the SMBus addresses may not +correlate with the RAM slots and cannot always be detected automatically. The address map is +encoded in function `mainboard_get_spd` in `romstage.c`. By default, autoport uses the most +common map `0x50, 0x51, 0x52, 0x53` on everything except for Lenovo systems, which are known +to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map, the easiest way is to boot +on the vendor firmware with just one module in channel 0, slot 0, and check the SMBus address +the EEPROM has. Under Linux, you can use these commands to see what is on SMBus: - phcoder@sid:~/coreboot/util/autoport$ sudo modprobe i2c-dev - phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect -l + $ sudo modprobe i2c-dev + $ sudo i2cdetect -l i2c-0 i2c i915 gmbus ssc I2C adapter i2c-1 i2c i915 gmbus vga I2C adapter i2c-2 i2c i915 gmbus panel I2C adapter @@ -98,7 +131,8 @@ i2c-7 i2c DPDDC-C I2C adapter i2c-8 i2c DPDDC-D I2C adapter i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter - phcoder@sid:~/coreboot/util/autoport$ sudo i2cdetect 9 + + $ sudo i2cdetect 9 WARNING! This program can confuse your I2C bus, cause data loss and worse! I will probe file /dev/i2c-9. I will probe address range 0x03-0x77. @@ -113,10 +147,11 @@ 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- -Make sure to replace `9` with whatever bus is marked as SMBus. Here in an example -you see SPD at address `0x50`. Since we've booted with just the module in C0S0, so -the first entry in SPD map has to be `0x50`. Once you have SPD map your -`mainboard_get_spd` should look something like: +Make sure to replace the `9` on the last command with the bus number for SMBus on +your system. Here, there is a module at address `0x50`. Since only one module was +installed on the first slot of the first channel, we know the first position of +the SPD array must be `0x50`. After testing all the slots, your `mainboard_get_spd` +should look similar to this: void mainboard_get_spd(spd_raw_data *spd) { read_spd (&spd[0], 0x50); @@ -125,18 +160,20 @@ read_spd (&spd[3], 0x53); } -You can and should omit lines which correspond to -slots not present on your machine. +Note that there should be one line per memory slot on the mainboard. Note: slot labelling may be missing or unreliable. Use `inteltool` to see which slots have modules in them. -This way works well if your RAM is socketed. For soldered RAM if you see -its SPD, you're in luck and can proceed the same way although you may have to -guess some entries due to RAM not being removable. +This procedure is ideal, if your RAM is socketed. If you have soldered RAM, +remove any socketed memory modules and check if any EEPROM appears on SMBus. +If this is the case, you can proceed as if the RAM was socketed. However, +you may have to guess some entries if there multiple EEPROMs appear. -Most cases of soldered RAM don't have EEPROM chip. In this case you'd have to create -fake SPD. Look in `inteltool.log`. You'll see something like: +Most of the time, soldered RAM does not have an EEPROM. Instead, the SPD data is +inside the main flash chip where the firmware is. If this is the case, you need +to generate the SPD data to use with coreboot. Look at `inteltool.log`. There +should be something like this: /* SPD matching current mode: */ /* CH0S0 */ @@ -174,12 +211,12 @@ e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -This is not completely exact represantation of RAM -capablities as it lists only the mode currently used -and lacks minor info like serial number. Using `xxd` -you can create binary represantation of this SPD: +This is not a full-fledged SPD dump, as it only lists +the currently-used speed configuration, and lacks info +such as a serial number, vendor and model. Use `xxd` +to create a binary file with this SPD data: - cat | xxd -r > spd.bin <<EOF + $ cat | xxd -r > spd.bin <<EOF 00: 92 11 0b 03 04 00 00 09 03 52 01 08 0a 00 80 00 10: 6e 78 6e 32 6e 11 18 81 20 08 3c 3c 00 f0 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -196,109 +233,114 @@ d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - EOF + EOF (press Ctrl + D) -Then you can place this file into mainboard directory -and hook it up into build system by adding following -lines to `Makefile.inc` (creating a new file if needed) +Then, move the generated file into your mainboard's directory +and hook it up to the build system by adding the following +lines to `Makefile.inc`: cbfs-files-y += spd.bin spd.bin-file := spd.bin spd.bin-type := raw -And then make coreboot actually use this SPD. Following -example shows a hybrid situation with one module -soldered and another is socketed: +Now we need coreboot to use this SPD file. The following example +shows a hybrid configuration, in which one module is soldered and +the other one is socketed: void mainboard_get_spd(spd_raw_data *spd) { void *spd_file; size_t spd_file_len = 0; - /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak( "spd.bin", CBFS_TYPE_RAW, + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_RAW, &spd_file_len); if (spd_file && spd_file_len >= 128) memcpy(&spd[0], spd_file, 128); - /* C0S0 is a DIMM slot. */ - read_spd(&spd[1], 0x51); + + /* C1S0 is a physical slot. */ + read_spd(&spd[2], 0x52); } -If several slots are soldered there are 3 ways of doing things: +If several slots are soldered there are two ways to handle them: -* If all of them are the same use the same file. Don't forget to copy -it to all array elements. -* Use several files (recommended). Name them e.g. spd1, spd2,... -* Concatenate it into a single file and split into several -array elements on runtime. Not recommended +* If all use the same SPD data, use the same file for all the slots. Do + not forget to copy the data on all the array elements that need it. +* If they use different data, use several files. ### `board_info.txt` -`board_info.txt` is a simple text file used to generate wiki page -listing supported boards. Some of the info can't be detected automatically. +`board_info.txt` is a text file used in the board status page to list all +the supported boards and their specifications. Most of the information +cannot be detected by autoport. Common entries are: -As this is used only to present information to users then when it matches -your board and definitions it is correct. +* `ROM package`, `ROM protocol` and `ROM socketed`: + These refer to the flash chips you found earlier. You can visit + <http://flashrom.org/Technology> for more information. -* Which package is used for ROM and whether it's socketed, as well -as release year. For ROM package refer to <http://flashrom.org/Technology> -and compare it with ROM you found at the beginning of the port. Set -`ROM package`, `ROM socketed` and other variables mentioned in FIXME. -* Release year, just go to web and find that information. -* Category. It's difficult to make difference between desktop and similar -categories from inside the computer. Valid categories are: - * `desktop`. Desktops and workstations. - * `server`. Servers - * `laptop`. Laptops. - * `half`. Embedded / PC/104 / Half-size boards. - * `mini`. Mini-ITX / Micro-ITX / Nano-ITX - * `settop`. Set-top-boxes / Thin clients. - * `eval`. Devel/Eval Boards - * `sbc`. Single-Board computer. - * `emulation`. Virtual machines and emulators. May require especial care - as they often behave differently from real counterparts. - * `misc`. Anything not fitting the categories above. You probably shouldn't use - this. +* `Release year`: Use the power of Internet to find that information. +* `Category`: This describes the type of mainboard you have. + Valid categories are: + * `desktop`. Desktops and workstations. + * `server`. Servers. + * `laptop`. Laptops, notebooks and netbooks. + * `half`. Embedded / PC/104 / Half-size boards. + * `mini`. Mini-ITX / Micro-ITX / Nano-ITX + * `settop`. Set-top-boxes / Thin clients. + * `eval`. Development / Evaluation Boards. + * `sbc`. Single-Board computer. + * `emulation`: Virtual machines and emulators. May require especial care + as they often behave differently from real counterparts. + * `misc`. Anything not fitting the categories above. Not recommended. + +* `Flashrom support`: This means whether the internal programmer is usable. + If flashing coreboot internally works, this should be set to `y`. Else, + feel free to investigate why it is not working. ### `USBDEBUG_HCD_INDEX` -Which controller the most easily accessible USB debug port is. On intel -1 is for `00:1d.0` and 2 is `00:1a.0` (yes, it's reversed). See +Which controller the most easily accessible USB debug port is. On Intel, +1 is for `00:1d.0` and 2 is for `00:1a.0` (yes, it's reversed). Refer to <https://www.coreboot.org/EHCI_Debug_Port> for more info. -If you're able to use EHCI debug port without setting HCD index manually -in config this is correct. +If you are able to use EHCI debug without setting the HCD index manually, +this is correct. ### `BOARD_ROMSIZE_KB_2048` -Default rom size should be detected automatically but sometimes isn't. -If yours weren't detected put correct rom size here to serve as sane -default when configuring coreboot. +This parameter refers to the total size of the flash chips coreboot will be in. +This value must be correct for S3 resume to work properly. This parameter also +defines the size of the generated coreboot image, but that is not a major issue +since tools like `dd` can be used to cut fragments of a coreboot image to flash +on smaller chips. -If default ROM size when slecting the board is right one than this value -is correct. +This should be detected automatically, but it may not be detected properly in +some cases. If it was not detected, put the correct total size here to serve +as a sane default when configuring coreboot. ### `DRAM_RESET_GATE_GPIO` -When machine is going to S3 in order not to reset the RAM modules, the -reset signal must be filtered out from reachin RAM. This is done by -powering down a special gate. Most manufacturers put this gate on -GPIO 60 but Lenovo is knowon to put it on GPIO 10. If you're able to -go to S3 and back than this value is correct. +When the computer is suspended to RAM (ACPI S3), the RAM reset signal must not +reach the RAM modules. Otherwise, the computer will not resume and any opened +programs will be lost. This is done by powering down a MOSFET, which disconnects +the reset signal from the RAM modules. Most manufacturers put this gate on GPIO +60 but Lenovo is known to put it on GPIO 10. If suspending and resuming works, +this value is correct. This can also be determined from the board's schematics. ## GNVS -`acpi_create_gnvs` sets values in GNVS which in turn is used by ACPI for -various power-related functions. Normally there is no need to modify it -but it makes sense to proofread it. +`acpi_create_gnvs` sets values in GNVS, which then ACPI makes use of for +various power-related functions. Normally, there is no need to modify it +on laptops (desktops have no "lid"!) but it makes sense to proofread it. ## `gfx.ndid` and `gfx.did` Those describe which video outputs are declared in ACPI tables. -Normally there is no need to adjust but if you miss some nonstandard output -you can declare it there. Bit 31 is set to indicate presence of the output. -Byte 1 is the type and byte 0 is used for disambigution so that ID composed of -byte 1 and 0 is unique. Types are +Normally, there is no need to adjust these values, but if you miss some +non-standard video output, you can declare it there. Bit 31 is set to +indicate the presence of the output. Byte 1 is the type and byte 0 is +used for disambigution so that ID composed of byte 1 and 0 is unique. +Types are: * 1 = VGA * 2 = TV * 3 = DVI @@ -306,22 +348,31 @@ ## `c*_acpower` and `c*_battery` -Which mwait states to match to which ACPI levels. Normally no need to modify unless -your device has very special power saving requirements. +Which mwait states to match to which ACPI levels. Normall, there is no +need to modify anything unless your device has very special power +saving requirements. ## `install_intel_vga_int15_handler` -This is used to configure int15 hook used by vgabios. Parameters 2 and 3 usually -shouldn't be modified as vgabios is quite ok to figure panel fit and active -output by itself. Last number is the numerical ID of display type. If you -don't get any output with vgabios you should try different values for 4th -parameter. If it doesn't help try different values for first parameter as well +This is used with the Intel VGA BIOS, which is not the default option. +It is more error-prone than open-source graphics initialization, so do +not bother with this until your mainboard boots. This is a function +which takes four parameters: +1. Which type of LCD panel is connected. +2. Panel fit. +3. Boot display. +4. Display type. + +Refer to `src/drivers/intel/gma/int15.h` to see which values can be used. +For desktops, there is no LCD panel directly connected to the Intel GPU, +so the first parameter should be `GMA_INT15_ACTIVE_LFP_NONE`. On other +mainboards, it depends. ## CMOS options -Due to horrible state of CMOS support in coreboot tree, autoport doesn't support it and -this probably won't change until format in the tree improves. If you really care about -CMOS options: +Due to the poor state of CMOS support in coreboot, autoport does not +support it and this probably won't change until the format in the tree +improves. If you really care about CMOS options: * Create files `cmos.layout` and `cmos.default` * Enable `HAVE_OPTION_TABLE` and `HAVE_CMOS_DEFAULT` in `Kconfig` @@ -355,9 +406,9 @@ ## EC (generic laptop) -Almost any laptop has an embedded controller. In nutshell it's a small -low-powered computer specialised on managing power for laptop. Exact -functionality differs between macines but of interest to us is mainly: +Almost any laptop has an embedded controller. In a nutshell, it's a +small, low-powered computer designed to be used on laptops. Exact +functionality differs between machines. Its main functions include: * Control of power and rfkill to different component * Keyboard (PS/2) interface implementation -- To view, visit https://review.coreboot.org/c/coreboot/+/30969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Gerrit-Change-Number: 30969 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/autoport: Trim gfx.did to size
by Angel Pons (Code Review) 18 Mar '19

18 Mar '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30963 Change subject: util/autoport: Trim gfx.did to size ...................................................................... util/autoport: Trim gfx.did to size Since the values are hardcoded, we might as well hardcode values that make sense. Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/30963/1 diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index cf2b859..79b0714 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -53,7 +53,7 @@ "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), /* FIXME:XX hardcoded. */ "gfx.ndid": "3", - "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410 }", }, Children: []DevTreeNode{ { -- To view, visit https://review.coreboot.org/c/coreboot/+/30963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Gerrit-Change-Number: 30963 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: mb/(ICH7): Do not try to rewrite on V1CAP register
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31004 Change subject: mb/(ICH7): Do not try to rewrite on V1CAP register ...................................................................... mb/(ICH7): Do not try to rewrite on V1CAP register V1CAP is a write-once register, and it is already programmd in intel/i945/early_init.c Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 7 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31004/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ad184a8..4e1fd96 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -143,8 +143,6 @@ { /* V0CTL Virtual Channel 0 Resource Control */ RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 471977f..6c5b441 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -146,7 +146,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9eaa8de..aa8878d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -124,7 +124,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 5e3535a..35213a9 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -48,7 +48,6 @@ { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* dev irq route register */ RCBA16(D31IR) = 0x0132; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3017357..f10f447 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6f66c88..1a2bc28 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -74,7 +74,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 6eceaeb..5dae395 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -75,7 +75,6 @@ { /* Set up virtual channel 0 */ RCBA32(V0CTL) = 0x80000001; - RCBA32(V1CAP) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; -- To view, visit https://review.coreboot.org/c/coreboot/+/31004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Gerrit-Change-Number: 31004 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Don't try to rewrite on SLOTCAP
by HAOUAS Elyes (Code Review) 18 Mar '19

18 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31036 Change subject: nb/intel/i945: Don't try to rewrite on SLOTCAP ...................................................................... nb/intel/i945: Don't try to rewrite on SLOTCAP SLOTCAP is R/WO, it becomes RO after the first write. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31036/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..15c3a33 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -719,9 +719,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Gerrit-Change-Number: 31036 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller
by Xiang Wang (Code Review) 18 Mar '19

18 Mar '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31059 Change subject: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller ...................................................................... src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller Initialize the clock of Gigabit Ethernet Controller and reset the PHY. Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/clock.c 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31059/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 17d1aef..4eb7d55 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -27,6 +27,7 @@ #include <symbols.h> #include <cbfs.h> #include <soc/otp.h> +#include <soc/addressmap.h> static void update_dtb(void) { @@ -52,6 +53,30 @@ OTHER_HLS(i)->fdt = (void *)dtb_target; } +static void nsleep(long nsec) +{ + long setp = 600; + while(*(volatile long*)&nsec > 0) + *(volatile long*)&nsec -= setp; +} + +#define GPIO_REG(n) (*(uint32_t*)(FU540_GPIO + (n))) +#define GPIO_OUTPUT_EN 0x08 +#define GPIO_OUTPUT_VAL 0x0c + +static void phy_init(void) +{ +#define PHY_NRESET 0x1000 + nsleep(2000000); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_EN), PHY_NRESET); + nsleep(100); + __sync_fetch_and_and(&GPIO_REG(GPIO_OUTPUT_VAL), ~PHY_NRESET); + nsleep(100); + __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); + nsleep(15000000); +} + void main(void) { console_init(); @@ -71,6 +96,7 @@ uart_init(CONFIG_UART_FOR_CONSOLE); sdram_init(); + phy_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 597b206..7194c3c 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -59,6 +59,8 @@ #define PRCI_DDRPLLCFG1_MASK (1u << 31) +#define PRCI_GEMGXLPPLCFG1_MASK (1u << 31) + #define PRCI_CORECLKSEL_CORECLKSEL 1 #define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0) @@ -141,6 +143,15 @@ .fse = 1, }; +static const struct pll_settings gemgxlpll_settings = { + .divr = 0, + .divf = 59, + .divq = 5, + .range = 4, + .bypass = 0, + .fse = 1, +}; + static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL @@ -168,6 +179,19 @@ write32(&prci->ddrpllcfg1, cfg1); } +static void init_gemgxlclk(void) +{ + u32 cfg1 = read32(&prci->gemgxlpllcfg1); + clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); + + configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings); + + setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + write32(&prci->gemgxlpllcfg1,cfg1); +} + + #define FU540_UART_DEVICES 2 #define FU540_UART_REG_DIV 0x18 #define FU540_UART_DIV_VAL 4 @@ -227,6 +251,17 @@ // device? for (int i = 0; i < 256; i++) asm volatile ("nop"); + + init_gemgxlclk(); + + write32(&prci->devicesresetreg, + PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) | + PRCI_DEVICESRESET_DDR_AXI_RST_N(1) | + PRCI_DEVICESRESET_DDR_AHB_RST_N(1) | + PRCI_DEVICESRESET_DDR_PHY_RST_N(1) | + PRCI_DEVICESRESET_GEMGXL_RST_N(1)); + + asm volatile ("fence"); } #endif /* ENV_ROMSTAGE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Gerrit-Change-Number: 31059 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP
by Maulik V Vaghela (Code Review) 18 Mar '19

18 Mar '19

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31285 to review the following change. Change subject: mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP ...................................................................... mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31285/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb index e30da3a..a810117 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -71,6 +71,27 @@ register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/31285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4 Gerrit-Change-Number: 31285 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

7 17

Change in ...coreboot[master]: mb/intel/coffeelake_rvp: Add cml_u board support
by Maulik V Vaghela (Code Review) 18 Mar '19

18 Mar '19

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31283 to review the following change. Change subject: mb/intel/coffeelake_rvp: Add cml_u board support ...................................................................... mb/intel/coffeelake_rvp: Add cml_u board support This patch selects CML SoC to build CMLRVP board. Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c 3 files changed, 11 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31283/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index d2d4b81..185d756 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -13,8 +13,8 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 @@ -28,10 +28,12 @@ default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 + default "cml_u" if BOARD_INTEL_COMETLAKE_RVP config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP default "cflrvp" config MAINBOARD_VENDOR @@ -41,6 +43,7 @@ config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP default "Intel_cflrvp" config CHROMEOS diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 70652ef..35c0f0f 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,3 +12,6 @@ config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE +config BOARD_INTEL_COMETLAKE_RVP + bool "-> Cometlake U DDR4 RVP" + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index fc35050..ed43317 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -264,7 +264,8 @@ /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) +#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) || \ + IS_ENABLED(CONFIG_BOARD_INTEL_COMETLAKE_RVP) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/31283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff Gerrit-Change-Number: 31283 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 12

Change in ...coreboot[master]: mb/intel/coffeelake_rvp/../cml_u: Do initial mainboard commit
by Maulik V Vaghela (Code Review) 18 Mar '19

18 Mar '19

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31281 to review the following change. Change subject: mb/intel/coffeelake_rvp/../cml_u: Do initial mainboard commit ...................................................................... mb/intel/coffeelake_rvp/../cml_u: Do initial mainboard commit Clone entirely from mainboard/intel/coffeelake_rvp/../whl_u commit id: 73916defba8d036c2536e1b37a1449ac16e5f56f Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h A src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h 3 files changed, 859 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31281/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb new file mode 100644 index 0000000..e30da3a --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -0,0 +1,138 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "ScsEmmcHs400Enabled" = "1" + register "HeciEnabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h new file mode 100644 index 0000000..c34a9b3 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h new file mode 100644 index 0000000..d821a26 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h @@ -0,0 +1,700 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC 700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 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0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18 Gerrit-Change-Number: 31281 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019