coreboot-gerrit February 2019

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: change speaker IV channels
by Jenny Tc (Code Review) 03 Apr '19

03 Apr '19

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31636 Change subject: mb/google/poppy/variant/nocturne: change speaker IV channels ...................................................................... mb/google/poppy/variant/nocturne: change speaker IV channels Change speaker IV channels for max98373 to match with 24 bit topology firmware BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31636/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4d9403c..5b84c96 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -403,16 +403,16 @@ end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" + register "vmon_slot_no" = "1" + register "imon_slot_no" = "0" register "uid" = "0" register "desc" = ""RIGHT SPEAKER AMP"" register "name" = ""MAXR"" device i2c 32 on end end chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" + register "vmon_slot_no" = "3" + register "imon_slot_no" = "2" register "uid" = "1" register "desc" = ""LEFT SPEAKER AMP"" register "name" = ""MAXL"" -- To view, visit https://review.coreboot.org/c/coreboot/+/31636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d94d473b25b23e206c998ca9bd8bd776b76d2bb Gerrit-Change-Number: 31636 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Little bit more helpful, giving back the lines for each file if any
by Balázs Vinarz (Code Review) 02 Apr '19

02 Apr '19

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30988 Change subject: Little bit more helpful, giving back the lines for each file if any ...................................................................... Little bit more helpful, giving back the lines for each file if any Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30988/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index f9b7891..b2011e7 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -20,7 +20,7 @@ # shellcheck disable=SC2086,SC2046 if uname | grep -qi "linux"; then - grep -l "[[:space:]][[:space:]]*$" \ + grep -n -H "[[:space:]][[:space:]]*$" \ $(git ls-files $INCLUDELIST | \ grep -Ev "($EXCLUDELIST)" ) | \ sed -e "s,^.*$,File & has lines ending with whitespace.," -- To view, visit https://review.coreboot.org/c/coreboot/+/30988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 Gerrit-Change-Number: 30988 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/spdtool: Add tool to extract SPD from BLOBs
by Patrick Rudolph (Code Review) 01 Apr '19

01 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31385 Change subject: util/spdtool: Add tool to extract SPD from BLOBs ...................................................................... util/spdtool: Add tool to extract SPD from BLOBs Opens a binary file to extract DDR SPDs using known bits. At the moment only DDR4 SPDs are supported. Dumps the found SPDs into the current folder, as either binary or hex encoded file. Works with python2 and python3. Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A util/spdtool/description.md A util/spdtool/spdtool.py 2 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31385/1 diff --git a/util/spdtool/description.md b/util/spdtool/description.md new file mode 100644 index 0000000..39d4a5c --- /dev/null +++ b/util/spdtool/description.md @@ -0,0 +1,3 @@ +Dumps SPD ROMs from a given blob to seperate files using known patterns +and reserved bits. Useful for analysing firmware that holds SPDs on boards +that have soldered down DRAM. `python` diff --git a/util/spdtool/spdtool.py b/util/spdtool/spdtool.py new file mode 100644 index 0000000..c20ee57 --- /dev/null +++ b/util/spdtool/spdtool.py @@ -0,0 +1,218 @@ +#!/usr/bin/env python + +# spdtool - Tool for partial deblobbing of Intel ME/TXE firmware images +# Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# Parse a BLOB and search for SPD files. +# First it is searched for a possible SPD header. +# +# For each candidate the function verify_match is invoked to check +# additional fields (known bits, reserved bits, CRC, ...) +# +# Dumps the found SPDs into the current folder. +# +# Implemented: +# DDR4 SPDs +# + +import argparse +import crc16 +import struct + +class Parser(object): + def __init__(self, blob, verbose=False, ignorecrc=False): + self.blob = blob + self.ignorecrc = ignorecrc + self.verbose = verbose + def get_matches(self): + """Return the first byte to look for""" + raise Exception("Function not implemented") + def verify_match(self, header, offset): + """Return true if it looks like a SPD""" + raise Exception("Function not implemented") + def get_len(self, header, offset): + """Return the length of the SPD""" + raise Exception("Function not implemented") + def get_part_number(self, offset): + """Return the part number in SPD""" + return "" + def get_manufacturer_id(self, offset): + """Return the manufacturer ID in SPD""" + return 0xffff + def get_mtransfers(self, offset): + """Return the number of MT/s""" + return 0 + + def get_manufacturer(self, offset): + """Return manufacturer as string""" + id = self.get_manufacturer_id(offset) + if id == 0xffff: + return "Unknown" + ids = { + 0x2c80: "Crucial/Micron", + 0x4304: "Ramaxel", + 0x4f01: "Transcend", + 0x9801: "Kingston", + 0x987f: "Hynix", + 0x9e02: "Corsair", + 0xb004: "OCZ", + 0xad80: "Hynix/Hyundai", + 0xb502: "SuperTalent", + 0xcd04: "GSkill", + 0xce80: "Samsung", + 0xfe02: "Elpida", + 0xff2c: "Micron", + } + if id in ids: + return ids[id] + return "Unknown" + + def blob_as_ord(self, offset): + """Helper for python2/python3 compability""" + return self.blob[offset] if type(self.blob[offset]) is int else ord(self.blob[offset]) + + def search(self, start): + """Search for SPD at start. Returns -1 on error or offset + if found. + """ + for i in self.get_matches(): + for offset in range(start, len(self.blob)): + if self.blob_as_ord(offset) != i: + continue + if not self.verify_match(i, offset): + continue + return offset, self.get_len(i, offset) + return -1, 0 + +class SPD4Parser(Parser): + def get_matches(self): + """Return DDR4 possible header candidates""" + ret = [] + for i in [1, 2, 3, 4]: + for j in [1, 2]: + ret.append(i + j * 16) + return ret + + def verify_match(self, header, offset): + """Verify DDR4 specific bit fields.""" + # offset 0 is a candidate, no need to validate + if self.blob_as_ord(offset + 1) == 0xff: + return False + if self.blob_as_ord(offset + 2) != 0x0c: + return False + if self.blob_as_ord(offset + 5) & 0xc0 > 0: + return False + if self.blob_as_ord(offset + 6) & 0xc > 0: + return False + if self.blob_as_ord(offset + 7) & 0xc0 > 0: + return False + if self.blob_as_ord(offset + 8) != 0: + return False + if self.blob_as_ord(offset + 9) & 0xf > 0: + return False + if self.verbose: + print("%x: Looks like DDR4 SPD" % offset) + + crc = crc16.crc16xmodem(self.blob[offset:offset + 0x7d + 1]) + # Vendors ignore the endianness... + crc_spd1 = self.blob_as_ord(offset + 0x7f) | (self.blob_as_ord(offset + 0x7e) << 8) + crc_spd2 = self.blob_as_ord(offset + 0x7e) | (self.blob_as_ord(offset + 0x7f) << 8) + if crc != crc_spd1 and crc != crc_spd2: + if self.verbose: + print("%x: CRC16 doesn't match" % offset) + if not self.ignorecrc: + return False + + return True + + def get_len(self, header, offset): + """Return the length of the SPD found.""" + if (header >> 4) & 7 == 1: + return 256 + if (header >> 4) & 7 == 2: + return 512 + return 0 + + def get_part_number(self, offset): + """Return part number as string""" + if offset + 0x15c > len(self.blob): + return "" + return self.blob[offset + 0x149:offset + 0x15c + 1].decode('utf-8').rstrip() + + def get_manufacturer_id(self, offset): + """Return manufacturer ID""" + if offset + 0x141 > len(self.blob): + return 0xffff + return struct.unpack('H', self.blob[offset + 0x140:offset + 0x141 + 1])[0] + + def get_mtransfers(self, offset): + """Return MT/s as specified by MTB and FTB""" + if offset + 0x7d > len(self.blob): + return 0 + + if self.blob_as_ord(offset + 0x11) != 0: + return 0 + mtb = 8.0 + ftb = 1000.0 + tckm = struct.unpack('B', self.blob[offset + 0x12:offset + 0x12 + 1])[0] + tckf = struct.unpack('b', self.blob[offset + 0x7d:offset + 0x7d + 1])[0] + return int(2000 / (tckm / mtb + tckf / ftb)) + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='SPD rom dumper') + parser.add_argument('--blob', required=True, + help='The ROM to search SPDs in.') + parser.add_argument('--spd4', action='store_true', default=False, + help='Search for DDR4 SPDs.') + parser.add_argument('--hex', action='store_true', default=False, + help='Store SPD in hex format otherwise binary.') + parser.add_argument('-v', '--verbose', help='increase output verbosity', + action='store_true') + parser.add_argument('--ignorecrc', help='Ignore CRC missmatch', + action='store_true', default=False) + args = parser.parse_args() + + blob = open(args.blob, "rb").read() + + if args.spd4: + p = SPD4Parser(blob, args.verbose, args.ignorecrc) + else: + raise Exception("Must specify one of the following arguments:\n--spd4") + + offset = 0 + length = 0 + cnt = 0 + while True: + offset, length = p.search(offset) + if length == 0: + break + print("Found SPD at 0x%x" % offset) + print(" '%s', size %d, manufacturer %s (0x%04x) %d MT/s\n" % + (p.get_part_number(offset), length, p.get_manufacturer(offset), + p.get_manufacturer_id(offset), p.get_mtransfers(offset))) + filename = "spd-%d-%s-%s.bin" % (cnt, p.get_part_number(offset), + p.get_manufacturer(offset)) + filename = filename.replace("/", "_") + filename = "".join([c for c in filename if c.isalpha() or c.isdigit() or c=='-' or c=='.' or c=='_']).rstrip() + if not args.hex: + open(filename, "wb").write(blob[offset:offset + length]) + else: + filename += ".hex" + fn = open(filename, "w") + j = 0 + for i in blob[offset:offset + length]: + fn.write("%02X%s" % (struct.unpack('B',i)[0], " " if j < 15 else "\n")) + j = (j + 1) % 16 + offset += 1 + cnt += 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c Gerrit-Change-Number: 31385 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing
by Patrick Georgi (Code Review) 27 Mar '19

27 Mar '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30964 Change subject: soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing ...................................................................... soc/qualcomm/qcs405: Define a Kconfig variable that the code is missing It's used in the code but never defined, which trips up the linter. We need to sort it out before the patch train gets in, but until then, the linter is mostly creating noise. Change-Id: Ib04d5b6d2cb03cc8ee6ef0275e1b201c0fc9eb6d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/qcs405/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30964/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index b24dc9e..ea1cee4 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -21,6 +21,13 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK +config QC_SDI_ENABLE + bool + default n + help + dummy entry because that variable isn't _really_ used yet. + todo(pgeorgi): check if used before merging + config QC_SOC_SIMULATE bool prompt "Build for Early Simulation Environment" -- To view, visit https://review.coreboot.org/c/coreboot/+/30964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib04d5b6d2cb03cc8ee6ef0275e1b201c0fc9eb6d Gerrit-Change-Number: 30964 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Move gfxinit into sub package
by Nico Huber (Code Review) 27 Mar '19

27 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31456 Change subject: drivers/intel/gma: Move gfxinit into sub package ...................................................................... drivers/intel/gma: Move gfxinit into sub package Move the actual graphics init provided by libgfxinit into a sub package `GMA.GFX_Init`. This way it can be compiled in individually. Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/Makefile.inc A src/drivers/intel/gma/gma-gfx_init.ads M src/drivers/intel/gma/gma.ads R src/drivers/intel/gma/hires_fb/gma-gfx_init.adb R src/drivers/intel/gma/text_fb/gma-gfx_init.adb 5 files changed, 48 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31456/1 diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index ebc688f..e128ad6 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -50,11 +50,13 @@ subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma.ads +ramstage-y += gma.ads + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma-gfx_init.adb else -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma-gfx_init.adb endif endif # CONFIG_GFX_GMA diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads new file mode 100644 index 0000000..7c96f9a --- /dev/null +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -0,0 +1,38 @@ +with Interfaces.C; + +with HW; +use HW; + +package GMA.GFX_Init +is + + procedure gfxinit (lightup_ok : out Interfaces.C.int); + pragma Export (C, gfxinit, "gma_gfxinit"); + + ---------------------------------------------------------------------------- + + type lb_framebuffer is record + tag : word32; + size : word32; + + physical_address : word64; + x_resolution : word32; + y_resolution : word32; + bytes_per_line : word32; + bits_per_pixel : word8; + red_mask_pos : word8; + red_mask_size : word8; + green_mask_pos : word8; + green_mask_size : word8; + blue_mask_pos : word8; + blue_mask_size : word8; + reserved_mask_pos : word8; + reserved_mask_size : word8; + end record; + + function fill_lb_framebuffer + (framebuffer : in out lb_framebuffer) + return Interfaces.C.int; + pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer"); + +end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads index 7286e7e..a6ce3a4 100644 --- a/src/drivers/intel/gma/gma.ads +++ b/src/drivers/intel/gma/gma.ads @@ -1,38 +1,2 @@ -with Interfaces.C; - -with HW; -use HW; - -package GMA -is - - procedure gfxinit (lightup_ok : out Interfaces.C.int); - pragma Export (C, gfxinit, "gma_gfxinit"); - - ---------------------------------------------------------------------------- - - type lb_framebuffer is record - tag : word32; - size : word32; - - physical_address : word64; - x_resolution : word32; - y_resolution : word32; - bytes_per_line : word32; - bits_per_pixel : word8; - red_mask_pos : word8; - red_mask_size : word8; - green_mask_pos : word8; - green_mask_size : word8; - blue_mask_pos : word8; - blue_mask_size : word8; - reserved_mask_pos : word8; - reserved_mask_size : word8; - end record; - - function fill_lb_framebuffer - (framebuffer : in out lb_framebuffer) - return Interfaces.C.int; - pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer"); - +package GMA is end GMA; diff --git a/src/drivers/intel/gma/hires_fb/gma.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb similarity index 98% rename from src/drivers/intel/gma/hires_fb/gma.adb rename to src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index e3553ca..1393784 100644 --- a/src/drivers/intel/gma/hires_fb/gma.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -13,7 +13,7 @@ with GMA.Mainboard; -package body GMA +package body GMA.GFX_Init is fb_valid : boolean := false; @@ -114,4 +114,4 @@ end if; end gfxinit; -end GMA; +end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/text_fb/gma.adb b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb similarity index 97% rename from src/drivers/intel/gma/text_fb/gma.adb rename to src/drivers/intel/gma/text_fb/gma-gfx_init.adb index 145b9a0..038b76b 100644 --- a/src/drivers/intel/gma/text_fb/gma.adb +++ b/src/drivers/intel/gma/text_fb/gma-gfx_init.adb @@ -8,7 +8,7 @@ with GMA.Mainboard; -package body GMA +package body GMA.GFX_Init is function fill_lb_framebuffer @@ -65,4 +65,4 @@ end if; end gfxinit; -end GMA; +end GMA.GFX_Init; -- To view, visit https://review.coreboot.org/c/coreboot/+/31456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Gerrit-Change-Number: 31456 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Make libgfxinit available w/o gfxinit
by Nico Huber (Code Review) 27 Mar '19

27 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31455 Change subject: drivers/intel/gma: Make libgfxinit available w/o gfxinit ...................................................................... drivers/intel/gma: Make libgfxinit available w/o gfxinit We might want to make use of libgfxinit functions without using it for actual graphics init. Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc 3 files changed, 19 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/31455/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index b90b15f..4e09c06 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -76,7 +76,6 @@ depends on MAINBOARD_HAS_LIBGFXINIT select HAVE_VGA_TEXT_FRAMEBUFFER select HAVE_LINEAR_FRAMEBUFFER - select RAMSTAGE_LIBHWBASE select VGA if VGA_TEXT_FRAMEBUFFER help Use the SPARK library `libgfxinit` for the native graphics diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index a5c8495..4f897fa 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -69,7 +69,20 @@ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE - depends on MAINBOARD_HAS_LIBGFXINIT + depends on MAINBOARD_USE_LIBGFXINIT + select RAMSTAGE_LIBHWBASE + +config GFX_GMA_INTERNAL_IS_EDP + bool + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + default n if GFX_GMA_INTERNAL_IS_LVDS + default y + +config GFX_GMA_INTERNAL_IS_LVDS + bool + depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM + default n if GFX_GMA @@ -89,16 +102,6 @@ default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL default "Normal" -config GFX_GMA_INTERNAL_IS_EDP - bool - default n if GFX_GMA_INTERNAL_IS_LVDS - default y - -config GFX_GMA_INTERNAL_IS_LVDS - bool - default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM - default n - config GFX_GMA_INTERNAL_PORT string default "DP" if GFX_GMA_INTERNAL_IS_EDP diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..ebc688f 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -33,7 +33,7 @@ $(call add_vbt_to_cbfs, vbt.bin, $(call strip_quotes,$(CONFIG_INTEL_GMA_VBT_FILE))) endif -ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) +ifeq ($(CONFIG_GFX_GMA),y) $(call add-special-class,gfxinit) gfxinit-handler = $(eval ramstage-srcs += $(1)$(2)) @@ -50,11 +50,11 @@ subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-y += gma.ads +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) -ramstage-y += hires_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma.adb else -ramstage-y += text_fb/gma.adb +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma.adb endif -endif # CONFIG_MAINBOARD_USE_LIBGFXINIT +endif # CONFIG_GFX_GMA -- To view, visit https://review.coreboot.org/c/coreboot/+/31455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Gerrit-Change-Number: 31455 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Add DP AUX channel control register bits
by Duncan Laurie (Code Review) 26 Mar '19

26 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31440 Change subject: soc/intel/common: Add DP AUX channel control register bits ...................................................................... soc/intel/common: Add DP AUX channel control register bits This change implements the SOC-specific function for providing the DP AUX channel control register bits. All of the recent Intel SOCs supported by soc/intel/common use the same format for this register. Change-Id: I95b75078f907da7df30bda2b3468668a2f0d7a47 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/drivers/intel/gma/i915_reg.h M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31440/1 diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index e0bf142..f32f0cd 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -2323,6 +2323,10 @@ #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +/* Used by Sky Lake and later SOC */ +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) + /* * Computing GMCH M and N values for the Display Port link * diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7..a8c93ec 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -20,6 +20,7 @@ #include <device/pci_ids.h> #include <intelblocks/graphics.h> #include <soc/pci_devs.h> +#include <drivers/intel/gma/i915.h> /* SoC Overrides */ __weak void graphics_soc_init(struct device *dev) @@ -96,11 +97,20 @@ graphics_gtt_write(reg, val); } +/* Return the SOC-specific bits of the AUX channel control register */ +uint32_t intel_dp_aux_ctl_soc(void) +{ + /* Currently all SOCs supported here use the gen9+ register format */ + return DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); +} + static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = graphics_soc_init, + .ops_i2c_bus = &intel_edp_aux_i2c_bus_ops, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95b75078f907da7df30bda2b3468668a2f0d7a47 Gerrit-Change-Number: 31440 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: drivers/intel/gma: Add DP AUX interface and I2C bus
by Duncan Laurie (Code Review) 26 Mar '19

26 Mar '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31439 Change subject: drivers/intel/gma: Add DP AUX interface and I2C bus ...................................................................... drivers/intel/gma: Add DP AUX interface and I2C bus In order to support reading the EDID of the internal panel this driver ports the kernel i915 Display Port AUX channel protocol and provides an I2C bus interface to it. A helper function is also provided for reading the EDID at the common I2C slave address. The bottom word of the AUX channel control register contains SOC-specific bits which are implemented for soc/intel/common in a subsequent commit. Change-Id: I4aa7e687aea397d6d70c0398e0f6958611db6410 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/drivers/intel/gma/i915.h A src/drivers/intel/gma/intel_dp_aux.c 4 files changed, 386 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/31439/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index a5c8495..63ca09f 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -32,6 +32,13 @@ bool default n +config INTEL_DP_AUX + bool + default n + help + Select this option to enable the AUX channel driver which provides + an I2C bus for reading the EDID from the eDP port. + config INTEL_GMA_SSC_ALTERNATE_REF bool default n diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..5a5fb8d 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +ramstage-$(CONFIG_INTEL_DP_AUX) += intel_dp_aux.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 0ddb2de..de56076 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -107,4 +107,53 @@ generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, struct device *dev, const char *idstr); +/* intel_dp_aux.c */ + +/** + * enum dp_aux_ch - Available AUX channels. + */ +enum dp_aux_ch { + AUX_CH_EDP, + AUX_CH_DDI1, + AUX_CH_DDI2, + AUX_CH_DDI3, +}; + +/** + * intel_dp_aux_ctl_soc() - Retrieve SOC specific bits for AUX control. + * + * Return: Mask of bits to set in AUX control register. + */ +uint32_t intel_dp_aux_ctl_soc(void); + +/** + * intel_dp_aux_ch() - Execute a DP AUX transaction. + * @dev: Graphics device. + * @aux_ch: Port for this transaction from %dp_aux_ch. + * @send_buf: Transmit data buffer. + * @send_bytes: Number of bytes to send. + * @recv_buf: Receive data buffer. + * @recv_size: Size of receive data buffer. + * + * Return: number of bytes received, or negative error code. + */ +ssize_t intel_dp_aux_ch(struct device *dev, enum dp_aux_ch aux_ch, + uint8_t *send_buf, size_t send_bytes, + uint8_t *recv_buf, size_t recv_size); + +/** + * intel_edp_aux_edid() - Read EDID from eDP AUX channel. + * @dev: Graphics device. + * @buf: Buffer to store EDID. + * @len: Size of provided buffer. + * + * Return: 0 to indicate success, negative error code on failure. + */ +int intel_edp_aux_edid(struct device *dev, uint8_t *buf, size_t len); + + +/* I2C controller for eDP AUX channel */ +struct i2c_bus_operations; +extern const struct i2c_bus_operations intel_edp_aux_i2c_bus_ops; + #endif diff --git a/src/drivers/intel/gma/intel_dp_aux.c b/src/drivers/intel/gma/intel_dp_aux.c new file mode 100644 index 0000000..906ce0e --- /dev/null +++ b/src/drivers/intel/gma/intel_dp_aux.c @@ -0,0 +1,329 @@ +/* + * Copyright 2008 Intel Corporation + * Copyright 2019 Google LLC + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Keith Packard <keithp(a)keithp.com> + */ + +/* + * This driver implements a Display Port AUX channel interface for the Intel + * i915 GPU. This work is based on the kernel i915 driver. There are SOC + * specific bits in part of the AUX channel control register, and this driver + * expects the SOC to implement a function to fill out those bits properly. + * + * An I2C controller driver is created that allows tunneling I2C traffic over + * the AUX channel for the eDP port. This allows reading the built-in panel + * EDID and a helper function is added to do that using the common EDID I2C + * slave address. + * + * The AUX channel interface does require the panel power to be enabled + * previously by coreboot or FSP. FSP will turn on the panel power it if + * the UPD for PanelPowerEnable is set (which is the default) or if the GOP + * driver is executed. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/i2c_bus.h> +#include <device/pci.h> +#include <device/resource.h> +#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/drm_dp_helper.h> +#include <stdint.h> +#include <string.h> +#include <timer.h> + +/** + * enum intel_dp_aux_info - Intel DP AUX driver information. + * @DP_AUX_RETRY: Number of retry attempts. Minimum in DP spec is 3. + * @DP_AUX_HEADER_SIZE: Number of bytes in transaction header. + * @DP_AUX_I2C_SLAVE_EDID: Common I2C slave address for EDID. + * @DP_AUX_SEND_BUSY_TIMEOUT: Time in milliseconds to wait for completion. + * @DP_AUX_DATA_REG_COUNT: Number of data registers in each channel. + * @DP_AUX_DATA_REG_SIZE: Total size of data registers including header. + * @DP_AUX_DATA_XFER_MAX: Maximum number of data bytes in a transaction. + */ +enum intel_dp_aux_info { + DP_AUX_RETRY = 5, + DP_AUX_HEADER_SIZE = 4, + DP_AUX_I2C_SLAVE_EDID = 0x50, + DP_AUX_SEND_BUSY_TIMEOUT_MS = 1000, + DP_AUX_DATA_REG_COUNT = 5, + DP_AUX_DATA_REG_SIZE = DP_AUX_DATA_REG_COUNT * sizeof(uint32_t), + DP_AUX_DATA_XFER_MAX = DP_AUX_DATA_REG_SIZE - DP_AUX_HEADER_SIZE, +}; + +/** + * enum intel_dp_aux_type - AUX channel transaction type. + * @AUX_TYPE_I2C_WRITE: I2C write transaction. + * @AUX_TYPE_I2C_READ: I2C read transaction. + */ +enum intel_dp_aux_type { + AUX_TYPE_I2C_WRITE, + AUX_TYPE_I2C_READ, +}; + +/* Map AUX channel to control register. */ +static uint32_t dp_aux_ch_ctl[] = { + [AUX_CH_EDP] = DPA_AUX_CH_CTL, + [AUX_CH_DDI1] = DPB_AUX_CH_CTL, + [AUX_CH_DDI2] = DPC_AUX_CH_CTL, + [AUX_CH_DDI3] = DPD_AUX_CH_CTL, +}; + +/* Map AUX channel to data register start. */ +static uint32_t dp_aux_ch_data[] = { + [AUX_CH_EDP] = DPA_AUX_CH_DATA1, + [AUX_CH_DDI1] = DPB_AUX_CH_DATA1, + [AUX_CH_DDI2] = DPC_AUX_CH_DATA1, + [AUX_CH_DDI3] = DPD_AUX_CH_DATA1, +}; + +/* Store the base address of the GMA region. */ +static uintptr_t base_address; + +__weak uint32_t intel_dp_aux_ctl_soc(void) +{ + return 0; +} + +static uint32_t i915_read32(uint32_t reg) +{ + return read32((void *)(base_address + reg)); +} + +static void i915_write32(uint32_t reg, uint32_t val) +{ + write32((void *)(base_address + reg), val); +} + +static uint32_t pack_aux(uint8_t *src, size_t src_bytes) +{ + uint32_t v = 0; + size_t i; + + if (src_bytes > 4) + src_bytes = 4; + for (i = 0; i < src_bytes; i++) + v |= ((uint32_t) src[i]) << ((3 - i) * 8); + return v; +} + +static void unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) +{ + size_t i; + + if (dst_bytes > 4) + dst_bytes = 4; + for (i = 0; i < dst_bytes; i++) + dst[i] = src >> ((3 - i) * 8); +} + +static int intel_dp_wait_busy(enum dp_aux_ch aux_ch) +{ + uint32_t status; + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, DP_AUX_SEND_BUSY_TIMEOUT_MS); + do { + status = i915_read32(dp_aux_ch_ctl[aux_ch]); + if (!(status & DP_AUX_CH_CTL_SEND_BUSY)) + break; + mdelay(1); + } while (!stopwatch_expired(&sw)); + + return status; +} + +ssize_t intel_dp_aux_ch(struct device *dev, enum dp_aux_ch aux_ch, + uint8_t *send_buf, size_t send_bytes, + uint8_t *recv_buf, size_t recv_size) +{ + size_t recv_bytes, try, i; + uint32_t status = 0; + + /* Initialize base address */ + if (!base_address) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + base_address = (uintptr_t)res->base; + } + + /* Try to wait for any previous AUX channel activity */ + for (try = 0; try < DP_AUX_RETRY; try++) { + status = intel_dp_wait_busy(aux_ch); + if (!(status & DP_AUX_CH_CTL_SEND_BUSY)) + break; + } + if (try == DP_AUX_RETRY) { + printk(BIOS_DEBUG, "%s: not started status 0x%08x\n", + __func__, status); + return -1; + } + + /* Must try at least 3 times according to DP spec */ + for (try = 0; try < DP_AUX_RETRY; try++) { + /* Load the send data into the aux channel data registers */ + for (i = 0; i < send_bytes; i += 4) + i915_write32(dp_aux_ch_data[aux_ch] + i, + pack_aux(send_buf + i, send_bytes - i)); + + /* Send the command and wait for it to complete */ + i915_write32(dp_aux_ch_ctl[aux_ch], + intel_dp_aux_ctl_soc() | /* SOC specific bits */ + DP_AUX_CH_CTL_SEND_BUSY | + DP_AUX_CH_CTL_TIME_OUT_1600us | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR | + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)); + + status = intel_dp_wait_busy(aux_ch); + if (status & DP_AUX_CH_CTL_SEND_BUSY) + continue; + + /* Clear done status and any errors */ + i915_write32(dp_aux_ch_ctl[aux_ch], + status | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR); + + if (status & DP_AUX_CH_CTL_DONE) + break; + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) + udelay(500); + } + + if ((status & DP_AUX_CH_CTL_DONE) == 0) { + printk(BIOS_DEBUG, "%s: not done status 0x%08x\n", + __func__, status); + return -1; + } + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { + printk(BIOS_DEBUG, "%s: receive error status 0x%08x\n", + __func__, status); + return -1; + } + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { + printk(BIOS_DEBUG, "%s: timeout status 0x%08x\n", + __func__, status); + return -1; + } + + /* Unload any bytes sent back from the other side */ + recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + if (recv_bytes > recv_size) + recv_bytes = recv_size; + + for (i = 0; i < recv_bytes; i += 4) + unpack_aux(i915_read32(dp_aux_ch_data[aux_ch] + i), + recv_buf + i, recv_bytes - i); + + return recv_bytes; +} + +static ssize_t intel_dp_aux_i2c_transfer(struct device *dev, + enum dp_aux_ch aux_ch, + const struct i2c_msg *msg, + size_t offset, size_t len) +{ + uint8_t txbuf[DP_AUX_DATA_REG_SIZE] = {}; + uint8_t rxbuf[DP_AUX_DATA_REG_SIZE] = {}; + uint8_t type; + size_t txsize, rxsize; + ssize_t bytes; + + if (!len) + return -1; + + if (msg->flags & I2C_M_RD) { + type = AUX_TYPE_I2C_READ; + txsize = DP_AUX_HEADER_SIZE; + rxsize = len + 1; + } else { + type = AUX_TYPE_I2C_WRITE; + txsize = DP_AUX_HEADER_SIZE + len; + rxsize = 2; + memcpy(txbuf + DP_AUX_HEADER_SIZE, msg->buf + offset, len); + } + + /* Fill DP AUX header */ + txbuf[0] = (type << 4) | ((msg->slave >> 16) & 0xf); + txbuf[1] = (msg->slave >> 8) & 0xff; + txbuf[2] = msg->slave & 0xff; + txbuf[3] = len - 1; + + bytes = intel_dp_aux_ch(dev, aux_ch, txbuf, txsize, rxbuf, rxsize); + if (bytes > 0 && msg->flags & I2C_M_RD) + memcpy(msg->buf + offset, rxbuf + 1, bytes - 1); + + return bytes; +} + +static int intel_edp_aux_i2c(struct device *dev, const struct i2c_msg *msg, + size_t count) +{ + /* Split different messages into separate transactions */ + while (count--) { + size_t offset = 0; + + /* Split into chunks to fit in available data registers */ + while (offset < msg->len) { + size_t txlen = MIN(msg->len - offset, + DP_AUX_DATA_XFER_MAX); + + if (intel_dp_aux_i2c_transfer(dev, AUX_CH_EDP, + msg, offset, txlen) < 0) + return -1; + + offset += txlen; + } + msg++; + } + return 0; +} + +const struct i2c_bus_operations intel_edp_aux_i2c_bus_ops = { + .transfer = intel_edp_aux_i2c +}; + +int intel_edp_aux_edid(struct device *dev, uint8_t *buf, size_t len) +{ + uint8_t start = 0; + struct i2c_msg msgs[] = { + { + .slave = DP_AUX_I2C_SLAVE_EDID, + .len = sizeof(start), + .buf = &start + }, { + .slave = DP_AUX_I2C_SLAVE_EDID, + .flags = I2C_M_RD, + .len = len, + .buf = buf + } + }; + + return intel_edp_aux_i2c(dev, msgs, ARRAY_SIZE(msgs)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa7e687aea397d6d70c0398e0f6958611db6410 Gerrit-Change-Number: 31439 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: crossgcc: Update CMake to version 3.13.4
by HAOUAS Elyes (Code Review) 22 Mar '19

22 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31240 Change subject: crossgcc: Update CMake to version 3.13.4 ...................................................................... crossgcc: Update CMake to version 3.13.4 Change-Id: I9fec45429d80500d80cc6b774718ecc91720f3f2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.13.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.13.4.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31240/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c19b766..df37ce1 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=7.0.1 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.13.3 +CMAKE_VERSION=3.13.4 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/cmake-3.13.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.13.3.tar.gz.cksum deleted file mode 100644 index 9ebd7f5..0000000 --- a/util/crossgcc/sum/cmake-3.13.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -f33558a268a9286d4fa310abbd56efbaf897f6dc tarballs/cmake-3.13.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.13.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.13.4.tar.gz.cksum new file mode 100644 index 0000000..4fbcee8 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.13.4.tar.gz.cksum @@ -0,0 +1 @@ +242ac4986ab38ddb06c7bfb7eb950e4c1b1ca770 tarballs/cmake-3.13.4.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/31240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fec45429d80500d80cc6b774718ecc91720f3f2 Gerrit-Change-Number: 31240 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: vboot: standardize on working data size
by Joel Kitching (Code Review) 21 Mar '19

21 Mar '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31474 Change subject: vboot: standardize on working data size ...................................................................... vboot: standardize on working data size Previously, the size of memory made for vb2_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL creates a new Kconfig option called VBOOT_WORKING_DATA_SIZE, which is tied to the value provided by vboot2 as VB2_WORKBUF_RECOMMENDED_DATA_SIZE via a _Static_assert in vboot_loader.c BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/arch/x86/car.ld M src/include/memlayout.h M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/vboot_loader.c M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/imgtec/pistachio/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld 18 files changed, 40 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31474/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6fe8f14..b8d8c03 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -26,11 +26,11 @@ . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif - /* Vboot work buffer is completely volatile outside of verstage and - * romstage. Appropriate code needs to handle the transition. */ -#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE) - VBOOT2_WORK(., 16K) -#endif + /* Vboot work buffer only needs to be available when verified boot + * starts in bootblock. */ +#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) + VBOOT2_WORK(.) + #endif /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..4fa1802 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -160,9 +160,8 @@ /* Careful: required work buffer size depends on RW properties such as key size * and algorithm -- what works for you might stop working after an update. Do * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); +#define VBOOT2_WORK(addr) \ + REGION(vboot2_work, addr, CONFIG_VBOOT_WORKING_DATA_SIZE, 16) #if ENV_VERSTAGE #define VERSTAGE(addr, sz) \ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a3e9b86..1b34c91 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -92,6 +92,13 @@ memory initialization). This implies that vboot working data is allocated in CBMEM. +config VBOOT_WORKING_DATA_SIZE + int + default 12288 # 12K, must match VB2_WORKBUF_RECOMMENDED_SIZE + help + Size in bytes that should be allocated for verified boot's working + data structure. + config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 6c63f7b..d1e2fe4 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -22,7 +22,13 @@ verstage-y += bootmode.c postcar-y += bootmode.c -verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +# When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by the time +# verstage runs. +ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) +verstage-generic-ccopts += -D__PRE_RAM__ +endif + +verstage-generic-ccopts += -D__VERSTAGE__ ramstage-y += gbb.c diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 747644a..c3d065e 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -40,25 +40,16 @@ uint32_t buffer_size; }; -static const size_t vb_work_buf_size = 16 * KiB; - static struct vb2_working_data * const vboot_get_working_data(void) { if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) /* cbmem_add() does a cbmem_find() first. */ - return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, vb_work_buf_size); + return cbmem_add(CBMEM_ID_VBOOT_WORKBUF, + CONFIG_VBOOT_WORKING_DATA_SIZE); else return (struct vb2_working_data *)_vboot2_work; } -static size_t vb2_working_data_size(void) -{ - if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) - return vb_work_buf_size; - else - return _vboot2_work_size; -} - static struct selected_region *vb2_selected_region(void) { struct selected_region *sel_reg = NULL; @@ -86,19 +77,17 @@ void vb2_init_work_context(struct vb2_context *ctx) { struct vb2_working_data *wd; - size_t work_size; /* First initialize the working data region. */ - work_size = vb2_working_data_size(); wd = vboot_get_working_data(); - memset(wd, 0, work_size); + memset(wd, 0, CONFIG_VBOOT_WORKING_DATA_SIZE); /* * vboot prefers 16-byte alignment. This takes away 16 bytes * from the VBOOT2_WORK region, but the vboot devs said that's okay. */ wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = work_size - wd->buffer_offset; + wd->buffer_size = CONFIG_VBOOT_WORKING_DATA_SIZE - wd->buffer_offset; /* Initialize the vb2_context. */ memset(ctx, 0, sizeof(*ctx)); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 75f75b5..7b0b8d8 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -22,6 +22,7 @@ #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> +#include <vb2_api.h> /* Ensure vboot configuration is valid: */ _Static_assert(IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) + @@ -33,6 +34,8 @@ _Static_assert(!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE) || IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); +_Static_assert(CONFIG_VBOOT_WORKING_DATA_SIZE == VB2_WORKBUF_RECOMMENDED_SIZE, + "working data size must be set to VB2_WORKBUF_RECOMMENDED_SIZE"); /* The stage loading code is compiled and entered from multiple stages. The * helper functions below attempt to provide more clarity on when certain diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 2222617..ab47f1f 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,7 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x30000) VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 05042ef..e0a92cf8 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -45,7 +45,7 @@ SRAM_START(0x1a000000) REGION(gram_bootblock, 0x1a000000, 28K, 1) ROMSTAGE(0x1a007000, 60K) - VBOOT2_WORK(0x1a016000, 12K) + VBOOT2_WORK(0x1a016000) PRERAM_CBFS_CACHE(0x1a019000, 48K) SRAM_END(0x1a066000) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 5b92153..3705ca1 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -38,7 +38,7 @@ SRAM_L2C_END(0x00100000) SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) + VBOOT2_WORK(0x00100000) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index a547083..4d065c7 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -28,7 +28,7 @@ SECTIONS { SRAM_START(0x00100000) - VBOOT2_WORK(0x00100000, 12K) + VBOOT2_WORK(0x00100000) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 615f0563..9907afe 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,7 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32) PRERAM_CBFS_CACHE(0x40006000, 16K) - VBOOT2_WORK(0x4000A000, 16K) + VBOOT2_WORK(0x4000A000) STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 30K) VERSTAGE(0x40017800, 72K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index d807c06..1521431 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,7 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 4K) PRERAM_CBFS_CACHE(0x40001000, 36K) - VBOOT2_WORK(0x4000A000, 12K) + VBOOT2_WORK(0x4000A000) #if ENV_ARM64 STACK(0x4000D000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 5e97077..59281cc 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -46,7 +46,7 @@ REGION_START(wifi_imem_1, 0x0A8C0000) BOOTBLOCK(0x0A8C0000, 24K) OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K) - VBOOT2_WORK(0x0A8D6000, 16K) + VBOOT2_WORK(0x0A8D6000) PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K) TIMESTAMP(0x0A8E2000, 1K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 6ff2b77..8ecd924 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -27,7 +27,7 @@ /* DDR(0x2A000000, 48K) */ BOOTBLOCK(0x2A00C000, 24K) OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) - VBOOT2_WORK(0x2A022000, 16K) + VBOOT2_WORK(0x2A022000) PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) TIMESTAMP(0x2A02E000, 1K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 5d99a8e..7a6394e 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -35,7 +35,7 @@ REGION(fw_reserved2, 0x14800000, 0x16000, 4096) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) - VBOOT2_WORK(0x1482E000, 16K) + VBOOT2_WORK(0x1482E000) STACK(0x14832000, 16K) TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 6320fad..de957d5 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -32,7 +32,7 @@ TTB(0xFF700000, 16K) BOOTBLOCK(0xFF704004, 20K - 4) PRERAM_CBMEM_CONSOLE(0xFF709000, 2K) - VBOOT2_WORK(0xFF709800, 12K) + VBOOT2_WORK(0xFF709800) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) PRERAM_CBFS_CACHE(0xFF717000, 1K) TIMESTAMP(0xFF717400, 0x180) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 01e352f..a3581a8 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -35,7 +35,7 @@ /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) BOOTBLOCK(0xFF8D8000, 40K) - VBOOT2_WORK(0XFF8E2000, 12K) + VBOOT2_WORK(0XFF8E2000) TTB(0xFF8E5000, 24K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 4daf2b9..9bdf105 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -32,7 +32,7 @@ /* 32K hole */ TTB(0x2058000, 16K) PRERAM_CBFS_CACHE(0x205C000, 80K) - VBOOT2_WORK(0x2070000, 16K) + VBOOT2_WORK(0x2070000) STACK(0x2074000, 16K) SRAM_END(0x2078000) -- To view, visit https://review.coreboot.org/c/coreboot/+/31474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Gerrit-Change-Number: 31474 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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