coreboot-gerrit February 2019

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Change in ...coreboot[master]: mb/ocp/monolake: add TPM and IPMI support
by Łukasz Siudut (Code Review) 24 Apr '19

24 Apr '19

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31525 Change subject: mb/ocp/monolake: add TPM and IPMI support ...................................................................... mb/ocp/monolake: add TPM and IPMI support Changes includes: - enabled TPM1 + added entry in devicetree - configured LPC IO to make IPMI work + added entry in devicetree - introduced DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut(a)fb.com> Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/monolake/romstage.c 5 files changed, 153 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31525/1 diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 76ecb48..2315ec6 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -11,6 +11,11 @@ select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_IFD_GBE_REGION + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + +config INTEGRATED_UART + def_bool n config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 30d99c2..2d91b73 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -7,7 +7,14 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip drivers/generic/generic # BMC KCS + device pnp ca2.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller device pci 1f.5 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 1248703..72b1c3c 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,6 +27,9 @@ { #include "acpi/platform.asl" + Name (IDTP, 0x0CA2) + Name (ICDP, 0x0CA6) + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -290,5 +293,97 @@ } } + Scope (_SB.PCI0.LPC0) + { + Device (SPMI) + { + Name (_HID, EisaId ("IPI0001")) + Name (_STR, Unicode ("IPMI_KCS")) + Name (_UID, 0x00) + OperationRegion (IPST, SystemIO, ICDP, 0x01) + Field (IPST, ByteAcc, NoLock, Preserve) + { + STAS, 8 + } + Method (_STA, 0, NotSerialized) { + Return (0x0f) + } + Name (ICRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y01) + IO (Decode16, + 0x0000, + 0x0000, + 0x00, + 0x00, + _Y02) + + }) + Method (_CRS, 0, NotSerialized) + { + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) + CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) + CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) + + IPDB = IDTP + IPDH = IDTP + IPDL = 0x01 + + IPCB = ICDP + IPCH = ICDP + IPCL = 0x01 + + Return (ICRS) + } + Method (_IFT, 0, NotSerialized) { + Return (0x01) + } + Method(_SRV, 0, NotSerialized) { + Return (0x0200) + } + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, + 0x0CA2, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA6, + 0x0CA6, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CA8, + 0x0CA8, + 0x01, + 0x01, + ) + IO (Decode16, + 0x0CAC, + 0x0CAC, + 0x01, + 0x01, + ) + }) + } + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index f1a3a20..934b757 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -15,17 +15,52 @@ */ #include <device/device.h> +#include <smbios.h> + #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#define BMC_KCS_BASE 0xca2 +#define INTERFACE_IS_IO 0x1 + +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address + 0x40, + 0); // no IRQ + + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif + /* Enable access to the BMC IPMI via KCS */ + struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); + struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + res->base = BMC_KCS_BASE; + res->size = 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index cf52c01..58b2d17 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -17,6 +17,8 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <soc/pci_devs.h> +#include <soc/lpc.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +26,14 @@ */ void early_mainboard_romstage_entry(void) { - + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC, + 0x0c0681); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, + 0x0c0ca1); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, + 0xfc0201); + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN4_DEC, + 0xfc0601); } /** @@ -33,7 +42,6 @@ */ void late_mainboard_romstage_entry(void) { - } /** @@ -41,5 +49,4 @@ */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - } -- To view, visit https://review.coreboot.org/c/coreboot/+/31525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f9fb17b9f1349272080e032991fe45a443a9d84 Gerrit-Change-Number: 31525 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() function
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31432 Change subject: cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() function ...................................................................... cpu/intel/speedstep/acpi: Use get_ia32_fsb_x3() function Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/speedstep/acpi.c 1 file changed, 7 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31432/1 diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index b5e2c9e9..7bc67ff 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -21,6 +21,7 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/intel/fsb.h> #include <cpu/intel/speedstep.h> #include <device/device.h> #include <string.h> @@ -41,29 +42,6 @@ return count; } -/** - * @brief Returns three times the FSB clock in MHz - * - * The result of calculations with the returned value shall be divided by 3. - * This helps to avoid rounding errors. - */ -static int get_fsb(void) -{ - const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7; - switch (fsbcode) { - case 0: return 800; /* / 3 == 266 */ - case 1: return 400; /* / 3 == 133 */ - case 2: return 600; /* / 3 == 200 */ - case 3: return 500; /* / 3 == 166 */ - case 4: return 1000; /* / 3 == 333 */ - case 5: return 300; /* / 3 == 100 */ - case 6: return 1200; /* / 3 == 400 */ - } - printk(BIOS_WARNING, - "Warning: No supported FSB frequency. Assuming 200MHz\n"); - return 600; -} - static void gen_pstate_entries(const sst_table_t *const pstates, const int cpuID, const int cores_per_package, const uint8_t coordination) @@ -76,7 +54,12 @@ cpuID, cores_per_package, coordination); acpigen_write_name("_PSS"); - const int fsb3 = get_fsb(); + int fsb3 = get_ia32_fsb_x3(); + if (fsb3 <= 0) { + printk(BIOS_ERR, "CPU or FSB not supported. Assuming 200MHz\n"); + fsb3 = 600; + } + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( pstates->states[pstates->num_states - 1]); const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/31432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8c5d5f7dd5b43becc144fd5e62d7de2f1ed3b80 Gerrit-Change-Number: 31432 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: nb/intel/i945: Check if interleaved even if rank[4] size is zero
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31007 Change subject: nb/intel/i945: Check if interleaved even if rank[4] size is zero ...................................................................... nb/intel/i945: Check if interleaved even if rank[4] size is zero With this patch, the board can boot when interleaved but rank4 is 0. Tested on 945G-M4, it boot when: DIMM0 + DIMM2 populated: Ok DIMM0 + DIMM3 populated: Ok DIMM1 + DIMM2 populated: Ok DIMM1 + DIMM3 populated: Ok raminit.c still needs channelA populated. It will not boot if channel A is not populated. Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/31007/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..a46677b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2551,9 +2551,6 @@ u32 bankaddr = 0, tmpaddr, mrsaddr = 0; for (i = 0, nonzero = -1; i < 8; i++) { - if (sysinfo->banksize[i] == 0) - continue; - printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); switch (i) { case 0: @@ -2576,6 +2573,9 @@ bankaddr = 0; } + if (sysinfo->banksize[i] == 0) + continue; + /* We have a bank with a non-zero size.. Remember it * for the next offset we have to calculate */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf130a3d4b6f8fa816f7a5f06822a9b8807be3d4 Gerrit-Change-Number: 31007 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 17

Change in ...coreboot[master]: soc/amd/common: Remove AmdReadEventLog()
by Kyösti Mälkki (Code Review) 23 Apr '19

23 Apr '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31484 Change subject: soc/amd/common: Remove AmdReadEventLog() ...................................................................... soc/amd/common: Remove AmdReadEventLog() Parameter passing is incorrect here, it should pass complete StdHeader instead of attempting to fill in HeapStatus that should be treated as a field private to AGESA, based on where it is defined in the header files. Furthermore the while() loop did not evaluate the return value. Feature can be brought back at a later date after someone verifies it actually works correctly across different stages. Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 0 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31484/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 1726955..fb33f4d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -42,34 +42,6 @@ static void *AcpiIvrs; static void *AcpiCrat; -static AGESA_STATUS agesawrapper_readeventlog(uint8_t HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams = { - .StdHeader.CalloutPtr = &GetBiosCallout, - .StdHeader.HeapStatus = HeapStatus, - }; - - Status = AmdReadEventLog(&AmdEventParams); - if (AmdEventParams.EventClass) - printk(BIOS_DEBUG, "AGESA Event Log:\n"); - - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, " Class = %x, Info = %x," - " Param1 = 0x%x, Param2 = 0x%x" - " Param3 = 0x%x, Param4 = 0x%x\n", - (u32)AmdEventParams.EventClass, - (u32)AmdEventParams.EventInfo, - (u32)AmdEventParams.DataParam1, - (u32)AmdEventParams.DataParam2, - (u32)AmdEventParams.DataParam3, - (u32)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} - static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) { /* Should clone entire StdHeader here. */ @@ -108,8 +80,6 @@ status = AmdInitReset(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -131,8 +101,6 @@ status = AmdInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -219,8 +187,6 @@ print_init_post_settings(PostParams); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(PostParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -243,8 +209,6 @@ status = AmdInitEnv(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -296,8 +260,6 @@ status = AmdInitMid(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -328,11 +290,6 @@ Status = AmdInitLate(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(LateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - DmiTable = LateParams->DmiTable; AcpiPstate = LateParams->AcpiPState; @@ -372,11 +329,6 @@ Status = AmdInitRtb(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - if (save_s3_info(RtbParams->S3DataBlock.NvStorage, RtbParams->S3DataBlock.NvStorageSize, RtbParams->S3DataBlock.VolatileStorage, @@ -406,8 +358,6 @@ status = AmdInitResume(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); - if (status != AGESA_SUCCESS) - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -436,10 +386,6 @@ Status = AmdS3LateRestore(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } AmdReleaseStruct(&AmdParamStruct); return Status; @@ -466,10 +412,6 @@ Status = AmdS3FinalRestore(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); - if (Status != AGESA_SUCCESS) { - agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } AmdReleaseStruct(&AmdParamStruct); return Status; diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index c42df59..2efee4e 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -226,17 +226,3 @@ if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(AmdApExeParams); } - -/********************************************************************** - * Interface service call: AmdReadEventLog - **********************************************************************/ -AGESA_STATUS -AmdReadEventLog ( - IN EVENT_PARAMS *Event -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - Event->StdHeader.Func = AMD_READ_EVENT_LOG; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(Event); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Gerrit-Change-Number: 31484 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: soc/amd/common: Introduce agesa_execute_state()
by Kyösti Mälkki (Code Review) 23 Apr '19

23 Apr '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31483 Change subject: soc/amd/common: Introduce agesa_execute_state() ...................................................................... soc/amd/common: Introduce agesa_execute_state() Each entrypoint to AGESA goes through the same sequence and have same the function signature. To avoid introducing bunch of preprocessor magic, rename all the agesawrapper_amdXXX() functions that are actual entrypoints to AGESA API, make them static, and provide a single exposed entry function agesa_execute_state(). Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c 8 files changed, 76 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31483/1 diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 2f3b8a6..04db424 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -34,22 +34,11 @@ /* Return current dispatcher or NULL on error. */ MODULE_ENTRY agesa_get_dispatcher(void); +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func); AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams); -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdinitrtb(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amds3finalrestore(void); -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); void amd_initcpuio(void); diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 1188f05..86e32af 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -42,11 +42,11 @@ return statusStrings[sret]; } -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) +static inline u32 do_agesawrapper(AGESA_STRUCT_NAME func, const char *name) { AGESA_STATUS ret; printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); + ret = agesa_execute_state(func); printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", name, decodeAGESA_STATUS(ret)); return (u32)ret; diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index fc69b46..1726955 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2018 Kyösti Mälkki + * Copyright (C) 2018 - 2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -89,7 +89,7 @@ return interface_struct->NewStructPtr; } -AGESA_STATUS agesawrapper_amdinitreset(void) +static AGESA_STATUS amd_init_reset(void) { AGESA_STATUS status; AMD_RESET_PARAMS _ResetParams; @@ -114,7 +114,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitearly(void) +static AGESA_STATUS amd_init_early(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -171,7 +171,7 @@ uma_size / MiB, uma_start); } -AGESA_STATUS agesawrapper_amdinitpost(void) +static AGESA_STATUS amd_init_post(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -226,7 +226,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitenv(void) +static AGESA_STATUS amd_init_env(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -276,7 +276,7 @@ } } -AGESA_STATUS agesawrapper_amdinitmid(void) +static AGESA_STATUS amd_init_mid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -303,7 +303,7 @@ return status; } -AGESA_STATUS agesawrapper_amdinitlate(void) +static AGESA_STATUS amd_init_late(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -358,7 +358,7 @@ return AmdLateRunApTask(ApExeParams); } -AGESA_STATUS agesawrapper_amdinitrtb(void) +static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -388,7 +388,7 @@ return Status; } -AGESA_STATUS agesawrapper_amdinitresume(void) +static AGESA_STATUS amd_init_resume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct = { @@ -413,7 +413,7 @@ return status; } -AGESA_STATUS agesawrapper_amds3laterestore(void) +static AGESA_STATUS amd_s3late_restore(void) { AGESA_STATUS Status; AMD_S3LATE_PARAMS _S3LateParams; @@ -445,7 +445,7 @@ return Status; } -AGESA_STATUS agesawrapper_amds3finalrestore(void) +static AGESA_STATUS amd_s3final_restore(void) { AGESA_STATUS Status; AMD_S3FINAL_PARAMS _S3FinalParams; @@ -474,3 +474,55 @@ return Status; } + +static AGESA_STATUS romstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + switch (StdHeader->Func) { + case AMD_INIT_RESET: + return amd_init_reset(); + case AMD_INIT_EARLY: + return amd_init_early(); + case AMD_INIT_POST: + return amd_init_post(); + case AMD_INIT_RESUME: + return amd_init_resume(); + default: + return AGESA_UNSUPPORTED; + } +} + +static AGESA_STATUS ramstage_dispatch(AMD_CONFIG_PARAMS *StdHeader) +{ + switch (StdHeader->Func) { + case AMD_INIT_ENV: + return amd_init_env(); + case AMD_INIT_MID: + return amd_init_mid(); + case AMD_INIT_LATE: + return amd_init_late(); + case AMD_INIT_RTB: + return amd_init_rtb(); + case AMD_S3LATE_RESTORE: + return amd_s3late_restore(); + case AMD_S3FINAL_RESTORE: + return amd_s3final_restore(); + default: + return AGESA_UNSUPPORTED; + } +} + +AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) +{ + AGESA_STATUS status = AGESA_UNSUPPORTED; + AMD_CONFIG_PARAMS template = {}; + AMD_CONFIG_PARAMS *StdHeader = &template; + + StdHeader->Func = func; + + if (ENV_ROMSTAGE) + status = romstage_dispatch(StdHeader); + if (ENV_RAMSTAGE) + status = ramstage_dispatch(StdHeader); + + return status; +} diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 68cf3a1..81d42b7 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -178,12 +178,12 @@ if (acpi_is_wakeup_s3()) return; - do_agesawrapper(agesawrapper_amdinitlate, "amdinitlate"); + do_agesawrapper(AMD_INIT_LATE, "amdinitlate"); if (!acpi_s3_resume_allowed()) return; - do_agesawrapper(agesawrapper_amdinitrtb, "amdinitrtb"); + do_agesawrapper(AMD_INIT_RTB, "amdinitrtb"); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index a282665..363ba83 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -18,7 +18,7 @@ static void agesawrapper_s3finalrestore(void *unused) { - do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore"); + do_agesawrapper(AMD_S3FINAL_RESTORE, "amds3finalrestore"); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index a29c56c..0ecd3e9 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -163,12 +163,11 @@ psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2"); post_code(0x47); - do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv"); + do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ post_code(0x46); - do_agesawrapper(agesawrapper_amds3laterestore, - "amds3laterestore"); + do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4a856a9..c10920f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -391,7 +391,7 @@ { /* Must be called after PCI enumeration and resource allocation */ if (!romstage_handoff_is_resume()) - do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid"); + do_agesawrapper(AMD_INIT_MID, "amdinitmid"); } void domain_set_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 9f8aed8..2769dfe 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -65,11 +65,11 @@ static void agesa_call(void) { post_code(0x37); - do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); + do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); post_code(0x38); /* APs will not exit amdinitearly */ - do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); + do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } static void bsp_agesa_call(void) @@ -102,7 +102,7 @@ if (!s3_resume) { post_code(0x40); - do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); + do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); /* @@ -137,7 +137,7 @@ } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(agesawrapper_amdinitresume, "amdinitresume"); + do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893 Gerrit-Change-Number: 31483 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: crossgcc: Update acpica to version 20190215
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31443 Change subject: crossgcc: Update acpica to version 20190215 ...................................................................... crossgcc: Update acpica to version 20190215 0) Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190215_iasl.patch D util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum 5 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/31443/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a83302d..b5dd435 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -71,7 +71,7 @@ */ #define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */ -#define ASL_REVISION 20190108 +#define ASL_REVISION 20190215 /* List of ACPI HID that use the coreboot ACPI ID */ enum coreboot_acpi_ids { diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 019b011..c6d7986 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 -IASL_VERSION=20190108 +IASL_VERSION=20190215 PYTHON_VERSION=3.7.2 EXPAT_VERSION=2.2.6 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch similarity index 84% rename from util/crossgcc/patches/acpica-unix2-20190108_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190215_iasl.patch index 6532255..c4f6052 100644 --- a/util/crossgcc/patches/acpica-unix2-20190108_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190215_iasl.patch @@ -1,4 +1,4 @@ -diff -Naur acpica-unix2-20190108_/source/compiler/asloptions.c acpica-unix2-20190108/source/compiler/asloptions.c > acpica-unix2-20190108_iasl.patch +diff -Naur acpica-unix2-20190215_/source/compiler/asloptions.c acpica-unix2-20190215/source/compiler/asloptions.c > acpica-unix2-20190215_iasl.patch --- acpica-unix2-20190108_/source/compiler/asloptions.c +++ acpica-unix2-20190108/source/compiler/asloptions.c @@ -126,6 +126,7 @@ diff --git a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum deleted file mode 100644 index c5cfb4c..0000000 --- a/util/crossgcc/sum/acpica-unix2-20190108.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50d96dd38b89c69260ad209cf61035cda1fcdd67 tarballs/acpica-unix2-20190108.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum new file mode 100644 index 0000000..310454d --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190215.tar.gz.cksum @@ -0,0 +1 @@ +82d729cb09edc50ee11669651683ca5a5c0f4d5a tarballs/acpica-unix2-20190215.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/31443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Gerrit-Change-Number: 31443 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 16

Change in ...coreboot[master]: crossgcc: Upgrade GCC to version 8.3.0
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31598 Change subject: crossgcc: Upgrade GCC to version 8.3.0 ...................................................................... crossgcc: Upgrade GCC to version 8.3.0 Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-8.3.0_gnat.patch R util/crossgcc/patches/gcc-8.3.0_libgcc.patch R util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch D util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 7 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31598/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c19b766..5536d87 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -50,7 +50,7 @@ GMP_VERSION=6.1.2 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 -GCC_VERSION=8.2.0 +GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 diff --git a/util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_ada-musl_workaround.patch rename to util/crossgcc/patches/gcc-8.3.0_ada-musl_workaround.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_gnat.patch b/util/crossgcc/patches/gcc-8.3.0_gnat.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_gnat.patch rename to util/crossgcc/patches/gcc-8.3.0_gnat.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_libgcc.patch b/util/crossgcc/patches/gcc-8.3.0_libgcc.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_libgcc.patch rename to util/crossgcc/patches/gcc-8.3.0_libgcc.patch diff --git a/util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch b/util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch similarity index 100% rename from util/crossgcc/patches/gcc-8.2.0_nds32_ite.patch rename to util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch diff --git a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum deleted file mode 100644 index 1ef301a..0000000 --- a/util/crossgcc/sum/gcc-8.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -19926bdb6c4b58891015929853d41aeff019d400 tarballs/gcc-8.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum new file mode 100644 index 0000000..b46ef8c --- /dev/null +++ b/util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum @@ -0,0 +1 @@ +c27f4499dd263fe4fb01bcc5565917f3698583b2 tarballs/gcc-8.3.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/31598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Gerrit-Change-Number: 31598 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: sb/intel/i82801gx/lpc: Use macros instead of magic numbers
by HAOUAS Elyes (Code Review) 23 Apr '19

23 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31310 Change subject: sb/intel/i82801gx/lpc: Use macros instead of magic numbers ...................................................................... sb/intel/i82801gx/lpc: Use macros instead of magic numbers Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/lpc.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31310/1 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7497c79..25e5ec7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -259,12 +259,12 @@ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = inl(pmbase + PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP - reg32 |= (1 << 1); // enable C3->C0 transition on bus master - reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + reg32 |= BM_RLD; // enable C3->C0 transition on bus master + reg32 |= SCI_EN; + outl(reg32, pmbase + PM1_CNT); } static void i82801gx_configure_cstates(struct device *dev) @@ -489,11 +489,11 @@ fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x20; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x28; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; fadt->gpe1_blk = 0; fadt->pm1_evt_len = 4; @@ -531,7 +531,7 @@ fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 0; @@ -545,21 +545,21 @@ fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Gerrit-Change-Number: 31310 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: google/kukui: Support I2C TPM and stop supporting SPI TPM
by You-Cheng Syu (Code Review) 23 Apr '19

23 Apr '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30978 Change subject: google/kukui: Support I2C TPM and stop supporting SPI TPM ...................................................................... google/kukui: Support I2C TPM and stop supporting SPI TPM Kukui TPM is going to move from SPI to I2C. This CL makes coreboot supports I2C TPM on Kukui. To make things easier, SPI TPM on Kukui is no longer supported. BRANCH=none BUG=b:117916698 TEST=none Change-Id: I194de167aa946d592ba20cff15f076739e5cc096 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/verstage.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30978/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 7635e5f..5de6b5b 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -35,7 +35,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI - select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR @@ -47,9 +47,13 @@ default "Kukui" if BOARD_GOOGLE_KUKUI default "Flapjack" if BOARD_GOOGLE_FLAPJACK -config DRIVER_TPM_SPI_BUS +config DRIVER_TPM_I2C_BUS hex - default 0x0 + default 0x6 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/kukui/verstage.c b/src/mainboard/google/kukui/verstage.c index 9bf93bf..f80fcc1 100644 --- a/src/mainboard/google/kukui/verstage.c +++ b/src/mainboard/google/kukui/verstage.c @@ -15,12 +15,12 @@ #include <security/vboot/vboot_common.h> #include <soc/gpio.h> -#include <soc/spi.h> +#include <soc/i2c.h> #include "gpio.h" void verstage_mainboard_init(void) { - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I194de167aa946d592ba20cff15f076739e5cc096 Gerrit-Change-Number: 30978 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Set basename for FSP binaries
by Felix Singer (Code Review) 21 Apr '19

21 Apr '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30930 Change subject: drivers/intel/fsp2_0: Set basename for FSP binaries ...................................................................... drivers/intel/fsp2_0: Set basename for FSP binaries Since there is no standardized naming scheme for the FSP binaries, the option USE_FSP_REPO can't be used on some platforms, because the output filenames differ and the build process awaits "Fsp_*.fd" as filename. As a workaround, add the option -n to SplitFspBin.py, which defines the basename. Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/30930/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..1d1bae7 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/c/coreboot/+/30930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Gerrit-Change-Number: 30930 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019