coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/gma: Choose better default settings for HSW
by Nico Huber (Code Review) 12 May '19

12 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31465 Change subject: drivers/intel/gma: Choose better default settings for HSW ...................................................................... drivers/intel/gma: Choose better default settings for HSW When libgfxinit was added, there were no Haswell boards in the tree with discrete CPU/PCH. There are now, and we have a Kconfig to distingush them. So use that instead of mainboard overrides. TEST=Built config for asrock/h81m-hds and checked that GFX_GMA_CPU_VARIANT is still set to `Normal`. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig 2 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31465/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2dbed01..fd2422d 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -105,7 +105,7 @@ default "ULT" if ((SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEY_LAKE) \ && !SOC_INTEL_CANNONLAKE_PCH_H) \ || ((SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE) && !SKYLAKE_SOC_PCH_H) \ - || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL + || SOC_INTEL_BROADWELL || (NORTHBRIDGE_INTEL_HASWELL && INTEL_LYNXPOINT_LP) default "Normal" config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index 55f1637..f2ba55c 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -40,14 +40,6 @@ hex default 0x200000 -# -# The override of GFX_GMA_CPU_VARIANT should be removed once the patches -# for dynamic CPU detection are merged in libgfxinit. -# -config GFX_GMA_CPU_VARIANT - string - default "Normal" - config MAINBOARD_DIR string default asrock/h81m-hds -- To view, visit https://review.coreboot.org/c/coreboot/+/31465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Gerrit-Change-Number: 31465 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/nami: Add VBT blobs and include them in cbfs
by Arthur Heymans (Code Review) 10 May '19

10 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30427 Change subject: mb/google/nami: Add VBT blobs and include them in cbfs ...................................................................... mb/google/nami: Add VBT blobs and include them in cbfs Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc R src/mainboard/google/poppy/variants/nami/akali-data.vbt A src/mainboard/google/poppy/variants/nami/data.vbt A src/mainboard/google/poppy/variants/nami/patheon-data.vbt A src/mainboard/google/poppy/variants/nami/vayne-data.vbt 5 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30427/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 7f86bb7..8f4ef0c 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -41,3 +41,15 @@ cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, akali-data.vbt, akali-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, vayne-data.vbt, vayne-vbt.bin) +$(call add_vbt_to_cbfs, data.vbt, vbt.bin) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000..8406362 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/patheon-data.vbt b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Gerrit-Change-Number: 30427 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0); /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2); /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Gerrit-Change-Number: 31027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable options for wakeup
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30447 Change subject: soc/intel/cannonlake: Enable options for wakeup ...................................................................... soc/intel/cannonlake: Enable options for wakeup Cannonlake FSP silicon init have dedicated wake up capability settings for several IP, expose the selection into coreboot. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..e5a3ae1 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -302,6 +302,13 @@ /* SATA Power Optimizer */ uint8_t satapwroptimize; + + /* Wake Up Capability */ + uint8_t codec_wake_sx; + uint8_t pcie_wake_deepsx; + uint8_t wlan_wake_sx; + uint8_t wlan_wake_deepsx; + uint8_t glan_wake_deepsx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9..9a24242 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -225,6 +225,14 @@ /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + + /* Wakeup Capability */ + params->PchHdaCodecSxWakeCapability = config->codec_wake_sx; + params->PchPmWoWlanEnable = config->wlan_wake_sx; + params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx; + params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx; + params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx; + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06 Gerrit-Change-Number: 30447 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31419 Change subject: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size ...................................................................... src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size The default 0xc00 size of pre-CBMEM console is too small to fit whole console log from romstage. Increase the size in order to avoid log truncation when checking console with cbmem utility. The size was adjusted by compiling and running the coreboot on apu2 with SPEW loglevel. Additionally unset the SQUELCH_EARLY_SMP option to get console output between amdinitreset and amdinitearly. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31419/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6e65a6e..3c04b05 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -113,4 +113,16 @@ int default 128 +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x3000 + help + Increase this value if preram cbmem console is getting truncated + +config SQUELCH_EARLY_SMP + bool + default n + help + When selected only the BSP CPU will output to early console. + endif # BOARD_PCENGINES_APU2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 Gerrit-Change-Number: 31419 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Add panel config data for display
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31590 Change subject: google/kukui: Add panel config data for display ...................................................................... google/kukui: Add panel config data for display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31590/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 950dca4..bf9bd02 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -15,9 +15,12 @@ #include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <edid.h> +#include <gpio.h> #include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> @@ -42,13 +45,66 @@ setup_usb_host(); } +/* Setup backlight control pins as output pin and power-off by default */ +static void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +static void configure_display(void) +{ + /* board from p0 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); +} + +static const struct edid kukui_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +struct lcm_init_table lcm_init_cmd[] = { + {INIT_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON}}, + {DELAY_CMD, 120, {}}, +}; + + static void display_startup(void) { + int ret = 0; + u32 mipi_dsi_flags; struct edid edid; + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } mtk_ddp_mode_set(&edid); @@ -62,6 +118,8 @@ mtcmos_display_power_on(); mtcmos_protect_display_bus(); + configure_backlight(); + configure_display(); display_startup(); } else { printk(BIOS_INFO, "Skipping display init.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Gerrit-Change-Number: 31590 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Add Sunrise Point LP (Skylake) IDs
by Felix Singer (Code Review) 06 May '19

06 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31506 Change subject: util/inteltool: Add Sunrise Point LP (Skylake) IDs ...................................................................... util/inteltool: Add Sunrise Point LP (Skylake) IDs Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/31506/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 93a7ffe..bdcee02 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -224,11 +224,19 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point Mobile Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1, "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2, + "Sunrise Point-LP U Base" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1, "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2, + "Sunrise Point-LP U Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1, + "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2, "Sunrise Point-LP Y Premium" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, "Sunrise Point-LP U iHDCP 2.2 Base" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fb64811..9fbe9b5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -144,10 +144,14 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2 0x9d58 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2 0x9d56 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b -- To view, visit https://review.coreboot.org/c/coreboot/+/31506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Gerrit-Change-Number: 31506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/common: Introduce module_dispatch()
by Kyösti Mälkki (Code Review) 06 May '19

06 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31485 Change subject: soc/amd/common: Introduce module_dispatch() ...................................................................... soc/amd/common: Introduce module_dispatch() This change removes all the separate entrypoint dispatch functions as they all share the same pattern. Furthermore, none of the function definitions under vendorcode binaryPI/AGESA.c file have proper declarations, the ones compiler picks up from AGESA.h are for the internal implementations and with sanely organized headerfiles would not be exposed outside the build of AGESA at all. Change-Id: I0b72badc007565740c93b58743cfd048e8b42775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 2 files changed, 39 insertions(+), 170 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31485/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index fb33f4d..f09fc5d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -42,8 +42,34 @@ static void *AcpiIvrs; static void *AcpiCrat; +static AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, + AMD_CONFIG_PARAMS *StdHeader) +{ + MODULE_ENTRY dispatcher = agesa_get_dispatcher(); + + if (!dispatcher) + return AGESA_UNSUPPORTED; + + StdHeader->Func = func; + return dispatcher(StdHeader); +} + +static AGESA_STATUS amd_dispatch(void *Params) +{ + AMD_CONFIG_PARAMS *StdHeader = Params; + return module_dispatch(StdHeader->Func, StdHeader); +} + +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) +{ + AMD_CONFIG_PARAMS *StdHeader = (void *)ApExeParams; + return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); +} + static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) { + AMD_CONFIG_PARAMS *StdHeader; + /* Should clone entire StdHeader here. */ interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; @@ -58,7 +84,9 @@ if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ die("No AGESA structure created"); - return interface_struct->NewStructPtr; + StdHeader = interface_struct->NewStructPtr; + StdHeader->Func = interface_struct->AgesaFunctionName; + return StdHeader; } static AGESA_STATUS amd_init_reset(void) @@ -77,7 +105,7 @@ SetFchResetParams(&ResetParams->FchInterface); timestamp_add_now(TS_AGESA_INIT_RESET_START); - status = AmdInitReset(ResetParams); + status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -98,7 +126,7 @@ OemCustomizeInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_START); - status = AmdInitEarly(EarlyParams); + status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -163,7 +191,7 @@ ); timestamp_add_now(TS_AGESA_INIT_POST_START); - status = AmdInitPost(PostParams); + status = amd_dispatch(PostParams); timestamp_add_now(TS_AGESA_INIT_POST_DONE); /* @@ -206,7 +234,7 @@ SetNbEnvParams(&EnvParams->GnbEnvConfiguration); timestamp_add_now(TS_AGESA_INIT_ENV_START); - status = AmdInitEnv(EnvParams); + status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -257,7 +285,7 @@ SetNbMidParams(&MidParams->GnbMidConfiguration); timestamp_add_now(TS_AGESA_INIT_MID_START); - status = AmdInitMid(MidParams); + status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -287,7 +315,7 @@ } timestamp_add_now(TS_AGESA_INIT_LATE_START); - Status = AmdInitLate(LateParams); + Status = amd_dispatch(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); DmiTable = LateParams->DmiTable; @@ -310,11 +338,6 @@ return Status; } -AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) -{ - return AmdLateRunApTask(ApExeParams); -} - static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; @@ -326,7 +349,7 @@ AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); timestamp_add_now(TS_AGESA_INIT_RTB_START); - Status = AmdInitRtb(RtbParams); + Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); if (save_s3_info(RtbParams->S3DataBlock.NvStorage, @@ -355,7 +378,7 @@ InitResumeParams->S3DataBlock.NvStorageSize = nv_size; timestamp_add_now(TS_AGESA_INIT_RESUME_START); - status = AmdInitResume(InitResumeParams); + status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -383,7 +406,7 @@ S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_LATE_START); - Status = AmdS3LateRestore(S3LateParams); + Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -409,7 +432,7 @@ S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_FINAL_START); - Status = AmdS3FinalRestore(S3FinalParams); + Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); AmdReleaseStruct(&AmdParamStruct); diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index 2efee4e..e17cedc 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -72,157 +72,3 @@ if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(InterfaceParams); } - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3FinalRestore - **********************************************************************/ -AGESA_STATUS -AmdS3FinalRestore ( - IN OUT AMD_S3FINAL_PARAMS *S3FinalParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3FinalParams->StdHeader.Func = AMD_S3FINAL_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3FinalParams); -} - -/********************************************************************** - * Interface call: AmdInitRtb - **********************************************************************/ -AGESA_STATUS -AmdInitRtb ( - IN OUT AMD_RTB_PARAMS *AmdInitRtbParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdInitRtbParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdApExeParams); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/31485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b72badc007565740c93b58743cfd048e8b42775 Gerrit-Change-Number: 31485 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: inteltool: Skylake GPIOs #2
by Felix Singer (Code Review) 05 May '19

05 May '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31660 Change subject: inteltool: Skylake GPIOs #2 ...................................................................... inteltool: Skylake GPIOs #2 Used Intel documents: - 332995-001EN - 332996-002EN Change-Id: Ic006d9c094f9fe1ad419cb0168ada45b7dd81732 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31660/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index a87ae35..52eae09 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1027,6 +1027,9 @@ case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_DNV_LPC: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index d61438b..5abb570 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -908,6 +908,9 @@ communities = sunrise_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_1: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_1: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_2: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_2: -- To view, visit https://review.coreboot.org/c/coreboot/+/31660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic006d9c094f9fe1ad419cb0168ada45b7dd81732 Gerrit-Change-Number: 31660 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variant/atlas: enable USB acpi
by Gaggery Tsai (Code Review) 03 May '19

03 May '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30754 Change subject: mb/google/poppy/variant/atlas: enable USB acpi ...................................................................... mb/google/poppy/variant/atlas: enable USB acpi Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:122540489 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat & retrieve ssdt.dat from DUT & $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio" under _DSD object Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30754/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 59abe72..197986d 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -150,6 +150,7 @@ select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index f8a6e6d..97c10b0 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -268,7 +268,30 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/30754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Gerrit-Change-Number: 30754 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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