coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: postcarpayload: Boot to payload from postcar stage directly [WIP]
by Subrata Banik (Code Review) 12 Jun '19

12 Jun '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30985 Change subject: postcarpayload: Boot to payload from postcar stage directly [WIP] ...................................................................... postcarpayload: Boot to payload from postcar stage directly [WIP] Changes: 1. Make only required changes to load generic payload [payload_init.c] 2. Compile required functions in postcar stage 3. Call postcar_payload_init() from postcar stage 4. soc and mainboard related changes TEST=Able to boot iclrvp and dragonegg to chrome os with limited FW changes. Change-Id: I27479187461ceb078167f2d726f40839865a9233 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/acpi.c M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/commonlib/Makefile.inc M src/console/post.c M src/cpu/intel/microcode/Makefile.inc M src/cpu/intel/turbo/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/mp_init.c M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/name/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/device/Makefile.inc M src/device/pci_early.c M src/drivers/elog/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/gma/Makefile.inc M src/drivers/mrc_cache/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/drivers/pc80/pc/Makefile.inc M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/ec/google/chromeec/Makefile.inc M src/include/memlayout.h M src/include/mrc_cache.h M src/include/rules.h M src/include/stddef.h M src/lib/Makefile.inc M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/mainboard/google/dragonegg/Kconfig M src/mainboard/google/dragonegg/Makefile.inc M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb M src/mainboard/intel/icelake_rvp/Kconfig M src/security/vboot/Makefile.inc M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/graphics/Makefile.inc M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/itss/Makefile.inc M src/soc/intel/common/block/lpc/Makefile.inc M src/soc/intel/common/block/pcr/Makefile.inc M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c A src/soc/intel/icelake/include/soc/payload_init.h A src/soc/intel/icelake/payload_init.c M src/southbridge/intel/common/Makefile.inc M src/vendorcode/google/chromeos/Makefile.inc 67 files changed, 477 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30985/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8dafac8..2ee4921 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -260,6 +260,11 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi_pld.c postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += gdt_init.S @@ -270,6 +275,7 @@ postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S +postcar-y += c_start.S postcar-y += memcpy.c postcar-y += memmove.c postcar-y += memset.c @@ -310,11 +316,13 @@ ramstage-y += c_start.S ramstage-y += cbmem.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S ramstage-y += gdt.c +postcar-$(CONFIG_IOAPIC) += ioapic.c ramstage-$(CONFIG_IOAPIC) += ioapic.c ramstage-y += memcpy.c ramstage-y += memlayout.ld @@ -327,10 +335,13 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +postcar-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c +postcar-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3b33f1b..e8c7cb4 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -48,6 +48,9 @@ #include <cpu/cpu.h> #include <cbfs.h> +#include <soc/pci_devs.h> +#include <intelblocks/graphics.h> + u8 acpi_checksum(u8 *table, u32 length) { u8 ret = 0; @@ -1264,6 +1267,7 @@ printk(BIOS_DEBUG, "current = %lx\n", current); +#if 0 // TODO: Bad hack to enable GFX for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { current = dev->ops->write_acpi_tables(dev, current, @@ -1271,6 +1275,9 @@ current = acpi_align_current(current); } } +#endif + graphics_soc_write_acpi_opregion(SA_DEV_IGD, current, rsdp); + current = acpi_align_current(current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 86147ec..5bb3cfd 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -37,8 +37,8 @@ #else .code32 #endif - .globl _start -_start: + .globl _start1 +_start1: cli lgdt %cs:gdtaddr #ifndef __x86_64__ diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 018ce9e..d9d0762 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -227,15 +227,11 @@ * from secondary cpus to a minimum, when debugging is * disabled. */ - struct device *cpu; - struct cpu_info *info; + struct device *cpu = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct cpuinfo_x86 c; - info = cpu_info(); - printk(BIOS_INFO, "Initializing CPU #%d\n", index); - cpu = info->cpu; if (!cpu) die("CPU: missing CPU device structure"); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index a061a27..7ddda19 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -837,7 +837,7 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if (ENV_RAMSTAGE || ENV_POSTCAR) && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3ee5cea..b10b984 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -210,7 +210,7 @@ ); return ci; } - +#if !ENV_POSTCAR static inline unsigned long cpu_index(void) { struct cpu_info *ci; @@ -218,6 +218,7 @@ return ci->index; } #endif +#endif #ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..da02d6b 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <soc/payload_init.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -37,6 +38,8 @@ display_mtrrs(); + postcar_payload_init(); + /* Load and run ramstage. */ run_ramstage(); } diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 4d89c48..3d68cb4 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -23,6 +23,8 @@ ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c +postcar-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c + bootblock-y += cbfs.c verstage-y += cbfs.c romstage-y += cbfs.c diff --git a/src/console/post.c b/src/console/post.c index 4c37535..50c84df 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -41,7 +41,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void cmos_post_log(void) { u8 code = 0; diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..cdef0e0 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c +postcar-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc index 48ec55d..6a62f59 100644 --- a/src/cpu/intel/turbo/Makefile.inc +++ b/src/cpu/intel/turbo/Makefile.inc @@ -1 +1,2 @@ +postcar-y += turbo.c ramstage-y += turbo.c diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a664..639d1f8 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,9 +6,11 @@ subdirs-y += pae subdirs-$(CONFIG_PARALLEL_MP) += name +postcar-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c ramstage-y += backup_default_smm.c +postcar-y += backup_default_smm.c additional-dirs += $(obj)/cpu/x86 @@ -19,6 +21,7 @@ ifeq ($(CONFIG_PARALLEL_MP),y) ramstage-srcs += $(SIPI_BIN).manual +postcar-srcs += $(SIPI_BIN).manual endif rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S @@ -37,3 +40,22 @@ $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + + +rmodules_$(ARCH-postcar-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-postcar-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-postcar-y)) $(CFLAGS_rmodules_$(ARCH-postcar-y)) -nostdlib -r -o $@ $^ + +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +endif + +$(SIPI_BIN): $(SIPI_RMOD) + $(OBJCOPY_postcar) -O binary $< $@ + +$(call src-to-obj,postcar,$(SIPI_BIN).manual): $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-postcar-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..3381d04 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += lapic.c +postcar-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3889c7d..0042f49 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -194,6 +194,19 @@ } } +#if ENV_POSTCAR +static inline unsigned long cpu_index(void) +{ + int i; + + for (i=0; i < CONFIG_MAX_CPUS; i++) { + if (mp_get_apic_id(i) == lapicid()) + return i; + } + return 0; +} +#endif + static void park_this_cpu(void *unused) { stop_this_cpu(); @@ -203,12 +216,11 @@ * been loaded. */ static void asmlinkage ap_init(unsigned int cpu) { - struct cpu_info *info; + static struct cpu_info *info; /* Ensure the local APIC is enabled */ enable_lapic(); - info = cpu_info(); info->index = cpu; info->cpu = cpus[cpu].dev; @@ -399,7 +411,7 @@ /* Assuming linear APIC space allocation. AP will set its own APIC id in the ap_init() path above. */ - cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i; + cpu_path.apic.apic_id = lapicid() + i; /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); @@ -565,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) { struct device_path cpu_path; - struct cpu_info *info; + static struct cpu_info *info; /* Print processor name */ fill_processor_name(processor_name); @@ -579,9 +591,9 @@ cpu_path.apic.apic_id = lapicid(); /* Find the device structure for the boot CPU. */ - info = cpu_info(); info->cpu = alloc_find_dev(cpu_bus, &cpu_path); info->cpu->name = processor_name; + info->index = cpu_index(); if (info->index != 0) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); @@ -661,8 +673,7 @@ static void mp_initialize_cpu(void) { /* Call back into driver infrastructure for the AP initialization. */ - struct cpu_info *info = cpu_info(); - cpu_initialize(info->index); + cpu_initialize(cpu_index()); } /* Returns APIC id for coreboot CPU number or < 0 on failure. */ diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index caa6e9c..15ee4e1 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mtrr.c +postcar-y += mtrr.c romstage-y += earlymtrr.c bootblock-y += earlymtrr.c diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 5dba1a2..6c62814 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += name.c +postcar-y += name.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 32f5ea7..83b7ff8 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -14,6 +14,7 @@ ## ramstage-y += smm_module_loader.c +postcar-y += smm_module_loader.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call create_class_compiler,smm,x86_32)) @@ -23,6 +24,14 @@ $(eval $(call create_class_compiler,smmstub,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call create_class_compiler,smm,x86_32)) +$(eval $(call create_class_compiler,smmstub,x86_32)) +else +$(eval $(call create_class_compiler,smm,x86_64)) +$(eval $(call create_class_compiler,smmstub,x86_64)) +endif + smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) @@ -36,6 +45,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S @@ -45,6 +58,9 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smmstub.manual + # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) @@ -57,6 +73,13 @@ $(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) +endif + + $(obj)/smmstub/smmstub: $(obj)/smmstub/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ @@ -64,6 +87,10 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +$(call src-to-obj,postcar,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,6 +99,12 @@ $(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif +ifeq ($(CONFIG_ARCH_POSTCAR_X86_32),y) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +endif + $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ @@ -84,6 +117,7 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +postcar-srcs += $(obj)/cpu/x86/smm/smm.manual endif smm-y += smmhandler.S diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bed0f71..3a2636c 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -1,9 +1,14 @@ ramstage-y += device.c +postcar-y += device.c ramstage-y += root_device.c +postcar-y += root_device.c ramstage-y += cpu_device.c +postcar-y += cpu_device.c ramstage-y += device_util.c +postcar-y += device_util.c ramstage-$(CONFIG_PCI) += pci_class.c ramstage-$(CONFIG_PCI) += pci_device.c +postcar-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c @@ -12,9 +17,13 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_PCI) += pci_ops.c +postcar-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +postcar-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_rom.c +postcar-$(CONFIG_PCI) += pci_rom.c ramstage-y += smbus_ops.c ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 4cf8c7e..568b517 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <delay.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..191a89a 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c -postcar-$(CONFIG_ELOG_PRERAM) += elog.c +postcar-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8..efe6208 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -28,6 +28,7 @@ ramstage-y += debug.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c +postcar-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c @@ -39,6 +40,10 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c +postcar-y += silicon_init.c +postcar-y += util.c +postcar-y += debug.c + postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0670663..834dbb0 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -54,13 +54,14 @@ post_code(POST_FSP_SILICON_EXIT); fsp_debug_after_silicon_init(status); - +#if 0 // TODO: bad hack /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die("FspSiliconINit returned an error!\n"); } +#endif } void fsps_load(bool s3wake) diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 274955a..c9dbb13 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -20,7 +20,7 @@ endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c - +postcar-$(CONFIG_INTEL_GMA_ACPI) += opregion.c # add_vbt_to_cbfs, first argument is the filename in cbfs, the second one # is the filename in the coreboot tree. add_vbt_to_cbfs= \ diff --git a/src/drivers/mrc_cache/Makefile.inc b/src/drivers/mrc_cache/Makefile.inc index 0d226fe..f3a6dd9 100644 --- a/src/drivers/mrc_cache/Makefile.inc +++ b/src/drivers/mrc_cache/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +postcar-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 4dd0dbc..549470a 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -542,7 +542,7 @@ printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +void update_mrc_cache(void *unused) { update_mrc_cache_by_type(MRC_TRAINING_DATA); diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..70cc516 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) +postcar-y += isa-dma.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 9b5f57c..62f315f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 94a7fc9..2db824a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 85e2599..949525f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -6,7 +6,9 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c bootblock-y += ec.c +postcar-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-y += ec.c crosec_proto.c vstore.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c @@ -31,6 +33,7 @@ verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c +postcar-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a8b3a60..7d65fbd 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -40,7 +40,7 @@ /* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE || ENV_POSTCAR) #endif #define STR(x) #x diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf..6ecb132 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -41,4 +41,6 @@ int mrc_cache_stash_data(int type, uint32_t version, const void *data, size_t size); +void update_mrc_cache(void *unused); + #endif /* _COMMON_MRC_CACHE_H_ */ diff --git a/src/include/rules.h b/src/include/rules.h index deea50b..424fa39 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -270,7 +270,7 @@ * For now only x86 is supported. */ -#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index a82a68d..865ab12 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -23,10 +23,10 @@ /* The devicetree data structures are only mutable in ramstage. All other stages have a constant devicetree. */ -#if !ENV_RAMSTAGE -#define DEVTREE_EARLY 1 -#else +#if ENV_RAMSTAGE || ENV_POSTCAR #define DEVTREE_EARLY 0 +#else +#define DEVTREE_EARLY 1 #endif #if DEVTREE_EARLY diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2fd4e4c..4be2fc9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -86,6 +86,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c +postcar-y += region_file.c romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c @@ -113,20 +114,27 @@ ramstage-y += prog_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c +postcar-y += selfboot.c ramstage-y += coreboot_table.c +postcar-y += coreboot_table.c ramstage-y += bootmem.c +postcar-y += bootmem.c ramstage-y += fmap.c ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c +postcar-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c +postcar-y += fallback_boot.c ramstage-y += compute_ip_checksum.c +postcar-y += compute_ip_checksum.c ramstage-y += cbfs.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +postcar-y += stack.c ramstage-y += hexstrtobin.c ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -139,6 +147,7 @@ ramstage-y += edid_fill_fb.c endif ramstage-y += memrange.c +postcar-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 29682eb..3b1b4c3 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -16,7 +16,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index ff1cb95..ae1b416 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -303,8 +303,8 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if ENV_RAMSTAGE || ENV_POSTCAR || (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) \ + && (ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..a32f284 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,7 @@ range_entry_unlink(&ranges->free_list, r); return r; } - if (ENV_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ac80a62..a9a6681 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -160,7 +160,7 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if ENV_RAMSTAGE || ENV_POSTCAR // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); @@ -213,10 +213,12 @@ timestamp_add_now(TS_SELFBOOT_JUMP); +#if ENV_RAMSTAGE /* Before we go off to run the payload, see if * we stayed within our bounds. */ checkstack(_estack, 0); +#endif prog_run(payload); } diff --git a/src/lib/program.ld b/src/lib/program.ld index 156b862..5694e72 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f4..2b51841 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -28,15 +28,15 @@ default 512 # Select this option to enable use of cr50 SPI TPM on dragon egg. -config DRAGONEGG_USE_SPI_TPM - bool - default y - select MAINBOARD_HAS_SPI_TPM_CR50 - select MAINBOARD_HAS_TPM2 +#config DRAGONEGG_USE_SPI_TPM +# bool +# default y +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 -config DRIVER_TPM_SPI_BUS - depends on DRAGONEGG_USE_SPI_TPM - default 0x1 +#config DRIVER_TPM_SPI_BUS +# depends on DRAGONEGG_USE_SPI_TPM +# default 0x1 config GBB_HWID string @@ -78,6 +78,7 @@ config VBOOT select VBOOT_LID_SWITCH select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_MOCK_SECDATA select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0..0388de3 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -21,10 +21,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c +postcar-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += ramstage.c +postcar-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 657320c..ac26a7d 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -21,7 +21,7 @@ #include <variant/gpio.h> -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_POSTCAR #include <boot/coreboot_tables.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc index 22736b9..f86ac87 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dragonegg/variants/baseboard/Makefile.inc @@ -18,3 +18,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +postcar-y += gpio.c diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..722956e 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -12,14 +12,14 @@ device lapic 0 on end end - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 2 @@ -278,7 +278,7 @@ device pci 19.0 on end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC + device pci 1a.0 off end # eMMC device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_06" @@ -311,7 +311,7 @@ device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 7cc4e53..0e1b69d 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -15,7 +15,7 @@ select SOC_INTEL_ICELAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE - + select EC_ACPI config MAINBOARD_DIR string default "intel/icelake_rvp" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index ae80a02..570e47f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -29,16 +29,19 @@ bootblock-y += vbnv.c verstage-y += vbnv.c romstage-y += vbnv.c +postcar-y += vbnv.c ramstage-y += vbnv.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c bootblock-$(CONFIG_VBOOT_VBNV_EC) += vbnv_ec.c diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..f55e41a 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -18,7 +18,9 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +postcar-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c +postcar-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c6bdac5..d792111 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 0ea6cb9..247e9e4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -446,7 +446,7 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) /* Save wake source data for ACPI _SWS methods in NVS */ -static void acpi_save_wake_source(void *unused) +void acpi_save_wake_source(void *unused) { global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); uint32_t pm1, *gpe0; diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227..57f1386 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -7,6 +7,8 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c diff --git a/src/soc/intel/common/block/gpio/Makefile.inc b/src/soc/intel/common/block/gpio/Makefile.inc index b0ffee3..8db62fd 100644 --- a/src/soc/intel/common/block/gpio/Makefile.inc +++ b/src/soc/intel/common/block/gpio/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO) += gpio.c diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index 44dfc7e..f58b3e7 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f72adfc..a6df4ee 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 6b1b9bd..cfbdf15 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -91,4 +91,6 @@ */ void soc_power_states_generation(int core_id, int cores_per_package); +void acpi_save_wake_source(void *unused); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index babf9ce..329051f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -64,6 +64,8 @@ */ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, const struct sa_mmio_descriptor *sa_fixed_resources, size_t count); + +void systemagent_read_resources(struct device *dev); /* * API to set BIOS Reset CPL through MCHBAR * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h diff --git a/src/soc/intel/common/block/itss/Makefile.inc b/src/soc/intel/common/block/itss/Makefile.inc index bc0e97a..ba3bcb9 100644 --- a/src/soc/intel/common/block/itss/Makefile.inc +++ b/src/soc/intel/common/block/itss/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS) += itss.c diff --git a/src/soc/intel/common/block/lpc/Makefile.inc b/src/soc/intel/common/block/lpc/Makefile.inc index 428ade9..400dfe4 100644 --- a/src/soc/intel/common/block/lpc/Makefile.inc +++ b/src/soc/intel/common/block/lpc/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c diff --git a/src/soc/intel/common/block/pcr/Makefile.inc b/src/soc/intel/common/block/pcr/Makefile.inc index 0577e0a..3da14ea 100644 --- a/src/soc/intel/common/block/pcr/Makefile.inc +++ b/src/soc/intel/common/block/pcr/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCR) += pcr.c diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636..e4d4b0b 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 9608359..cfbbbe9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -250,7 +250,7 @@ *resource_cnt = index; } -static void systemagent_read_resources(struct device *dev) +void systemagent_read_resources(struct device *dev) { int index = 0; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index c1cef5d..7884961 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" #include <timer.h> -#if !ENV_RAMSTAGE +#if !ENV_RAMSTAGE && !ENV_POSTCAR void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 74c9182..84458aa 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -33,12 +33,15 @@ romstage-y += uart.c ramstage-y += acpi.c +postcar-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +postcar-y += cpu.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c +postcar-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c @@ -50,17 +53,22 @@ ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += smmrelocate.c +postcar-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += sd.c +ramstage-y += payload_init.c + smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c - +postcar-y += fsp_params.c +postcar-y += gpio.c +postcar-y += payload_init.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a..c147692 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -220,7 +220,7 @@ gnvs->dpte = config->dptf_enable; /* Fill in the Wifi Region id */ - gnvs->cid1 = wifi_regulatory_domain(); +// gnvs->cid1 = wifi_regulatory_domain(); // TODO: bad hack /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; diff --git a/src/soc/intel/icelake/include/soc/payload_init.h b/src/soc/intel/icelake/include/soc/payload_init.h new file mode 100644 index 0000000..4e838cd --- /dev/null +++ b/src/soc/intel/icelake/include/soc/payload_init.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _PAYLOAD_INIT_H_ +#define _PAYLOAD_INIT_H_ + +#include <stdint.h> + +void postcar_payload_init(void); +#endif diff --git a/src/soc/intel/icelake/payload_init.c b/src/soc/intel/icelake/payload_init.c new file mode 100644 index 0000000..20fe90c --- /dev/null +++ b/src/soc/intel/icelake/payload_init.c @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <boot/tables.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mp.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/systemagent.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <romstage_handoff.h> +#include <soc/pci_devs.h> +#include <string.h> +#include <program_loading.h> +#include <soc/payload_init.h> + +#include <cpu/intel/microcode.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/acpi.h> +#include <soc/cpu.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "mrc_cache.h" +#include <soc/intel/common/acpi.h> + +#define XHCI_FIXED_BAR 0xb2310000 +#define XHCI_BAR_SIZE 0x10000 + +#define IGD_FIXED_BAR 0xb0000000 +#define IGD_BAR_SIZE 0x1000000 +#define IGD_FIXED_BAR_2 0xa0000000 +#define IGD_BAR_SIZE_2 0x10000000 + +static void pch_set_bar(struct device *dev, uintptr_t tempbar, + uintptr_t tempbar_1, uintptr_t tempbar_2) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, tempbar_1); + pci_write_config32(dev, PCI_BASE_ADDRESS_2, tempbar_2); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +static void allocate_device_resource(struct device *dev, int offset, + uint32_t base, uint32_t size) +{ + struct resource *res; + + res = new_resource(dev, offset); + res->base = base; + res->size = size; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; +} + +static void set_device_resource(struct device *dev, int offset, + uint32_t base) +{ + struct resource *res; + + res = find_resource(dev, offset); + dev->command |= 2; + res->flags = IORESOURCE_STORED; + report_resource_stored(dev, res, "Device BAR 0"); + + pci_dev_enable_resources(dev); +} + +static void enable_xhci_device(void) +{ + struct device *dev = PCH_DEV_XHCI; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR, XHCI_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + XHCI_FIXED_BAR); + + pch_set_bar(dev, XHCI_FIXED_BAR, 0, 0); +} + +static void enable_igd_device(void) +{ + struct device *dev = SA_DEV_IGD; + + allocate_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR, IGD_BAR_SIZE); + set_device_resource(dev, PCI_BASE_ADDRESS_0, + IGD_FIXED_BAR); + + allocate_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2, IGD_BAR_SIZE_2); + set_device_resource(dev, PCI_BASE_ADDRESS_2, + IGD_FIXED_BAR_2); + + pch_set_bar(dev, IGD_FIXED_BAR, 0, IGD_FIXED_BAR_2); +} + +static void wrapper_x86_core_init(void *unused) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + + soc_core_init(dev); +} + +static void init_cpus(void) +{ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + static const void *microcode_patch; + + intel_microcode_load_unlocked(microcode_patch); + + if (dev && dev->link_list) + soc_init_cpus(dev->link_list); + + if (mp_run_on_all_cpus(&wrapper_x86_core_init, NULL, 5000) < 0) + printk(BIOS_ERR, "CPU Init failure\n"); +} + +static void wrapper_x86_setup_mtrrs(void *unused) +{ + x86_setup_mtrrs_with_detect(); +} + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void post_cpus_init(void) +{ + if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL, 5000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); + + x86_mtrr_check(); +} + +static void wake_from_s3(void) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + void *wake_vector; + + wake_vector = acpi_find_wakeup_vector(); + + if (wake_vector != NULL) { + acpi_save_wake_source(NULL); + arch_bootstate_coreboot_exit(); + acpi_resume(wake_vector); + } +#endif +} + +static void finaize_smm(void) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(0xcb, 0xb2); +} + +void postcar_payload_init(void) +{ + struct device *dev = SA_DEV_ROOT; + int is_s3_resume = romstage_handoff_is_resume(); + + /* Initialize CPU cores */ + init_cpus(); + + /* Perform silicon specific init. */ + fsp_silicon_init(is_s3_resume); + + /* Save MRC cache into SPI*/ + update_mrc_cache(NULL); + + /* Read Resources for Root Device 0:0:0 */ + systemagent_read_resources(dev); + pci_dev_set_resources(dev); + pci_dev_enable_resources(dev); + + /* Make IGD Enable */ + enable_igd_device(); + + /* Make USB bootable */ + enable_xhci_device(); + + /* Add S3 Resume logic */ + if (is_s3_resume) { + finaize_smm(); + wake_from_s3(); + } + + acpi_prepare_resume_backup(); + + /* DSDT generation */ + southbridge_inject_dsdt(dev); + mainboard_chromeos_acpi_generate(); + + /* Post MP Init to program MTRR on APs */ + post_cpus_init(); + + /* Create coreboot tables */ + write_tables(); + + /* Load Payload */ + payload_load(); + + finaize_smm(); + + /* Run Payload */ + payload_run(); +} diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3224e1f..bc43da6 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..28abd2e 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,10 +13,13 @@ ## GNU General Public License for more details. ## +postcar-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +postcar-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c +postcar-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c -- To view, visit https://review.coreboot.org/c/coreboot/+/30985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27479187461ceb078167f2d726f40839865a9233 Gerrit-Change-Number: 30985 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: autoport: Generate a libgfxinit template
by Iru Cai (vimacs) (Code Review) 09 Jun '19

09 Jun '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30912 to review the following change. Change subject: autoport: Generate a libgfxinit template ...................................................................... autoport: Generate a libgfxinit template Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/main.go 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30912/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1a7907 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -748,6 +748,10 @@ ScanRoot(ctx) + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { mf := Create(ctx, "Makefile.inc") defer mf.Close() @@ -882,4 +886,42 @@ } `) + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; +`) } -- To view, visit https://review.coreboot.org/c/coreboot/+/30912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Gerrit-Change-Number: 30912 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size
by Kacper Słomiński (Code Review) 09 Jun '19

09 Jun '19

Kacper Słomiński has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30980 Change subject: mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size ...................................................................... mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM size Signed-off-by: Kacper Słomiński <kacper.slominski72(a)gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30980/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 363df55..c88d317 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -24,6 +24,8 @@ bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_6144 + bool config BOARD_ROMSIZE_KB_8192 bool config BOARD_ROMSIZE_KB_10240 @@ -47,6 +49,7 @@ default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 @@ -94,6 +97,11 @@ help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_6144 + bool "6144 KB (6 MB)" + help + Choose this option if you have a 6144 KB (6 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_8192 bool "8192 KB (8 MB)" help @@ -136,6 +144,7 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 @@ -153,6 +162,7 @@ default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 -- To view, visit https://review.coreboot.org/c/coreboot/+/30980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Gerrit-Change-Number: 30980 Gerrit-PatchSet: 1 Gerrit-Owner: Kacper Słomiński <kacper.slominski72(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [TESTME]soc/intel/braswell: Implement and use open source CAR
by Arthur Heymans (Code Review) 08 Jun '19

08 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30778 Change subject: [TESTME]soc/intel/braswell: Implement and use open source CAR ...................................................................... [TESTME]soc/intel/braswell: Implement and use open source CAR Copied from baytrail. Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/car.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/cache_as_ram.inc 6 files changed, 242 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30778/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 6409ad5..10e3c60 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -21,36 +21,38 @@ #include <program_loading.h> #include <timestamp.h> -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params) +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc) { + /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram + * is still enabled. We can directly access work buffer here. */ + FSP_INFO_HEADER *fih; + struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); + /* Initialize timestamp book keeping only once. */ - timestamp_init(car_params->tsc); + timestamp_init(tsc); /* Call into pre-console init code then initialize console. */ car_soc_pre_console_init(); car_mainboard_pre_console_init(); console_init(); - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + printk(BIOS_SPEW, "bist: 0x%08lx\n", bist); + printk(BIOS_SPEW, "tsc: 0x%016llx\n", tsc); - printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); - printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); - - if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || - car_params->bootloader_car_end != - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { - printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n", - CONFIG_DCACHE_RAM_BASE, - CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE, - (long)car_params->bootloader_car_start, - (long)car_params->bootloader_car_end); + if (prog_locate(&fsp)) { + fih = NULL; + printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); + } else { + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); } car_soc_post_console_init(); car_mainboard_post_console_init(); /* Return new stack value in RAM back to assembly stub. */ - cache_as_ram_stage_main(car_params->fih); + cache_as_ram_stage_main(fih); } /* Entry point taken when romstage is called after a separate verstage. */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index df5e0da..96c9cf9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -30,7 +30,7 @@ }; /* Entry points from the cache-as-ram assembly code. */ -asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void cache_as_ram_main(unsigned long bist, uint64_t tsc); asmlinkage void after_cache_as_ram(void *chipset_context); asmlinkage void romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d0a250a..b780038 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,7 +39,8 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC +# select USE_GENERIC_FSP_CAR_INC + select SKIP_FSP_CAR select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 3296331..1a5addb 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -18,6 +18,7 @@ postcar-y += memmap.c postcar-y += iosf.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index c3ed415..1ab1b45 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,5 @@ romstage-y += early_spi.c romstage-y += pmc.c romstage-y += romstage.c + +cpu_incs-y += $(src)/soc/intel/braswell/romstage/cache_as_ram.inc diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc new file mode 100644 index 0000000..9db7f85 --- /dev/null +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> + +#include "fmap_config.h" + +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE _ALIGN_UP_POW2(___FMAP__COREBOOT_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) + +#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Configure the default memory type to uncacheable as well as disable + * fixed and variable range mtrrs. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x22) + /* Zero the variable MTRRs. */ + movl $IA32_MCG_CAP, %ecx + rdmsr + movzx %al, %ebx + /* First variable MTRR. */ + movl $MTRR_PHYS_BASE(0), %ecx + xorl %eax, %eax + xorl %edx, %edx +1: + wrmsr + inc %ecx + dec %ebx + jnz 1b + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRR_PHYS_MASK(0), %ecx + wrmsr + movl $MTRR_PHYS_MASK(1), %ecx + wrmsr + + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRR_PHYS_BASE(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRR_PHYS_MASK(0)), %ecx + rdmsr + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + post_code(0x25) + /* Set code caching up for romstage. */ + movl $(MTRR_PHYS_BASE(1)), %ecx + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x26) + + /* Enable the L2 cache. */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr + + post_code(0x27) + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + wrmsr + + post_code(0x28) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* enable no evict mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $2, %eax + wrmsr + + post_code(0x29) + + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp + + /* Push the initial TSC value from boot block. The low 32 bits are + * in mm0, and the high 32 bits are in mm1. */ + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x2a) + /* Call car.c main function. */ + call cache_as_ram_main + + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) + +.Lhlt: + hlt + jmp .Lhlt + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list -- To view, visit https://review.coreboot.org/c/coreboot/+/30778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29eabb8960b5e98a9b50f7c7082b9e148a42fde2 Gerrit-Change-Number: 30778 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: sb/intel/i82801gx: Detect if the southbridge supports AHCI
by Arthur Heymans (Code Review) 06 Jun '19

06 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30822 Change subject: sb/intel/i82801gx: Detect if the southbridge supports AHCI ...................................................................... sb/intel/i82801gx: Detect if the southbridge supports AHCI This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/lenovo/z61t/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/sata.c 25 files changed, 18 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30822/1 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 898aae4..84c923b 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -64,7 +64,6 @@ register "gpi1_routing" = "2" register "gpi7_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 156fe3f..acb8ac6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -51,7 +51,6 @@ register "gpi13_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ba2f00d..f4d1dc4 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 2fa0fe4..2b74e7e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index b458115..5479faf 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -46,7 +46,6 @@ register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 2f7d278..de63da2 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -53,7 +53,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 5bf582b..4e39ac5 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -43,7 +43,6 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x04000440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 75df88e..a611ee3 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -40,7 +40,6 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 237e22d..a00718f 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -48,7 +48,6 @@ register "ide_enable_primary" = "0x0" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" device pci 1b.0 on end # Audio diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index a81ef3a..f2a3912 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -57,7 +57,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "docking_supported" = "1" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 7ed4d19..1c69613 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -76,7 +76,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 8b47c4f..d24eb5d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -48,7 +48,6 @@ register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3544c96..8b170e1 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -36,7 +36,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x1" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a008610..825611e 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,7 +38,6 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 716654c..573b9c8 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -50,7 +50,6 @@ register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index be28763..295fbc4 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -63,7 +63,6 @@ register "gpi15_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 06f29e0..023c516 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -36,7 +36,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 7b1721e..67b7794 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -72,7 +72,6 @@ register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index cc3ef49..ace2bfb 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -44,7 +44,6 @@ register "gpi13_routing" = "1" # ??vendor register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2a60b87..ad31557 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -65,7 +65,6 @@ register "gpi12_routing" = "1" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 92bf3ce..6e2450a 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -71,7 +71,6 @@ register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index ec42766..efe8ce1 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -61,7 +61,6 @@ register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index db27ef7..019c65e 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -65,7 +65,7 @@ uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; - uint32_t sata_ahci; + uint32_t sata_no_ahci; uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d37a822..521d372 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -90,6 +90,7 @@ #define FDVCT 0xe4 #define PCIE_4_PORTS_MAX (1 << 7) +#define AHCI_UNSUPPORTED (1 << 3) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 567c1e5..dcd9b80 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -71,6 +71,10 @@ u32 *ahci_bar; u8 ports; + + struct device *lpc_dev = pcidev_path_on_root(PCI_DEVFN(31, 0)); + bool ahci_supported = pci_read_config32(lpc_dev, FDVCT) & ACHI_UNSUPPORTED ? false : true; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -87,7 +91,18 @@ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { + if (ahci_supported && !config->sata_no_ahci) { + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + /* Allow both Legacy and Native mode */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); + ahci_bar[3] = config->sata_ports_implemented; + } else if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -118,17 +133,6 @@ /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if (config->sata_ahci) { - printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); - /* Allow both Legacy and Native mode */ - pci_write_config8(dev, 0x09, 0x8f); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - - ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); - ahci_bar[3] = config->sata_ports_implemented; } else { printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); /* Set Sata Controller Mode. No Mapping(?) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Gerrit-Change-Number: 30822 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 25

Change in ...coreboot[master]: mb/*/devicetree.cb: Remove unavailable PCIe ports
by Arthur Heymans (Code Review) 05 Jun '19

05 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30821 Change subject: mb/*/devicetree.cb: Remove unavailable PCIe ports ...................................................................... mb/*/devicetree.cb: Remove unavailable PCIe ports Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb 11 files changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30821/1 diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 833ea00..156fe3f 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -62,8 +62,6 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 63bcbc8..ba2f00d 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -57,8 +57,6 @@ device pci 1c.1 on end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index cdcadba..2fa0fe4 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -61,8 +61,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 4c910c5..b458115 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -56,8 +56,6 @@ device pci 1c.1 on end # PCIe 2 (ethernet) device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1849 0x27c8 end diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 642f1ee..2f7d278 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -64,8 +64,6 @@ device pci 1c.1 on end # PCIe device pci 1c.2 off end # PCIe port 3 device pci 1c.3 off end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on # USB UHCI ioapic_irq 2 INTA 0x10 end diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index f721f08..5bf582b 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -54,8 +54,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 84cf353..237e22d 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -58,8 +58,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 05edb27..8b47c4f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -63,8 +63,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1458 0x5004 end diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 90c517f..716654c 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -59,8 +59,6 @@ device pci 1c.1 off end # PCIe port 2 device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..be28763 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -77,8 +77,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x8086 0x5756 end diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index f3f56ce..cc3ef49 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -55,8 +55,6 @@ end device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB -- To view, visit https://review.coreboot.org/c/coreboot/+/30821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Gerrit-Change-Number: 30821 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: mb/google/hatch: Set VmxEnable to 1
by Furquan Shaikh (Code Review) 03 Jun '19

03 Jun '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31438 Change subject: mb/google/hatch: Set VmxEnable to 1 ...................................................................... mb/google/hatch: Set VmxEnable to 1 This change sets VmxEnable to 1 to match the kernel setting. BUG=b:124518711 Change-Id: I20f9282a94dc502e963578c435061ffe52ce83d3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31438/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index aaef663..1cb570c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,7 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "VmxEnable" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication -- To view, visit https://review.coreboot.org/c/coreboot/+/31438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20f9282a94dc502e963578c435061ffe52ce83d3 Gerrit-Change-Number: 31438 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: google/buddy: fix Windows ACPI error with WLAN
by Matt DeVillier (Code Review) 02 Jun '19

02 Jun '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30523 Change subject: google/buddy: fix Windows ACPI error with WLAN ...................................................................... google/buddy: fix Windows ACPI error with WLAN Buddy's WLAN ACPI code was equivalent to, but formatted differently from the other auron variants. Since only differnce is root port used, have buddy use common WLAN ACPI and use preprocessor guards to set the root port correctly. Test: build/boot Buddy, verify Windows 10 boots without ACPI BIOS ERROR. Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/acpi/mainboard.asl M src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl 2 files changed, 4 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/30523/1 diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 204c1c4..b473362 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -16,8 +16,11 @@ #include <variant/onboard.h> -#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY) +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY) +Scope (\_SB.PCI0.RP02) +#else Scope (\_SB.PCI0.RP01) +#endif { Device (WLAN) { @@ -35,7 +38,6 @@ } } } -#endif #include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl index 788fbdc..e9fd212 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/buddy/include/variant/acpi/mainboard.asl @@ -117,27 +117,3 @@ } } } - -/* - * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce - */ -Scope (\_SB.PCI0.RP02) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is WLAN_WAKE_L_Q */ - Name (GPIO, BOARD_WLAN_WAKE_GPIO) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527 Gerrit-Change-Number: 30523 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: qualcomm/qcs405: enable SPI bus 4 for TPM
by Patrick Georgi (Code Review) 02 Jun '19

02 Jun '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30934 Change subject: qualcomm/qcs405: enable SPI bus 4 for TPM ...................................................................... qualcomm/qcs405: enable SPI bus 4 for TPM Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/Makefile.inc A src/mainboard/google/mistral/verstage.c M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 6 files changed, 93 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30934/1 diff --git a/src/mainboard/google/mistral/Makefile.inc b/src/mainboard/google/mistral/Makefile.inc index 0e2f6bd..e9013af 100644 --- a/src/mainboard/google/mistral/Makefile.inc +++ b/src/mainboard/google/mistral/Makefile.inc @@ -5,6 +5,7 @@ verstage-y += memlayout.ld verstage-y += chromeos.c +verstage-y += verstage.c romstage-y += memlayout.ld romstage-y += chromeos.c diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c new file mode 100644 index 0000000..1fad7f5 --- /dev/null +++ b/src/mainboard/google/mistral/verstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <spi-generic.h> + +void verstage_mainboard_init(void) +{ + struct spi_slave spi; + printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n"); + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + } +} diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 270dad3..015632f 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -87,6 +87,9 @@ static struct qcs405_clock *const blsp1_uart2_clk = (void *)GCC_BLSP1_UART2_BASE; +static struct qcs405_clock *const blsp1_qup0_spi_clk = + (void *)GCC_BLSP1_QUP0_SPI_BASE; + static struct qcs405_clock *const blsp2_qup0_spi_clk = (void *)GCC_BLSP2_QUP0_SPI_BASE; @@ -207,6 +210,13 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); + clock_configure(blsp1_qup0_spi_clk, spi_cfg, 50000000, + ARRAY_SIZE(spi_cfg)); + clock_enable(REG(GCC_BLSP1_QUP0_SPI_APPS_CBCR)); + clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), + REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), + BLSP1_AHB_CLK_ENA); + clock_configure(blsp2_qup0_spi_clk, spi_cfg, 50000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP2_QUP0_SPI_APPS_CBCR)); diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 2736133..7e7af3f 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -45,6 +45,7 @@ #define GCC_BLSP1_UART3_APPS_CBCR 0x180400C #define GCC_BLSP2_UART0_APPS_CBCR 0x180C03C +#define GCC_BLSP1_QUP0_SPI_APPS_CBCR 0x1802004 #define GCC_BLSP2_QUP0_SPI_APPS_CBCR 0x180C004 #define GCC_BLSP1_AHB_CBCR 0x1801008 diff --git a/src/soc/qualcomm/qcs405/include/soc/spi.h b/src/soc/qualcomm/qcs405/include/soc/spi.h index 5da709f..10f259b 100644 --- a/src/soc/qualcomm/qcs405/include/soc/spi.h +++ b/src/soc/qualcomm/qcs405/include/soc/spi.h @@ -37,60 +37,80 @@ #include <spi-generic.h> #define BLSP0_QUP_REG_BASE ((void *)0x78b5000u) +#define BLSP4_QUP_REG_BASE ((void *)0x78b9000u) #define BLSP5_QUP_REG_BASE ((void *)0x7af5000u) #define BLSP0_SPI_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000300) +#define BLSP4_SPI_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000300) #define BLSP5_SPI_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000300) #define BLSP0_SPI_IO_CONTROL_REG (BLSP0_QUP_REG_BASE + 0x00000304) +#define BLSP4_SPI_IO_CONTROL_REG (BLSP4_QUP_REG_BASE + 0x00000304) #define BLSP5_SPI_IO_CONTROL_REG (BLSP5_QUP_REG_BASE + 0x00000304) #define BLSP0_SPI_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x00000308) +#define BLSP4_SPI_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x00000308) #define BLSP5_SPI_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x00000308) #define BLSP0_SPI_DEASSERT_WAIT_REG (BLSP0_QUP_REG_BASE + 0x00000310) +#define BLSP4_SPI_DEASSERT_WAIT_REG (BLSP4_QUP_REG_BASE + 0x00000310) #define BLSP5_SPI_DEASSERT_WAIT_REG (BLSP5_QUP_REG_BASE + 0x00000310) #define BLSP0_SPI_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x0000030c) +#define BLSP4_SPI_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x0000030c) #define BLSP5_SPI_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x0000030c) #define BLSP0_QUP_CONFIG_REG (BLSP0_QUP_REG_BASE + 0x00000000) +#define BLSP4_QUP_CONFIG_REG (BLSP4_QUP_REG_BASE + 0x00000000) #define BLSP5_QUP_CONFIG_REG (BLSP5_QUP_REG_BASE + 0x00000000) #define BLSP0_QUP_ERROR_FLAGS_REG (BLSP0_QUP_REG_BASE + 0x0000001c) +#define BLSP4_QUP_ERROR_FLAGS_REG (BLSP4_QUP_REG_BASE + 0x0000001c) #define BLSP5_QUP_ERROR_FLAGS_REG (BLSP5_QUP_REG_BASE + 0x0000001c) #define BLSP0_QUP_ERROR_FLAGS_EN_REG (BLSP0_QUP_REG_BASE + 0x00000020) +#define BLSP4_QUP_ERROR_FLAGS_EN_REG (BLSP4_QUP_REG_BASE + 0x00000020) #define BLSP5_QUP_ERROR_FLAGS_EN_REG (BLSP5_QUP_REG_BASE + 0x00000020) #define BLSP0_QUP_OPERATIONAL_MASK (BLSP0_QUP_REG_BASE + 0x00000028) +#define BLSP4_QUP_OPERATIONAL_MASK (BLSP4_QUP_REG_BASE + 0x00000028) #define BLSP5_QUP_OPERATIONAL_MASK (BLSP5_QUP_REG_BASE + 0x00000028) #define BLSP0_QUP_OPERATIONAL_REG (BLSP0_QUP_REG_BASE + 0x00000018) +#define BLSP4_QUP_OPERATIONAL_REG (BLSP4_QUP_REG_BASE + 0x00000018) #define BLSP5_QUP_OPERATIONAL_REG (BLSP5_QUP_REG_BASE + 0x00000018) #define BLSP0_QUP_IO_MODES_REG (BLSP0_QUP_REG_BASE + 0x00000008) +#define BLSP4_QUP_IO_MODES_REG (BLSP4_QUP_REG_BASE + 0x00000008) #define BLSP5_QUP_IO_MODES_REG (BLSP5_QUP_REG_BASE + 0x00000008) #define BLSP0_QUP_STATE_REG (BLSP0_QUP_REG_BASE + 0x00000004) +#define BLSP4_QUP_STATE_REG (BLSP4_QUP_REG_BASE + 0x00000004) #define BLSP5_QUP_STATE_REG (BLSP5_QUP_REG_BASE + 0x00000004) #define BLSP0_QUP_INPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000218 + 4 * (c)) +#define BLSP4_QUP_INPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000218 + 4 * (c)) #define BLSP5_QUP_INPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000218 + 4 * (c)) #define BLSP0_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP0_QUP_REG_BASE + 0x00000110 + 4 * (c)) +#define BLSP4_QUP_OUTPUT_FIFOc_REG(c) \ + (BLSP4_QUP_REG_BASE + 0x00000110 + 4 * (c)) #define BLSP5_QUP_OUTPUT_FIFOc_REG(c) \ (BLSP5_QUP_REG_BASE + 0x00000110 + 4 * (c)) #define BLSP0_QUP_MX_INPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000200) +#define BLSP4_QUP_MX_INPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000200) #define BLSP5_QUP_MX_INPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000200) #define BLSP0_QUP_MX_OUTPUT_COUNT_REG (BLSP0_QUP_REG_BASE + 0x00000100) +#define BLSP4_QUP_MX_OUTPUT_COUNT_REG (BLSP4_QUP_REG_BASE + 0x00000100) #define BLSP5_QUP_MX_OUTPUT_COUNT_REG (BLSP5_QUP_REG_BASE + 0x00000100) #define BLSP0_QUP_SW_RESET_REG (BLSP0_QUP_REG_BASE + 0x0000000c) +#define BLSP4_QUP_SW_RESET_REG (BLSP4_QUP_REG_BASE + 0x0000000c) #define BLSP5_QUP_SW_RESET_REG (BLSP5_QUP_REG_BASE + 0x0000000c) #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8) @@ -138,6 +158,7 @@ #define SPI_MODE2 2 #define SPI_MODE3 3 #define BLSP0_SPI 0 +#define BLSP4_SPI 4 #define BLSP5_SPI 5 struct blsp_spi { diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 245569b..d4fb29e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -60,7 +60,29 @@ BLSP0_QUP_OPERATIONAL_MASK, BLSP0_SPI_DEASSERT_WAIT_REG, }, - {0}, {0}, {0}, {0}, + {0}, {0}, {0}, + /* BLSP4 registers for SPI interface */ + { + BLSP4_SPI_CONFIG_REG, + BLSP4_SPI_IO_CONTROL_REG, + BLSP4_SPI_ERROR_FLAGS_REG, + BLSP4_SPI_ERROR_FLAGS_EN_REG, + BLSP4_QUP_CONFIG_REG, + BLSP4_QUP_ERROR_FLAGS_REG, + BLSP4_QUP_ERROR_FLAGS_EN_REG, + BLSP4_QUP_OPERATIONAL_REG, + BLSP4_QUP_IO_MODES_REG, + BLSP4_QUP_STATE_REG, + BLSP4_QUP_INPUT_FIFOc_REG(0), + BLSP4_QUP_OUTPUT_FIFOc_REG(0), + BLSP4_QUP_MX_INPUT_COUNT_REG, + BLSP4_QUP_MX_OUTPUT_COUNT_REG, + BLSP4_QUP_SW_RESET_REG, + 0, + 0, + BLSP4_QUP_OPERATIONAL_MASK, + BLSP4_SPI_DEASSERT_WAIT_REG, + }, /* BLSP5 registers for SPI interface */ { BLSP5_SPI_CONFIG_REG, @@ -202,7 +224,7 @@ check_qup_state_valid(ds); } -static struct ipq_spi_slave spi_slave_pool[2]; +static struct ipq_spi_slave spi_slave_pool[3]; static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) { @@ -669,6 +691,7 @@ int i; unsigned int bus = slave->bus; unsigned int cs = slave->cs; + printk(BIOS_ERR, "trying to initialize SPI bus %d\n", bus); if ((bus < BLSP0_SPI) || (bus > BLSP5_SPI) || ((bus == BLSP0_SPI) && (cs > 2)) @@ -694,6 +717,7 @@ * to configure this */ ds->freq = 10000000; + ds->freq = 800000; ds->mode = SPI_MODE0; ds->allocated = 1; @@ -725,6 +749,11 @@ .bus_start = BLSP5_SPI, .bus_end = BLSP5_SPI, }, + { + .ctrlr = &spi_ctrlr, + .bus_start = BLSP4_SPI, + .bus_end = BLSP4_SPI, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/30934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5 Gerrit-Change-Number: 30934 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31249 Change subject: soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE ...................................................................... soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE CONFIG_CBFS_SIZE is only meaningful to generate the default fmap layout and ought not to be used in the code directly. Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31249/1 diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 110d67d..58144bd 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -37,8 +37,8 @@ .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, .CodeRegionBase = - (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), - .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, + (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, .Reserved1 = {0}, }, .FsptConfig = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae72a9fb02d62d7548d34689f5eb371f34cd3d81 Gerrit-Change-Number: 31249 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019