coreboot-gerrit February 2019

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Change in ...coreboot[master]: soc/intel/apollolake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30510 Change subject: soc/intel/apollolake: Don't use CAR_GLOBAL ...................................................................... soc/intel/apollolake: Don't use CAR_GLOBAL All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/meminit.c M src/soc/intel/apollolake/mmap_boot.c M src/soc/intel/apollolake/romstage.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30510/1 diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 889bbde..a230222 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -21,7 +21,7 @@ #include <fsp/soc_binding.h> #include <string.h> -static size_t memory_size_mib CAR_GLOBAL; +static size_t memory_size_mib; size_t memory_in_system_in_mib(void) { diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 1c3077e..8174502 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -57,10 +57,10 @@ * */ -static size_t bios_size CAR_GLOBAL; +static size_t bios_size; -static struct mem_region_device shadow_dev CAR_GLOBAL; -static struct xlate_region_device real_dev CAR_GLOBAL; +static struct mem_region_device shadow_dev; +static struct xlate_region_device real_dev; static void bios_mmap_init(void) { diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 4f4f9f5..4133946 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -58,7 +58,7 @@ 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, }; -static uint32_t fsp_version CAR_GLOBAL; +static uint32_t fsp_version; /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 -- To view, visit https://review.coreboot.org/c/coreboot/+/30510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Gerrit-Change-Number: 30510 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0
by Arthur Heymans (Code Review) 29 May '19

29 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30791 Change subject: src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0 ...................................................................... src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0 This is a better location. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/drivers/intel/fsp1_0/Kconfig 2 files changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/30791/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 232fe63..608afd7 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -151,13 +151,6 @@ This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. -config PLATFORM_USES_FSP1_0 - bool - default n - help - Selected for Intel processors/platform combinations that use the - Intel Firmware Support Package (FSP) 1.0 for initialization. - config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING def_bool n help diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index c7f6c18..4d1c4df 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -13,6 +13,15 @@ ## GNU General Public License for more details. ## +config PLATFORM_USES_FSP1_0 + bool + default n + select CACHE_MRC_SETTINGS + help + Selected for Intel processors/platform combinations that use the + Intel Firmware Support Package (FSP) 1.0 for initialization. + + if PLATFORM_USES_FSP1_0 comment "Intel FSP" -- To view, visit https://review.coreboot.org/c/coreboot/+/30791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Gerrit-Change-Number: 30791 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mb/lenovo/z61t/acpi_tables: Add critical and passive threshold
by Peter Lemenkov (Code Review) 27 May '19

27 May '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31114 to review the following change. Change subject: mb/lenovo/z61t/acpi_tables: Add critical and passive threshold ...................................................................... mb/lenovo/z61t/acpi_tables: Add critical and passive threshold Add critical and passive threshold to be advertised in thermal zone 0. This commit follows up on commit afa627db with Change-Id Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01. Change-Id: I7d645818d2b2f6b7c16d2d813bf982a55774561d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/z61t/acpi_tables.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31114/1 diff --git a/src/mainboard/lenovo/z61t/acpi_tables.c b/src/mainboard/lenovo/z61t/acpi_tables.c index 3e9a810..183b7fe 100644 --- a/src/mainboard/lenovo/z61t/acpi_tables.c +++ b/src/mainboard/lenovo/z61t/acpi_tables.c @@ -23,4 +23,7 @@ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; + /* Set thermal levels */ + gnvs->tcrt = 100; + gnvs->tpsv = 90; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d645818d2b2f6b7c16d2d813bf982a55774561d Gerrit-Change-Number: 31114 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 25 May '19

25 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30939 Change subject: [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK ...................................................................... [UNTESTED]nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK Not yet tested. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/mainboard/foxconn/d41s/Makefile.inc A src/mainboard/foxconn/d41s/bootblock.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/intel/d510mo/Makefile.inc A src/mainboard/intel/d510mo/bootblock.c M src/mainboard/intel/d510mo/romstage.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/bootblock_gcc.c 15 files changed, 149 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30939/1 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 6566a01..e6e904d 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -20,4 +20,11 @@ hex default 0x4000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + endif diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 868f6e5..c95e135 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,7 +8,9 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S + postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/foxconn/d41s/Makefile.inc +++ b/src/mainboard/foxconn/d41s/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/foxconn/d41s/bootblock.c b/src/mainboard/foxconn/d41s/bootblock.c new file mode 100644 index 0000000..86abba4 --- /dev/null +++ b/src/mainboard/foxconn/d41s/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8721f/it8721f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + + /* Environment Controller */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index ade85e6..c7e6e55 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -15,31 +15,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <device/pnp_def.h> -#include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8721f/it8721f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN - | COMA_LPC_EN); - - /* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void get_mb_spd_addrmap(u8 *spd_addrmap) { diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc index f3d7e76..abfc473 100644 --- a/src/mainboard/intel/d510mo/Makefile.inc +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -1,2 +1,3 @@ +bootblock-y += bootblock.c ramstage-y += cstates.c romstage-y += gpio.c diff --git a/src/mainboard/intel/d510mo/bootblock.c b/src/mainboard/intel/d510mo/bootblock.c new file mode 100644 index 0000000..b66164e --- /dev/null +++ b/src/mainboard/intel/d510mo/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, + pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN + | COMB_LPC_EN); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 28e2e25..d9ec66b 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -14,31 +14,8 @@ * GNU General Public License for more details. */ -#include <arch/io.h> -#include <device/pnp_def.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/pineview/pineview.h> -#include <superio/winbond/w83627thg/w83627thg.h> -#include <superio/winbond/common/winbond.h> - -#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - -void mb_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN - | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} void mb_pirq_setup(void) { diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305..773f1db 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select C_ENVIRONMENT_BOOTBLOCK config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 524bcae..6323391 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 1fab845..373d476 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */ #include <arch/io.h> -#define PCIEXBAR 0x60 +#include <cpu/intel/car/bootblock.h> +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 65d21cf..f53ff17 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -236,7 +236,6 @@ u8 decode_pciebar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ -void mb_enable_lpc(void); void get_mb_spd_addrmap(u8 *spd_addr_map); void mb_pirq_setup(void); /* optional */ diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 10ac0f5..b25c36e 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -55,17 +55,12 @@ if (bist == 0) enable_lapic(); - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); - mb_enable_lpc(); // nm10_enable_lpc - /* Initialize console device(s) */ console_init(); diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..0864786 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) +bootblock-y += bootblock_gcc.c + ramstage-y += i82801gx.c ramstage-y += ac97.c ramstage-y += azalia.c diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c new file mode 100644 index 0000000..8b9826a --- /dev/null +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/intel/car/bootblock.h> +#include "i82801gx.h" + +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +void bootblock_early_southbridge_init(void) +{ + enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Gerrit-Change-Number: 30939 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Add HP EliteBook 8760w
by Iru Cai (vimacs) (Code Review) 25 May '19

25 May '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30950 to review the following change. Change subject: Documentation: Add HP EliteBook 8760w ...................................................................... Documentation: Add HP EliteBook 8760w Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/8760w.md A Documentation/mainboard/hp/elitebook_series.md M Documentation/mainboard/index.md 3 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30950/1 diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md new file mode 100644 index 0000000..ba4da7d --- /dev/null +++ b/Documentation/mainboard/hp/8760w.md @@ -0,0 +1,33 @@ +# HP EliteBook 8760w + +This page describes how to run coreboot on the [HP EliteBook 8760w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +## Untested + +- dock: serial port, parallel port, ... +- TPM +- S3 suspend/resume +- Gigabit Ethernet +- Using `me_cleaner` + +## Working + +- SeaBIOS payload +- EHCI debug: the port is at the right next to the charging port +- USB +- WLAN +- WWAN +- SATA + +[HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/… diff --git a/Documentation/mainboard/hp/elitebook_series.md b/Documentation/mainboard/hp/elitebook_series.md new file mode 100644 index 0000000..6668928 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_series.md @@ -0,0 +1,111 @@ +# HP EliteBook series + +This document is about HP EliteBook series laptops up to Ivy Bridge era +which use SMSC KBC1126 as embedded controller. + +## EC + +SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations. +They use similar EC firmware that will load other code and data from the +SPI flash chip, so we need to put some firmware blobs to the coreboot image. + +The following document takes EliteBook 2760p as an example. + +First, you need to extract the blobs needed by EC firmware using util/kbc1126. +You can extract them from your backup firmware image, or firmware update +provided by HP with [unar] as follows: + +```bash +wget https://ftp.hp.com/pub/softpaq/sp79501-80000/sp79710.exe +unar sp79710.exe +${COREBOOT_DIR}/util/kbc1126/kbc1126_ec_dump sp79710/Rompaq/68SOU.BIN +mv 68SOU.BIN.fw1 ${COREBOOT_DIR}/2760p-fw1.bin +mv 68SOU.BIN.fw2 ${COREBOOT_DIR}/2760p-fw2.bin +``` + +When you config coreboot, select: + +```text +Chipset ---> + [*] Add firmware images for KBC1126 EC + (2760p-fw1.bin) KBC1126 firmware #1 path and filename + (2760p-fw2.bin) KBC1126 filename #2 path and filename +``` + +## Super I/O + +EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide +a serial port and a parallel port, you can debug the laptop via this +serial port. + +## porting + +To port coreboot to an HP EliteBook laptop, you need to do the following: + +- select Kconfig option `EC_HP_KBC1126` +- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O +- initialize EC and Super I/O in romstage +- add EC and Super I/O support to devicetree.cb + +To get the related values for EC in devicetree.cb, you need to extract the EFI +module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually, +`ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values: + +- For xx60 series: 0x60, 0x64, 0xca +- For xx70 series: 0x62, 0x66, 0x81 + +You can use [radare2] and the following [r2pipe] Python script to find +these values from the EcThermalInit EFI module: + +```python +#!/usr/bin/env python + +# install radare2 and use `pip3 install --user r2pipe` to install r2pipe + +import r2pipe +import sys + +if len(sys.argv) < 2: + fn = "ecthermalinit.efi" +else: + fn = sys.argv[1] + +r2 = r2pipe.open(fn) +r2.cmd("aa") +entryf = r2.cmdj("pdfj") + +for insn in entryf["ops"]: + if "lea r8" in insn["opcode"]: + _callback = insn["ptr"] + break + +r2.cmd("af @ {}".format(_callback)) +callbackf_insns = r2.cmdj("pdfj @ {}".format(_callback))["ops"] + +def find_port(addr): + ops = r2.cmdj("pdfj @ {}".format(addr))["ops"] + for insn in ops: + if "lea r8d" in insn["opcode"]: + return insn["ptr"] + +ctrl_reg_found = False + +for i in range(0, len(callbackf_insns)): + if not ctrl_reg_found and "mov cl" in callbackf_insns[i]["opcode"]: + ctrl_reg_found = True + ctrl_reg = callbackf_insns[i]["ptr"] + print("ec_ctrl_reg = 0x%02x" % ctrl_reg) + cmd_port = find_port(callbackf_insns[i+1]["jump"]) + data_port = find_port(callbackf_insns[i+3]["jump"]) + print("ec_cmd_port = 0x%02x\nec_data_port = 0x%02x" % (cmd_port, data_port)) + + if "mov bl" in callbackf_insns[i]["opcode"]: + ctrl_value = callbackf_insns[i]["ptr"] + print("ec_fan_ctrl_value = 0x%02x" % ctrl_value) +``` + + +[unar]: https://theunarchiver.com/command-line +[UEFITool]: https://github.com/LongSoft/UEFITool +[radare2]: https://radare.org/ +[r2pipe]: https://github.com/radare/radare2-r2pipe diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4e2b742..606901f 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -46,6 +46,11 @@ - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +### EliteBook series + +- [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8760w](hp/8760w.md) + ## Lenovo - [T4xx common](lenovo/t4xx_series.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/30950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Gerrit-Change-Number: 30950 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: AGESA binaryPI: Add AGESA entry timestamps
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31515 Change subject: AGESA binaryPI: Add AGESA entry timestamps ...................................................................... AGESA binaryPI: Add AGESA entry timestamps Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31515/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 152011e..887da30 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <stdint.h> #include <string.h> +#include <timestamp.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> @@ -30,54 +31,78 @@ { AGESA_STRUCT_NAME func; const char *name; + uint32_t entry_id; + uint32_t exit_id; }; static const struct agesa_mapping entrypoint[] = { { .func = AMD_INIT_RESET, .name = "AmdInitReset", + .entry_id = TS_AGESA_INIT_RESET_START, + .exit_id = TS_AGESA_INIT_RESET_DONE, }, { .func = AMD_INIT_EARLY, .name = "AmdInitEarly", + .entry_id = TS_AGESA_INIT_EARLY_START, + .exit_id = TS_AGESA_INIT_EARLY_DONE, }, { .func = AMD_INIT_POST, .name = "AmdInitPost", + .entry_id = TS_AGESA_INIT_POST_START, + .exit_id = TS_AGESA_INIT_POST_DONE, }, { .func = AMD_INIT_RESUME, .name = "AmdInitResume", + .entry_id = TS_AGESA_INIT_RESUME_START, + .exit_id = TS_AGESA_INIT_RESUME_DONE, }, { .func = AMD_INIT_ENV, .name = "AmdInitEnv", + .entry_id = TS_AGESA_INIT_ENV_START, + .exit_id = TS_AGESA_INIT_ENV_DONE, }, { .func = AMD_INIT_MID, .name = "AmdInitMid", + .entry_id = TS_AGESA_INIT_MID_START, + .exit_id = TS_AGESA_INIT_MID_DONE, }, { .func = AMD_INIT_LATE, .name = "AmdInitLate", + .entry_id = TS_AGESA_INIT_LATE_START, + .exit_id = TS_AGESA_INIT_LATE_DONE, }, { .func = AMD_S3LATE_RESTORE, .name = "AmdS3LateRestore", + .entry_id = TS_AGESA_S3_LATE_START, + .exit_id = TS_AGESA_S3_LATE_DONE, }, #if !defined(AMD_S3_SAVE_REMOVED) { .func = AMD_S3_SAVE, .name = "AmdS3Save", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, #endif { .func = AMD_S3FINAL_RESTORE, .name = "AmdS3FinalRestore", + .entry_id = TS_AGESA_S3_FINAL_START, + .exit_id = TS_AGESA_S3_FINAL_DONE, }, { .func = AMD_INIT_RTB, .name = "AmdInitRtb", + .entry_id = TS_AGESA_INIT_RTB_START, + .exit_id = TS_AGESA_INIT_RTB_DONE, }, }; @@ -92,6 +117,8 @@ for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { if (task->func == entrypoint[i].func) { task->function_name = entrypoint[i].name; + task->ts_entry_id = entrypoint[i].entry_id; + task->ts_exit_id = entrypoint[i].exit_id; break; } } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index f676192..4d56218 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -21,6 +21,8 @@ #include <arch/cpu.h> #include <bootstate.h> #include <cbfs.h> +#include <cbmem.h> +#include <timestamp.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -263,12 +265,18 @@ AMD_CONFIG_PARAMS *StdHeader = aip.NewStructPtr; ASSERT(StdHeader->Func == func); + if (task.ts_entry_id) + timestamp_add_now(task.ts_entry_id); + if (ENV_ROMSTAGE) final = romstage_dispatch(cb, func, StdHeader); if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); + if (task.ts_exit_id) + timestamp_add_now(task.ts_exit_id); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 45d57c2..f1dd139 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -60,6 +60,8 @@ AGESA_STRUCT_NAME func; const char *function_name; + uint32_t ts_entry_id; + uint32_t ts_exit_id; }; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); -- To view, visit https://review.coreboot.org/c/coreboot/+/31515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Gerrit-Change-Number: 31515 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: AGESA binaryPI: Redo entrypoints namelist
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31514 Change subject: AGESA binaryPI: Redo entrypoints namelist ...................................................................... AGESA binaryPI: Redo entrypoints namelist Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c 1 file changed, 62 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/31514/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 303af53..152011e 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2016-2019 Kyösti Mälkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,45 +26,75 @@ static const char undefined[] = "undefined"; -/* Match order of enum AGESA_STRUCT_NAME. */ -static const char *AgesaFunctionNameStr[] = { - "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", - "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", - "AmdS3LateRestore", "AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", - "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", - "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" +struct agesa_mapping +{ + AGESA_STRUCT_NAME func; + const char *name; }; -/* This function has to match with enumeration of AGESA_STRUCT_NAME defined - * inside AMD.h header file. Unfortunately those are different across - * different vendorcode subtrees. - * - * TBD: Fix said header or move this function together with the strings above - * under vendorcode/ tree. - */ - -static const char *agesa_struct_name(AGESA_STRUCT_NAME state) -{ -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) - if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) - return undefined; - - int index = state - AMD_INIT_RECOVERY; -#else - state >>= 12; - if ((state < AMD_INIT_RECOVERY >> 12) || (state > AMD_IDENTIFY_DIMMS >> 12)) - return undefined; - - int index = state - (AMD_INIT_RECOVERY >> 12); +static const struct agesa_mapping entrypoint[] = { + { + .func = AMD_INIT_RESET, + .name = "AmdInitReset", + }, + { + .func = AMD_INIT_EARLY, + .name = "AmdInitEarly", + }, + { + .func = AMD_INIT_POST, + .name = "AmdInitPost", + }, + { + .func = AMD_INIT_RESUME, + .name = "AmdInitResume", + }, + { + .func = AMD_INIT_ENV, + .name = "AmdInitEnv", + }, + { + .func = AMD_INIT_MID, + .name = "AmdInitMid", + }, + { + .func = AMD_INIT_LATE, + .name = "AmdInitLate", + }, + { + .func = AMD_S3LATE_RESTORE, + .name = "AmdS3LateRestore", + }, +#if !defined(AMD_S3_SAVE_REMOVED) + { + .func = AMD_S3_SAVE, + .name = "AmdS3Save", + }, #endif - return AgesaFunctionNameStr[index]; -} + { + .func = AMD_S3FINAL_RESTORE, + .name = "AmdS3FinalRestore", + }, + { + .func = AMD_INIT_RTB, + .name = "AmdInitRtb", + }, +}; void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) { + int i; + task->apic_id = (u8) (cpuid_ebx(1) >> 24); task->func = func; - task->function_name = agesa_struct_name(func); + task->function_name = undefined; + + for (i = 0; i < ARRAY_SIZE(entrypoint); i++) { + if (task->func == entrypoint[i].func) { + task->function_name = entrypoint[i].name; + break; + } + } printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", task->apic_id, task->function_name, task->func); -- To view, visit https://review.coreboot.org/c/coreboot/+/31514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Gerrit-Change-Number: 31514 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: AGESA: Move debug helper to eventlog file
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31513 Change subject: AGESA: Move debug helper to eventlog file ...................................................................... AGESA: Move debug helper to eventlog file Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h 3 files changed, 40 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31513/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index b80c220..303af53 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Kyösti Mälkki + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -18,6 +20,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> +#include <debug_util.h> #include <AGESA.h> #include <AMD.h> @@ -40,7 +43,7 @@ * under vendorcode/ tree. */ -const char *agesa_struct_name(int state) +static const char *agesa_struct_name(AGESA_STRUCT_NAME state) { #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) @@ -57,6 +60,27 @@ return AgesaFunctionNameStr[index]; } +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func) +{ + task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->func = func; + task->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader) +{ + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + task->apic_id, heap_status_name(StdHeader->HeapStatus), + StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + task->apic_id, task->function_name, task->func); +} + /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 672bca1..f676192 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,7 +27,6 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> -#include <debug_util.h> #include <AMD.h> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) @@ -232,38 +231,6 @@ return status; } -/* DEBUG trace helper */ - -struct agesa_state -{ - u8 apic_id; - - AGESA_STRUCT_NAME func; - const char *function_name; -}; - -static void state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func, - const char *struct_name) -{ - task->apic_id = (u8) (cpuid_ebx(1) >> 24); - task->func = func; - task->function_name = struct_name; - - printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - -static void state_on_exit(struct agesa_state *task, - AMD_CONFIG_PARAMS *StdHeader) -{ - printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", - task->apic_id, heap_status_name(StdHeader->HeapStatus), - StdHeader->HeapStatus, (u32)StdHeader->HeapBasePtr); - - printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", - task->apic_id, task->function_name, task->func); -} - int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func) { AMD_INTERFACE_PARAMS aip; @@ -273,13 +240,12 @@ } agesa_params; void *buf = NULL; size_t len = 0; - const char *state_name = agesa_struct_name(func); AGESA_STATUS status, final; struct agesa_state task; memset(&task, 0, sizeof(task)); - state_on_entry(&task, func, state_name); + agesa_state_on_entry(&task, func); aip.StdHeader = cb->StdHeader; @@ -303,13 +269,13 @@ if (ENV_RAMSTAGE) final = ramstage_dispatch(cb, func, StdHeader); - agesawrapper_trace(final, StdHeader, state_name); + agesawrapper_trace(final, StdHeader, task.function_name); ASSERT(final < AGESA_FATAL); status = amd_release_struct(&aip); ASSERT(status == AGESA_SUCCESS); - state_on_exit(&task, &aip.StdHeader); + agesa_state_on_exit(&task, &aip.StdHeader); return (final < AGESA_FATAL) ? 0 : -1; } diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index c7d654d..45d57c2 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -23,7 +23,6 @@ #define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) /* eventlog */ -const char *agesa_struct_name(int state); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); @@ -54,6 +53,18 @@ void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); + +struct agesa_state +{ + u8 apic_id; + + AGESA_STRUCT_NAME func; + const char *function_name; +}; + +void agesa_state_on_entry(struct agesa_state *task, AGESA_STRUCT_NAME func); +void agesa_state_on_exit(struct agesa_state *task, + AMD_CONFIG_PARAMS *StdHeader); int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func); /* AGESA dispatchers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Gerrit-Change-Number: 31513 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31512 Change subject: AGESA f12 f14 vendorcofe: Clean up extra CFLAGS ...................................................................... AGESA f12 f14 vendorcofe: Clean up extra CFLAGS Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc 2 files changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31512/1 diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index dbea9c3..9bc3c26 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index bf1051c..da79a39 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -43,12 +43,8 @@ CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -# These are invalid, coreboot proper should not require -# use of AGESA internal header files. -CPPFLAGS_x86_ANY = - -CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) -CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) +CPPFLAGS_x86_32 += $(AGESA_INC) +CPPFLAGS_x86_64 += $(AGESA_INC) ####################################################################### -- To view, visit https://review.coreboot.org/c/coreboot/+/31512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Gerrit-Change-Number: 31512 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: AGESA: Move heap_status_name() implementation
by Kyösti Mälkki (Code Review) 25 May '19

25 May '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31511 Change subject: AGESA: Move heap_status_name() implementation ...................................................................... AGESA: Move heap_status_name() implementation Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h M src/vendorcode/amd/agesa/common/Makefile.inc A src/vendorcode/amd/agesa/common/debug_util.c A src/vendorcode/amd/agesa/common/debug_util.h M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc 10 files changed, 34 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31511/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 3231d4f..b80c220 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -21,8 +21,6 @@ #include <AGESA.h> #include <AMD.h> -#include <heapManager.h> - static const char undefined[] = "undefined"; /* Match order of enum AGESA_STRUCT_NAME. */ @@ -34,11 +32,6 @@ "Amd2dDataEye", "AmdS3FinalRestore", "AmdInitRtb" }; -/* heapManager.h */ -static const char *HeapStatusStr[] = { - "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" -}; - /* This function has to match with enumeration of AGESA_STRUCT_NAME defined * inside AMD.h header file. Unfortunately those are different across * different vendorcode subtrees. @@ -64,15 +57,6 @@ return AgesaFunctionNameStr[index]; } -const char *heap_status_name(int status) -{ - if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) - return undefined; - - int index = status - HEAP_DO_NOT_EXIST_YET; - return HeapStatusStr[index]; -} - /* * Possible AGESA_STATUS values: * diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 15ea211..672bca1 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,6 +27,7 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <amdlib.h> +#include <debug_util.h> #include <AMD.h> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 43b205a..c7d654d 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -24,7 +24,6 @@ /* eventlog */ const char *agesa_struct_name(int state); -const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc index 78dd4fc..2479694 100644 --- a/src/vendorcode/amd/agesa/common/Makefile.inc +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesa-entry.c ramstage-y += agesa-entry.c +libagesa-y += debug_util.c libagesa-y += amdlib.c # Do not optimise performance-critical low-level IO for size with -Os, diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000..29d0841 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include <AGESA.h> +#include <AMD.h> +#include <heapManager.h> + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000..a8d9a33 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index f925ccb..dbea9c3 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -46,7 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index ad2d2dc..bf1051c 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 57350d9..1c5dc18 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 3115c4d..c423cf2 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -46,8 +46,6 @@ # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h -CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h -- To view, visit https://review.coreboot.org/c/coreboot/+/31511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Gerrit-Change-Number: 31511 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019