coreboot-gerrit November 2019

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Change in coreboot[master]: nb/intel/gm45: Add VBOOT support
by Arthur Heymans (Code Review) 02 Nov '19

02 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35997 ) Change subject: nb/intel/gm45: Add VBOOT support ...................................................................... nb/intel/gm45: Add VBOOT support Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35997/1 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 169dcac..1a6fe83 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,6 +29,10 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE +config VBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + config CBFS_SIZE hex default 0x100000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943723da7167a47f514eda19fb9b71b8f56c2d32 Gerrit-Change-Number: 35997 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.
by Nico Huber (Code Review) 02 Nov '19

02 Nov '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35994 ) Change subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK. ...................................................................... cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK. Tested on Thinkpad X200: the romstage execution speeds are back to pre-C_ENVIRONMENT_BOOTBLOCK levels. Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_6fx/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 037234a..16bc03b 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -13,3 +13,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 32f6e8c..e6c8256 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -14,3 +14,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/35994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28 Gerrit-Change-Number: 35994 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: set FSP param to enable or skip GOP
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36350 ) Change subject: soc/intel/skylake: set FSP param to enable or skip GOP ...................................................................... soc/intel/skylake: set FSP param to enable or skip GOP Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36350/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 55fedd3..feb1339 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -501,6 +501,13 @@ params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } + /* Only initialize graphics if supported and enabled */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + soc_irq_settings(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7 Gerrit-Change-Number: 36350 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Build test with VBOOT
by Nico Huber (Code Review) 02 Nov '19

02 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36238 ) Change subject: nb/intel/gm45: Build test with VBOOT ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7 Gerrit-Change-Number: 36238 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 16:07:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: pmclib: add API to get ETR register address
by Nico Huber (Code Review) 02 Nov '19

02 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36565 ) Change subject: soc/intel/common: pmclib: add API to get ETR register address ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36565/3/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/36565/3/src/soc/intel/common/block… PS3, Line 173: mmconf It's still only MMCONF on SKL. -- To view, visit https://review.coreboot.org/c/coreboot/+/36565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Gerrit-Change-Number: 36565 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icelake: lockdown: lock global reset
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36572 ) Change subject: soc/intel/icelake: lockdown: lock global reset ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b Gerrit-Change-Number: 36572 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:54:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: lockdown: lock global reset
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36571 ) Change subject: soc/intel/cannonlake: lockdown: lock global reset ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Gerrit-Change-Number: 36571 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:54:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: pmclib: make use of the new ETR address API
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 ) Change subject: soc/intel/common: pmclib: make use of the new ETR address API ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Gerrit-Change-Number: 36570 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:54:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: add soc implementation for ETR address API
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36569 ) Change subject: soc/intel/skylake: add soc implementation for ETR address API ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Gerrit-Change-Number: 36569 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:54:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: add soc implementation for ETR address API
by Michael Niewöhner (Code Review) 02 Nov '19

02 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36566 ) Change subject: soc/intel/apollolake: add soc implementation for ETR address API ...................................................................... Uploaded patch set 3: Patch Set 2 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1832f5f14055fc3dbb502289035130ca7a5d6d33 Gerrit-Change-Number: 36566 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 14:54:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2019