Change in coreboot[master]: soc/intel/skylake: set FSP param to enable or skip GOP

[Michael Niewöhner (Code Review)]

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

soc/intel/skylake: set FSP param to enable or skip GOP

Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/chip_fsp20.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36350/1

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 55fedd3..feb1339 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -501,6 +501,13 @@
    	params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
    }

+	/* Only initialize graphics if supported and enabled */
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+		params->PeiGraphicsPeimInit = 1;
+	else
+		params->PeiGraphicsPeimInit = 0;
+
    soc_irq_settings(params);
 }

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Patch Set 1: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Uploaded patch set 2.

[Michael Niewöhner (Code Review)]

Hello Kyösti Mälkki, Naresh Solanki, Patrick Rudolph, Subrata Banik, Maxim Polyakov, Paul Menzel, Hung-Te Lin, build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36350

to look at the new patch set (#2).

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

soc/intel/skylake: set FSP param to enable or skip GOP

Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/chip_fsp20.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36350/2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Patch Set 2: Code-Review+2

[Michael Niewöhner (Code Review)]

Hello Kyösti Mälkki, Naresh Solanki, Patrick Rudolph, Subrata Banik, Maxim Polyakov, Paul Menzel, Hung-Te Lin, build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36350

to look at the new patch set (#3).

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

soc/intel/skylake: set FSP param to enable or skip GOP

Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/chip.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36350/3

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Uploaded patch set 3.

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Patch Set 3: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

Patch Set 3: Code-Review+2

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36350 )

Change subject: soc/intel/skylake: set FSP param to enable or skip GOP
......................................................................

soc/intel/skylake: set FSP param to enable or skip GOP

Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.

Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36350
Reviewed-by: Patrick Georgi 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/chip.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index c4f4e50..7987f46 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -509,6 +509,12 @@
    	params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
    }

+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+		params->PeiGraphicsPeimInit = 1;
+	else
+		params->PeiGraphicsPeimInit = 0;
+
    soc_irq_settings(params);
 }