November 2019 - coreboot-gerrit

Change in coreboot[master]: nb/intel/gm45: Build test with VBOOT
by Arthur Heymans (Code Review) Nov. 2, 2019

Nov. 2, 2019

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36238 to look at the new patch set (#6). Change subject: nb/intel/gm45: Build test with VBOOT ...................................................................... nb/intel/gm45: Build test with VBOOT Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- R configs/config.lenovo_t400_vboot_and_debug 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36238/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/36238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7 Gerrit-Change-Number: 36238 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is mostly optional
by Kyösti Mälkki (Code Review) Nov. 2, 2019

Nov. 2, 2019

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is mostly optional ...................................................................... timestamps: COLLECT_TIMESTAMPS is mostly optional It is a user-visible option and enabled by default for ARCH_X86, some consider it as debugging aid only. Therefore platform design should not depend on it. It must remain selected with CHROMEOS and boards are allowed to explicitly select it as well. For siemens/mc_bdx1,mc_aplX boot time will be increased due the use of get_us_since_boot() with COLLECT_TIMESTAMPS=n. When unable to determine if N seconds has elapsed from boot, this turns into a delay of N seconds. Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/skylake/Kconfig 5 files changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6f75e9e..d87d634 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -38,7 +38,6 @@ select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE select UDELAY_TSC - select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0e55937..0d6f2ff 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -54,7 +54,6 @@ select HAVE_USBDEBUG_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE - select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a1d3c07..b54528f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -40,7 +40,6 @@ # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d6438f..5053790 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -14,7 +14,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_IN_BLOB_REPO select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d47572b..f9f6f93 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,7 +26,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: pmclib: add API to get ETR register MMCONF address
by Nico Huber (Code Review) Nov. 2, 2019

Nov. 2, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36565 ) Change subject: soc/intel/common: pmclib: add API to get ETR register MMCONF address ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block… PS1, Line 173: uintptr_t Why is this not a pointer? If common code should use it, it will also make assumptions on the register width.... -- To view, visit https://review.coreboot.org/c/coreboot/+/36565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Gerrit-Change-Number: 36565 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:31:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: pmclib: add API to get ETR register MMCONF address
by Nico Huber (Code Review) Nov. 2, 2019

Nov. 2, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36565 ) Change subject: soc/intel/common: pmclib: add API to get ETR register MMCONF address ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block… PS1, Line 173: uintptr_t soc_read_pmc_etr_mmconf_addr(void); I guess Aaron's idea was to have a common interface for all platforms, i.e. just return the address, no matter if that is in MMCONF or MMIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/36565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Gerrit-Change-Number: 36565 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/pch: move EBDA Kconfig to soc level
by Nico Huber (Code Review) Nov. 2, 2019

Nov. 2, 2019

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36409 ) Change subject: soc/intel/common/pch: move EBDA Kconfig to soc level ...................................................................... soc/intel/common/pch: move EBDA Kconfig to soc level EBDA is not PCH related, thus move the Kconfig to the appropriate socs. Change-Id: I216871ad1a8dd5bc294062a4e9b54eb51f71b781 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36409 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/pch/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1f53b1..941c150 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -88,6 +88,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 7ece9549..993593d 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -19,7 +19,6 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP - select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 4ae043a..993e9b2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -43,6 +43,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3e9d659..d47572b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -59,6 +59,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL -- To view, visit https://review.coreboot.org/c/coreboot/+/36409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I216871ad1a8dd5bc294062a4e9b54eb51f71b781 Gerrit-Change-Number: 36409 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Nico Huber (Code Review) Nov. 2, 2019

Nov. 2, 2019

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: Code-Review+1 Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be somewhere between FSP 2.0 and 2.1. Subrata, do you know what the lack of SkipMpInit for CNL implies? -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:19:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) Nov. 2, 2019

Nov. 2, 2019

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 ) Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG@7 PS2, Line 7: icelake Nico Huber: > Patch Set 2: -Code-Review > > Thinking about this, MP init works different with FSP2.1, so it > should be tested, IMHO. Might even be a no-op. -- To view, visit https://review.coreboot.org/c/coreboot/+/36357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib728e61bc874acf505348e72c00a99e0a6efd2cb Gerrit-Change-Number: 36357 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:14:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) Nov. 2, 2019

Nov. 2, 2019

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 ) Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: > Patch Set 2: -Code-Review > > Thinking about this, MP init works different with FSP2.1, so it > should be tested, IMHO. Might even be a no-op. ACK -- To view, visit https://review.coreboot.org/c/coreboot/+/36357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib728e61bc874acf505348e72c00a99e0a6efd2cb Gerrit-Change-Number: 36357 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 13:14:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) Nov. 2, 2019

Nov. 2, 2019

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36355 ) Change subject: soc/intel/skylake: set LT_LOCK_MEMORY at end of POST ...................................................................... soc/intel/skylake: set LT_LOCK_MEMORY at end of POST Use the new common function to set LT_LOCK_MEMORY at end of POST to protect SMM in accordance to Intel BWG. Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/finalize.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36355/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 4cc9c83..58a8701 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -123,6 +124,9 @@ reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); } static void soc_finalize(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/36355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8 Gerrit-Change-Number: 36355 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel: common,apl,skl: remove orphaned memory locking API
by Nico Huber (Code Review) Nov. 2, 2019

Nov. 2, 2019

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36515 ) Change subject: soc/intel: common,apl,skl: remove orphaned memory locking API ...................................................................... soc/intel: common,apl,skl: remove orphaned memory locking API Remove the now orphaned memory locking API that was replaced by a Kconfig-based approach. Change-Id: Iebc45f514c576d77f90f558151d25c21f0554779 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36515 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/skylake/cpu.c 3 files changed, 0 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 0022b3a..6e826b8 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -291,9 +291,3 @@ CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); } - -void cpu_lock_sgx_memory(void) -{ - /* Do nothing because MCHECK while loading microcode and enabling - * IA untrusted mode takes care of necessary locking */ -} diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 693dd20..36634d3 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -19,12 +19,6 @@ #include <soc/nvs.h> /* - * Lock SGX memory. - * CPU specific code needs to provide the implementation. - */ -void cpu_lock_sgx_memory(void); - -/* * Configure core PRMRR. * PRMRR needs to configured first on all cores and then * call sgx_configure() for all cores to init SGX. diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ac1451..bfed528 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -575,14 +575,3 @@ return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } - -void cpu_lock_sgx_memory(void) -{ - msr_t msr; - - msr = rdmsr(MSR_LT_LOCK_MEMORY); - if ((msr.lo & 1) == 0) { - msr.lo |= 1; /* Lock it */ - wrmsr(MSR_LT_LOCK_MEMORY, msr); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc45f514c576d77f90f558151d25c21f0554779 Gerrit-Change-Number: 36515 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0