Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36238
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Change subject: nb/intel/gm45: Build test with VBOOT
......................................................................
nb/intel/gm45: Build test with VBOOT
Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
R configs/config.lenovo_t400_vboot_and_debug
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36238/6
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36565 )
Change subject: soc/intel/common: pmclib: add API to get ETR register MMCONF address
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block…
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block…
PS1, Line 173: uintptr_t
Why is this not a pointer? If common code should use it, it will also make
assumptions on the register width....
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36565 )
Change subject: soc/intel/common: pmclib: add API to get ETR register MMCONF address
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block…
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/36565/1/src/soc/intel/common/block…
PS1, Line 173: uintptr_t soc_read_pmc_etr_mmconf_addr(void);
I guess Aaron's idea was to have a common interface for all platforms,
i.e. just return the address, no matter if that is in MMCONF or MMIO.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 )
Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2: Code-Review+1
Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be
somewhere between FSP 2.0 and 2.1.
Subrata, do you know what the lack of SkipMpInit for CNL implies?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 )
Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/36357/2//COMMIT_MSG@7
PS2, Line 7: icelake
Nico Huber:
> Patch Set 2: -Code-Review
>
> Thinking about this, MP init works different with FSP2.1, so it
> should be tested, IMHO. Might even be a no-op.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36357 )
Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
......................................................................
Patch Set 2:
> Patch Set 2: -Code-Review
>
> Thinking about this, MP init works different with FSP2.1, so it
> should be tested, IMHO. Might even be a no-op.
ACK
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Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36355 )
Change subject: soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
......................................................................
soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
Use the new common function to set LT_LOCK_MEMORY at end of POST to
protect SMM in accordance to Intel BWG.
Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/skylake/finalize.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36355/1
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 4cc9c83..58a8701 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -20,6 +20,7 @@
#include <bootstate.h>
#include <console/console.h>
#include <console/post_codes.h>
+#include <cpu/x86/mp.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <intelblocks/cpulib.h>
@@ -123,6 +124,9 @@
reg8 |= SMI_LOCK;
pci_write_config8(dev, GEN_PMCON_A, reg8);
}
+
+ /* Lock chipset memory registers to protect SMM */
+ mp_run_on_all_cpus(cpu_lt_lock_memory, NULL);
}
static void soc_finalize(void *unused)
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