coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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2418 discussions

Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 02 Nov '19

02 Nov '19

Kyösti Mälkki has removed Huang Jin from this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... Removed reviewer Huang Jin. -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 02 Nov '19

02 Nov '19

Kyösti Mälkki has removed David Guckian from this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... Removed reviewer David Guckian. -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 02 Nov '19

02 Nov '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG@15 PS15, Line 15: implementation for three platforms. > I'm not sure that's true across the board. […] Well I know for AGESA/PI rdtscll() rescales during raminit. That's why they are not at TSC_MONOTONIC_TIMER yet. For the duration of coreboot execution, do we need to care about C/P-states or other clock throttling? Then again, I belive LAPIC_MONOTONIC_TIMER did not work either for AMD. Marshall, Martin; do you reemember something about this on amd/stoneyridge? Like udelay() failing with UART8250MEM. -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Nov 2019 06:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Remove UDELAY_LAPIC_FIXED_FSB
by Kyösti Mälkki (Code Review) 02 Nov '19

02 Nov '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36526 ) Change subject: soc/amd/stoneyridge: Remove UDELAY_LAPIC_FIXED_FSB ...................................................................... soc/amd/stoneyridge: Remove UDELAY_LAPIC_FIXED_FSB We only need this defined with udelay() implementation on top of LAPIC_MONOTONIC_TIMER. Change-Id: I490245fa0d57de3a6e8609e735f668626cf1201e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36526 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 72719d7..0e55937 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -86,10 +86,6 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config UDELAY_LAPIC_FIXED_FSB - int - default 200 - # TODO: Sync these with definitions in PI vendorcode. # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. -- To view, visit https://review.coreboot.org/c/coreboot/+/36526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I490245fa0d57de3a6e8609e735f668626cf1201e Gerrit-Change-Number: 36526 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80
by Kyösti Mälkki (Code Review) 02 Nov '19

02 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36507 ) Change subject: cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80 ...................................................................... cpu/x86: Move calibrate_tsc_with_pit() to drivers/pc80 Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/tsc/delay_tsc.c M src/drivers/pc80/pc/Makefile.inc M src/drivers/pc80/pc/i8254.c M src/include/pc80/i8254.h 4 files changed, 84 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36507/1 diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0784822..29cd37e 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -12,90 +12,12 @@ */ #include <arch/early_variables.h> -#include <console/console.h> -#include <arch/io.h> #include <cpu/x86/tsc.h> +#include <pc80/i8254.h> #include <smp/spinlock.h> #include <delay.h> #include <thread.h> -static unsigned long clocks_per_usec CAR_GLOBAL; - -#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ - -/* ------ Calibrate the TSC ------- - * Too much 64-bit arithmetic here to do this cleanly in C, and for - * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) - * output busy loop as low as possible. We avoid reading the CTC registers - * directly because of the awkward 8-bit access mechanism of the 82C54 - * device. - */ - -#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ -#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ - -static unsigned long calibrate_tsc_with_pit(void) -{ - /* Set the Gate high, disable speaker */ - outb((inb(0x61) & ~0x02) | 0x01, 0x61); - - /* - * Now let's take care of CTC channel 2 - * - * Set the Gate high, program CTC channel 2 for mode 0, - * (interrupt on terminal count mode), binary count, - * load 5 * LATCH count, (LSB and MSB) to begin countdown. - */ - outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ - - outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */ - outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */ - - { - tsc_t start; - tsc_t end; - unsigned long count; - - start = rdtsc(); - count = 0; - do { - count++; - } while ((inb(0x61) & 0x20) == 0); - end = rdtsc(); - - /* Error: ECTCNEVERSET */ - if (count <= 1) - goto bad_ctc; - - /* 64-bit subtract - gcc just messes up with long longs */ - __asm__("subl %2,%0\n\t" - "sbbl %3,%1" - : "=a" (end.lo), "=d" (end.hi) - : "g" (start.lo), "g" (start.hi), - "0" (end.lo), "1" (end.hi)); - - /* Error: ECPUTOOFAST */ - if (end.hi) - goto bad_ctc; - - - /* Error: ECPUTOOSLOW */ - if (end.lo <= CALIBRATE_DIVISOR) - goto bad_ctc; - - return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); - } - - /* - * The CTC wasn't reliable: we got a hit on the very first read, - * or the CPU was so fast/slow that the quotient wouldn't fit in - * 32 bits.. - */ -bad_ctc: - printk(BIOS_ERR, "bad_ctc\n"); - return 0; -} - static unsigned long calibrate_tsc(void) { if (CONFIG(TSC_CONSTANT_RATE)) diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 8c348e3..1b26984 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_ARCH_X86),y) ramstage-y += isa-dma.c -ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c romstage-$(CONFIG_UDELAY_IO) += udelay_io.c @@ -9,4 +8,10 @@ ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c +bootblock-y += i8254.c +verstage-y += i8254.c +romstage-y += i8254.c +ramstage-y += i8254.c +smm-y += i8254.c + endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 53d880c..8e15d4d 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -12,6 +12,8 @@ */ #include <arch/io.h> +#include <commonlib/helpers.h> +#include <cpu/x86/tsc.h> #include <pc80/i8254.h> /* Initialize i8254 timers */ @@ -46,3 +48,77 @@ ; } #endif + +#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ + +/* ------ Calibrate the TSC ------- + * Too much 64-bit arithmetic here to do this cleanly in C, and for + * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) + * output busy loop as low as possible. We avoid reading the CTC registers + * directly because of the awkward 8-bit access mechanism of the 82C54 + * device. + */ + +#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ +#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ + +unsigned long calibrate_tsc_with_pit(void) +{ + /* Set the Gate high, disable speaker */ + outb((inb(0x61) & ~0x02) | 0x01, 0x61); + + /* + * Now let's take care of CTC channel 2 + * + * Set the Gate high, program CTC channel 2 for mode 0, + * (interrupt on terminal count mode), binary count, + * load 5 * LATCH count, (LSB and MSB) to begin countdown. + */ + outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ + + outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */ + outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */ + + { + tsc_t start; + tsc_t end; + unsigned long count; + + start = rdtsc(); + count = 0; + do { + count++; + } while ((inb(0x61) & 0x20) == 0); + end = rdtsc(); + + /* Error: ECTCNEVERSET */ + if (count <= 1) + goto bad_ctc; + + /* 64-bit subtract - gcc just messes up with long longs */ + __asm__("subl %2,%0\n\t" + "sbbl %3,%1" + : "=a" (end.lo), "=d" (end.hi) + : "g" (start.lo), "g" (start.hi), + "0" (end.lo), "1" (end.hi)); + + /* Error: ECPUTOOFAST */ + if (end.hi) + goto bad_ctc; + + + /* Error: ECPUTOOSLOW */ + if (end.lo <= CALIBRATE_DIVISOR) + goto bad_ctc; + + return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); + } + + /* + * The CTC wasn't reliable: we got a hit on the very first read, + * or the CPU was so fast/slow that the quotient wouldn't fit in + * 32 bits.. + */ +bad_ctc: + return 0; +} diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index 794945c..21e47c2 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -55,5 +55,6 @@ #define PPCB_T2GATE 0x01 /* Bit 0 */ void setup_i8254(void); +unsigned long calibrate_tsc_with_pit(void); #endif /* PC80_I8254_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8d8dc23ee0b51d62c83f5ba640b3a9aea4e744b Gerrit-Change-Number: 36507 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Shelley Chen (Code Review) 02 Nov '19

02 Nov '19

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/35907/5/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/c/coreboot/+/35907/5/src/mainboard/google/hatch… PS5, Line 106: register "generic.reset_delay_ms" = "120" > Let's not to change reset_delay until thee next build is done: b/142316026. Kane can you please revert this change until the next build as Philip requested? -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Nov 2019 05:23:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Ravishankar Sarawadi (Code Review) 02 Nov '19

02 Nov '19

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, John Zhao, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36225 to look at the new patch set (#9). Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... soc/intel/common: Include Tigerlake device IDs Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 20 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36225/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 9 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Subrata Banik (Code Review) 02 Nov '19

02 Nov '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36225 ) Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... Patch Set 8: can you please fix -1 verified issue ? -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Sat, 02 Nov 2019 02:22:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi
by Subrata Banik (Code Review) 02 Nov '19

02 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36457 ) Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ...................................................................... soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi This patch creates a common instance of globalnvs.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer globalnvs.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/globalnvs.asl R src/soc/intel/common/block/acpi/acpi/globalnvs.asl 9 files changed, 8 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36457/1 diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index ab0b977..8a43784 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5ffdf18 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a7..344e4a7 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 58e0704..22e283f 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d23..5f4a349 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6..c5f1136 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469fa..15890f1 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl deleted file mode 100644 index 940cf43..0000000 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name (\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count - PPCM, 8, // 0x04 - Max PPC State - TLVL, 8, // 0x05 - Throttle Level Limit - LIDS, 8, // 0x06 - LID State - PWRS, 8, // 0x07 - AC Power State - CBMC, 32, // 0x08 - 0x0b AC Power State - PM1I, 64, // 0x0c - 0x13 PM1 wake status bit - GPEI, 64, // 0x14 - 0x17 GPE wake status bit - DPTE, 8, // 0x1c - Enable DPTF - NHLA, 64, // 0x1d - 0x24 NHLT Address - NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier - U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap - U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap - UIOR, 8, // 0x2f - UART debug controller init on S3 resume - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl similarity index 96% rename from src/soc/intel/icelake/acpi/globalnvs.asl rename to src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 678ce5a..8e8241b 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count -- To view, visit https://review.coreboot.org/c/coreboot/+/36457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Gerrit-Change-Number: 36457 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Aaron Durbin (Code Review) 01 Nov '19

01 Nov '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 16 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 22:27:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2019