coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC
by Ravishankar Sarawadi (Code Review) 01 Nov '19

01 Nov '19

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36248 ) Change subject: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC ...................................................................... Patch Set 3: (1 comment) I am working on build and boot recipe in parallel using tglrvp board. https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/gp… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/gp… PS3, Line 28: PAD_CFG0_LOGICAL_RESET_DSW_PWROK revert this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/36248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04436a12e3fdd80e1f4ac0ecf73d78e467e4fe9f Gerrit-Change-Number: 36248 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Nov 2019 21:38:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Ravishankar Sarawadi (Code Review) 01 Nov '19

01 Nov '19

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36225 ) Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… PS7, Line 57: #define PAD_CFG0_LOGICAL_RESET_DSW_PWROK (0U << 30) > seems unrelated Done https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… File src/soc/intel/common/block/lpc/lpc_def.h: https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… PS7, Line 40: #define LPC_BC_LE (1 << 2) /* LE */ > seems unrelated Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Nov 2019 21:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Ravishankar Sarawadi (Code Review) 01 Nov '19

01 Nov '19

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, John Zhao, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36225 to look at the new patch set (#8). Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... soc/intel/common: Include Tigerlake device IDs Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/lpc/lpc_def.h M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 22 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36225/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 8 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/emulation/qemu-riscv: Initialize cbmem in romstage
by Arthur Heymans (Code Review) 01 Nov '19

01 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36446 ) Change subject: mb/emulation/qemu-riscv: Initialize cbmem in romstage ...................................................................... mb/emulation/qemu-riscv: Initialize cbmem in romstage Change-Id: I00f8e3b315e57a5c042889f48450f79d263f24b1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-riscv/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36446/1 diff --git a/src/mainboard/emulation/qemu-riscv/romstage.c b/src/mainboard/emulation/qemu-riscv/romstage.c index 684b249..d9b87c9 100644 --- a/src/mainboard/emulation/qemu-riscv/romstage.c +++ b/src/mainboard/emulation/qemu-riscv/romstage.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <program_loading.h> void main(void) { console_init(); + cbmem_initialize_empty(); run_ramstage(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f8e3b315e57a5c042889f48450f79d263f24b1 Gerrit-Change-Number: 36446 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Build vboot library with same .a that depthcharge uses
by Tim Wawrzynczak (Code Review) 01 Nov '19

01 Nov '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36341 ) Change subject: security/vboot: Build vboot library with same .a that depthcharge uses ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi… File src/security/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi… PS14, Line 113: VB_ > Can we call this VBOOT_LIB? You bet -- To view, visit https://review.coreboot.org/c/coreboot/+/36341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I905b781c3596965ec7ef45a2a7eafe15fdd4d9cc Gerrit-Change-Number: 36341 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 19:34:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is mostly optional
by Marshall Dawson (Code Review) 01 Nov '19

01 Nov '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is mostly optional ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 19:34:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: timestamps: COLLECT_TIMESTAMPS is mostly optional
by Aaron Durbin (Code Review) 01 Nov '19

01 Nov '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36527 ) Change subject: timestamps: COLLECT_TIMESTAMPS is mostly optional ...................................................................... Patch Set 5: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/36527/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/36527/4//COMMIT_MSG@9 PS4, Line 9: enabled by default > for ARCH_X86 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3 Gerrit-Change-Number: 36527 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Nov 2019 19:09:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Aaron Durbin (Code Review) 01 Nov '19

01 Nov '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... Patch Set 15: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG@15 PS15, Line 15: implementation for three platforms. I'm not sure that's true across the board. May want to mention which platforms you were referring to? Your call. -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Nov 2019 19:08:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Tigerlake device IDs
by Patrick Rudolph (Code Review) 01 Nov '19

01 Nov '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36225 ) Change subject: soc/intel/common: Include Tigerlake device IDs ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… PS7, Line 57: #define PAD_CFG0_LOGICAL_RESET_DSW_PWROK (0U << 30) seems unrelated https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… File src/soc/intel/common/block/lpc/lpc_def.h: https://review.coreboot.org/c/coreboot/+/36225/7/src/soc/intel/common/block… PS7, Line 40: #define LPC_BC_LE (1 << 2) /* LE */ seems unrelated -- To view, visit https://review.coreboot.org/c/coreboot/+/36225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19047354718bdf510dffee4659d885f1313a751b Gerrit-Change-Number: 36225 Gerrit-PatchSet: 7 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Nov 2019 18:40:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) 01 Nov '19

01 Nov '19

Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Patrick Georgi, HAOUAS Elyes, Vanny E, Huang Jin, Philipp Deppenwiese, Nico Huber, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33928 to look at the new patch set (#15). Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/cpu.c M src/arch/x86/timestamp.c M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/via/nano/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/drivers/pc80/pc/i8254.c M src/include/cpu/x86/tsc.h M src/northbridge/via/vx900/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 32 files changed, 43 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33928/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 15 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2019