Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36248 )
Change subject: soc/intel/tigerlake: Update GPIOs for Tigerlake SOC
......................................................................
Patch Set 3:
(1 comment)
I am working on build and boot recipe in parallel using tglrvp board.
https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/gp…
File src/soc/intel/tigerlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/36248/3/src/soc/intel/tigerlake/gp…
PS3, Line 28: PAD_CFG0_LOGICAL_RESET_DSW_PWROK
revert this change.
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Hello Raj Astekar, Patrick Rudolph, Subrata Banik, John Zhao, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36225
to look at the new patch set (#8).
Change subject: soc/intel/common: Include Tigerlake device IDs
......................................................................
soc/intel/common: Include Tigerlake device IDs
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs.
BUG=None
BRANCH=None
TEST=Build 'emerge-tglrvp coreboot'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Change-Id: I19047354718bdf510dffee4659d885f1313a751b
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/lpc/lpc_def.h
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
22 files changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36225/8
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36341 )
Change subject: security/vboot: Build vboot library with same .a that depthcharge uses
......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi…
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/36341/14/src/security/vboot/Makefi…
PS14, Line 113: VB_
> Can we call this VBOOT_LIB?
You bet
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 )
Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
......................................................................
Patch Set 15: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/33928/15//COMMIT_MSG@15
PS15, Line 15: implementation for three platforms.
I'm not sure that's true across the board. May want to mention which platforms you were referring to? Your call.
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Hello Werner Zeh, Aaron Durbin, Patrick Rudolph, HAOUAS Elyes, Julius Werner, Arthur Heymans, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36527
to look at the new patch set (#5).
Change subject: timestamps: COLLECT_TIMESTAMPS is mostly optional
......................................................................
timestamps: COLLECT_TIMESTAMPS is mostly optional
It is a user-visible option and enabled by default for ARCH_X86,
some consider it as debugging aid only. Therefore platform design
should not depend on it.
It must remain selected with CHROMEOS and boards are allowed
to explicitly select it as well.
For siemens/mc_bdx1,mc_aplX boot time will be increased due
the use of get_us_since_boot() with COLLECT_TIMESTAMPS=n.
When unable to determine if N seconds has elapsed from boot,
this turns into a delay of N seconds.
Change-Id: I6ee4195d266440143344781d39db9578cd8bdcb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/stoneyridge/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/braswell/Kconfig
M src/soc/intel/skylake/Kconfig
5 files changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36527/5
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