Change in coreboot[master]: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi
This patch creates a common instance of globalnvs.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer globalnvs.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/globalnvs.asl R src/soc/intel/common/block/acpi/acpi/globalnvs.asl 9 files changed, 8 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36457/1
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index ab0b977..8a43784 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5ffdf18 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a7..344e4a7 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 58e0704..22e283f 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d23..5f4a349 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6..c5f1136 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469fa..15890f1 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl deleted file mode 100644 index 940cf43..0000000 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name (\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count - PPCM, 8, // 0x04 - Max PPC State - TLVL, 8, // 0x05 - Throttle Level Limit - LIDS, 8, // 0x06 - LID State - PWRS, 8, // 0x07 - AC Power State - CBMC, 32, // 0x08 - 0x0b AC Power State - PM1I, 64, // 0x0c - 0x13 PM1 wake status bit - GPEI, 64, // 0x14 - 0x17 GPE wake status bit - DPTE, 8, // 0x1c - Enable DPTF - NHLA, 64, // 0x1d - 0x24 NHLT Address - NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier - U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap - U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap - UIOR, 8, // 0x2f - UART debug controller init on S3 resume - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl similarity index 96% rename from src/soc/intel/icelake/acpi/globalnvs.asl rename to src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 678ce5a..8e8241b 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
Patch Set 1: Code-Review+1
Could you also have a look at synchronizing GNVS between targets? I have the impression that a lot goes unused in for instance skylake.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
Patch Set 1:
You might want to move the C header defining GNVS to a common place in the same CL.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+1
Could you also have a look at synchronizing GNVS between targets? I have the impression that a lot goes unused in for instance skylake.
Sure Arthur we can take a look into SKL code as well, but can we do that with little less priority (if needed i will raise a ticket in cb.org) compare to unblock TGL upstream code readiness work that we have in hand ?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
Could you also have a look at synchronizing GNVS between targets? I have the impression that a lot goes unused in for instance skylake.
Sure Arthur we can take a look into SKL code as well, but can we do that with little less priority (if needed i will raise a ticket in cb.org) compare to unblock TGL upstream code readiness work that we have in hand ?
Sure, no problem.
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Aamir Bohra, Ravishankar Sarawadi, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36457
to look at the new patch set (#2).
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/globalnvs.asl M src/soc/intel/cannonlake/include/soc/nvs.h R src/soc/intel/common/block/acpi/acpi/globalnvs.asl A src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/icelake/include/soc/nvs.h 12 files changed, 58 insertions(+), 123 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36457/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... PS3, Line 21: #include <intelblocks/nvs.h> Is it possible to include this directly in other files instead of this header?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... PS3, Line 21: #include <intelblocks/nvs.h>
Is it possible to include this directly in other files instead of this header?
other C files are looking for soc/nvs.h hence thought of making minimum changes to achieve this
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... PS3, Line 21: #include <intelblocks/nvs.h>
other C files are looking for soc/nvs.h hence thought of making minimum changes to achieve this
Ok. Getting rid of it needs to happen when unifying nvs.h but that's outside the scope here.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/36457/3/src/soc/intel/cannonlake/in... PS3, Line 21: #include <intelblocks/nvs.h>
other C files are looking for soc/nvs.h hence thought of making minimum changes to achieve this […]
yes
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 3: Code-Review+2
Thanks!
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/globalnvs.asl M src/soc/intel/cannonlake/include/soc/nvs.h R src/soc/intel/common/block/acpi/acpi/globalnvs.asl A src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/icelake/include/soc/nvs.h 12 files changed, 58 insertions(+), 123 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index d5c709e..4318dc3 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 91d3704..0a092cf 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index 9329b58..6247829 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 743a2f0..9a5c787 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index acc4c7c..9a519c0 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index f830035..1d7216a 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 6657a6e..152f038 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl deleted file mode 100644 index 940cf43..0000000 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name (\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count - PPCM, 8, // 0x04 - Max PPC State - TLVL, 8, // 0x05 - Throttle Level Limit - LIDS, 8, // 0x06 - LID State - PWRS, 8, // 0x07 - AC Power State - CBMC, 32, // 0x08 - 0x0b AC Power State - PM1I, 64, // 0x0c - 0x13 PM1 wake status bit - GPEI, 64, // 0x14 - 0x17 GPE wake status bit - DPTE, 8, // 0x1c - Enable DPTF - NHLA, 64, // 0x1d - 0x24 NHLT Address - NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier - U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap - U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap - UIOR, 8, // 0x2f - UART debug controller init on S3 resume - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index 1cb22fa..3bd7bc2 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -18,34 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_
-#include <commonlib/helpers.h> -#include <vendorcode/google/chromeos/gnvs.h> - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - 0x01 Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 pcnt; /* 0x03 - Processor Count */ - u8 ppcm; /* 0x04 - Max PPC State */ - u8 tlvl; /* 0x05 - Throttle Level Limit */ - u8 lids; /* 0x06 - LID State */ - u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ - u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ - u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ - u8 dpte; /* 0x1c - Enable DPTF */ - u64 nhla; /* 0x1d - 0x24 NHLT Address */ - u32 nhll; /* 0x25 - 0x28 NHLT Length */ - u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ - u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ - u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ - u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - +#include <intelblocks/nvs.h>
#endif diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl similarity index 96% rename from src/soc/intel/icelake/acpi/globalnvs.asl rename to src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 678ce5a..8e8241b 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h new file mode 100644 index 0000000..5f367b6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_NVS_H +#define SOC_INTEL_COMMON_BLOCK_NVS_H + +#include <commonlib/helpers.h> +#include <vendorcode/google/chromeos/gnvs.h> + +typedef struct global_nvs_t { + /* Miscellaneous */ + u16 osys; /* 0x00 - 0x01 Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 pcnt; /* 0x03 - Processor Count */ + u8 ppcm; /* 0x04 - Max PPC State */ + u8 tlvl; /* 0x05 - Throttle Level Limit */ + u8 lids; /* 0x06 - LID State */ + u8 pwrs; /* 0x07 - AC Power State */ + u32 cbmc; /* 0x08 - 0xb AC Power State */ + u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ + u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ + u8 dpte; /* 0x1c - Enable DPTF */ + u64 nhla; /* 0x1d - 0x24 NHLT Address */ + u32 nhll; /* 0x25 - 0x28 NHLT Length */ + u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ + u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ + u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ + u8 uior; /* 0x2f - UART debug controller init on S3 resume */ + u8 unused[208]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __packed global_nvs_t; +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + +#endif diff --git a/src/soc/intel/icelake/include/soc/nvs.h b/src/soc/intel/icelake/include/soc/nvs.h index b2d903a..c855df0 100644 --- a/src/soc/intel/icelake/include/soc/nvs.h +++ b/src/soc/intel/icelake/include/soc/nvs.h @@ -16,34 +16,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_
-#include <commonlib/helpers.h> -#include <vendorcode/google/chromeos/gnvs.h> - -typedef struct global_nvs_t { - /* Miscellaneous */ - u16 osys; /* 0x00 - 0x01 Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 pcnt; /* 0x03 - Processor Count */ - u8 ppcm; /* 0x04 - Max PPC State */ - u8 tlvl; /* 0x05 - Throttle Level Limit */ - u8 lids; /* 0x06 - LID State */ - u8 pwrs; /* 0x07 - AC Power State */ - u32 cbmc; /* 0x08 - 0xb AC Power State */ - u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ - u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ - u8 dpte; /* 0x1c - Enable DPTF */ - u64 nhla; /* 0x1d - 0x24 NHLT Address */ - u32 nhll; /* 0x25 - 0x28 NHLT Length */ - u16 cid1; /* 0x29 - 0x2a Wifi Country Identifier */ - u16 u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */ - u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ - u8 uior; /* 0x2f - UART debug controller init on S3 resume */ - u8 unused[208]; - - /* ChromeOS specific (0x100 - 0xfff) */ - chromeos_acpi_t chromeos; -} __packed global_nvs_t; -check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - +#include <intelblocks/nvs.h>
#endif
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/6/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
PS6: If NVS is moved completely to common code, why retain this placeholder file? Isn't it better to just update references to this under soc/intel/X to include intelblocks/nvs.h directly?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/6/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
PS6:
If NVS is moved completely to common code, why retain this placeholder file? Isn't it better to just […]
I see a comment on earlier patchset related to this. I think we should get rid of this file in the soc/ paths and mainboards for those SoC which are already moved to use common code.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/ ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36457/6/src/soc/intel/cannonlake/in... File src/soc/intel/cannonlake/include/soc/nvs.h:
PS6:
I see a comment on earlier patchset related to this. […]
so far we could able to move nvs.asl and nvs.h for CNL and ICL but SKL/APL are too different to call it common
btw, soc/nvs.h is getting called from intelblocks/ common code as well hence unless we move all common code supported soc into real common place, we really can't get rid of this wrapper file
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Furquan Shaikh (Code Review)
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Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)