Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 )
Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
......................................................................
Patch Set 17:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33928/12//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/33928/12//COMMIT_MSG@15
PS12, Line 15: For via/epia-m850, switch romstage udelay() from UDELAY_IO to
: UDELAY_TSC.
> Well, via/epia-m850 should have been separate change, not squashed here. […]
Improved the commit message about why via/epia-m850 was touched here.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33928 )
Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33928/14//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/33928/14//COMMIT_MSG@7
PS14, Line 7: cpu/x86/tsc: Replace TSC_CONSTANT_RATE with UNKNOWN_TSC_RATE
> Could you please add that info to the commit description?
Done
https://review.coreboot.org/c/coreboot/+/33928/14/src/cpu/x86/tsc/delay_tsc…
File src/cpu/x86/tsc/delay_tsc.c:
https://review.coreboot.org/c/coreboot/+/33928/14/src/cpu/x86/tsc/delay_tsc…
PS14, Line 23: (void)tsc_freq_mhz();
> I am anticipating the UNKNOWN_TSC_RATE implementation in pc80/i8254.c could be removed soon. […]
Ack
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36581 )
Change subject: soc/intel/{braswell,baytrail}: Use sb/common/intel/platform.asl
......................................................................
Patch Set 2: Code-Review+1
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig@161
PS1, Line 161: depends on BOOTBLOCK_CONSOLE
Doesn't seem to make sense. If bootblock console is disabled, we'd run
into the same issue in romstage or even still in ramstage (in case of the
500ms set in the next patch).
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36592 )
Change subject: mb/supermicro/x11-lga1151-series: use new console delay option
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 )
Change subject: soc/intel/common: pmclib: make use of the new ETR address API
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
PS4, Line 432: void pmc_global_reset_lock(void)
: {
: uint32_t *etr = soc_read_pmc_etr_addr();
: uint32_t reg;
:
: reg = read32(etr);
: reg = (reg & ~CF9_GLB_RST) | CF9_LOCK;
: write32(etr, reg);
: }
> The callback stuff was requested by Aaron
besides that, why duplicate code again and again in soc/ when we can have a common function?
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 )
Change subject: soc/intel/common: pmclib: make use of the new ETR address API
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
PS4, Line 432: void pmc_global_reset_lock(void)
: {
: uint32_t *etr = soc_read_pmc_etr_addr();
: uint32_t reg;
:
: reg = read32(etr);
: reg = (reg & ~CF9_GLB_RST) | CF9_LOCK;
: write32(etr, reg);
: }
> Is it really worth it to have a function and callback for something that can be written down in 1 or […]
The callback stuff was requested by Aaron
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