Hello Kyösti Mälkki, Patrick Rudolph, Arthur Heymans, Jacob Garber, Matt DeVillier, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36591
to look at the new patch set (#2).
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
console: serial: add optional delay to wait for BMC serial routing
Some mainboards with a BMC do the serial routing setup in the BMC boot
phase on cold boot. This results in scrambled console output when this
is not finished fast enough.
This adds a Kconfig-based delay that can be set at mainboard level to
wait for the BMC to finish setup.
A user may set this delay to 0 when using another BMC firmware like
OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup.
Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/console/Kconfig
M src/console/init.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36591/2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36592 )
Change subject: mb/supermicro/x11-lga1151-series: use new console delay option
......................................................................
Patch Set 1: Code-Review-1
This would delay the boot, even with serial disabled.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig@161
PS1, Line 161: depends on BOOTBLOCK_CONSOLE
> @Patrick Ouch. […]
If it were taking that long to get to romstage... that would imply the
bootblock takes 2x longer than the whole coreboot on some boards ^^
You could try to get your hands on the first timestamp and then delay
appropriately. I assume, everything else would result in an `if` mess.
Btw. when I first saw this, I thought "why doesn't he do it in
bootblock_mainboard_early_init()?". Guaranteed to run only once
per boot and explicitly executed before console_init().
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Gerrit-MessageType: comment
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig@161
PS1, Line 161: depends on BOOTBLOCK_CONSOLE
> That's not true. […]
@Patrick Ouch. I didn't see this on X11SSM :/
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 )
Change subject: soc/intel/common: pmclib: make use of the new ETR address API
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
PS4, Line 434: soc_read_pmc_etr_addr();
> Check for NULL and unaligned?
IMO, that would be overkill. If it were NULL or unaligned, it wouldn't do
what the function name suggests.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig@161
PS1, Line 161: depends on BOOTBLOCK_CONSOLE
> The delay counts from power on. […]
That's not true. On x11ssh romstage is sometimes invisible when bootblock is too fast (with the fixed delay removed).
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 )
Change subject: soc/intel/common: pmclib: make use of the new ETR address API
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block…
PS4, Line 432: void pmc_global_reset_lock(void)
: {
: uint32_t *etr = soc_read_pmc_etr_addr();
: uint32_t reg;
:
: reg = read32(etr);
: reg = (reg & ~CF9_GLB_RST) | CF9_LOCK;
: write32(etr, reg);
: }
> you can put anything on one line if you like to ;) I agree on the first one. […]
with CB:36596 the mmio part would translate to this:
update32(get_base_... + ETR, ~CF9_GLB_RST, CF9_LOCK);
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36596 )
Change subject: include: introduce update* for mmio operations
......................................................................
Patch Set 1:
This change is ready for review.
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36591 )
Change subject: console: serial: add optional delay to wait for BMC serial routing
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig
File src/console/Kconfig:
https://review.coreboot.org/c/coreboot/+/36591/1/src/console/Kconfig@161
PS1, Line 161: depends on BOOTBLOCK_CONSOLE
> Doesn't seem to make sense. If bootblock console is disabled, we'd run […]
The delay counts from power on. When we reach romstage, the BMC bootloader should have run pretty sure. Serial output routing does only once after the BMC is turned on, not on every stage.
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Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36558 )
Change subject: arch/riscv: Pass cbmem_top to ramstage via calling argument
......................................................................
Patch Set 3:
Have a look at Stage handoff protocol here:
https://doc.coreboot.org/arch/riscv/index.html
a1 contains a pointer to fdt and not to cbmem_top.
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