November 2019 - coreboot-gerrit

Change in coreboot[master]: soc/intel/common: pmclib: make use of the new ETR address API
by Michael Niewöhner (Code Review) Nov. 3, 2019

Nov. 3, 2019

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 ) Change subject: soc/intel/common: pmclib: make use of the new ETR address API ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block… PS4, Line 432: void pmc_global_reset_lock(void) : { : uint32_t *etr = soc_read_pmc_etr_addr(); : uint32_t reg; : : reg = read32(etr); : reg = (reg & ~CF9_GLB_RST) | CF9_LOCK; : write32(etr, reg); : } > > besides that, why duplicate code again and again in soc/ when we can have a common function? […] you can put anything on one line if you like to ;) I agree on the first one. The second one is not good coding style I'd say; but we could add a update32 macro, to do the same as with pci. More important, where do you draw the line when something should be put to common? I would say the goal is to have as much in common code as possible and consilidate most code sooner or later. I've seen much code that could be moved from the socs to common, but that's not easy when some guys always only copypasta code :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/36570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Gerrit-Change-Number: 36570 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Nov 2019 08:37:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Add helper functions to deal with different save states
by Arthur Heymans (Code Review) Nov. 3, 2019

Nov. 3, 2019

Hello Aaron Durbin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36589 to look at the new patch set (#3). Change subject: cpu/x86/smm: Add helper functions to deal with different save states ...................................................................... cpu/x86/smm: Add helper functions to deal with different save states This abstracts the different save_states to get some common registers. Change-Id: I85325a25dc38d7cfc7eb0dfde621e5ebfeef0e15 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/smihelper.c M src/include/cpu/x86/smm.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36589/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85325a25dc38d7cfc7eb0dfde621e5ebfeef0e15 Gerrit-Change-Number: 36589 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Add helper functions to deal with different save states
by Arthur Heymans (Code Review) Nov. 3, 2019

Nov. 3, 2019

Hello Aaron Durbin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36589 to look at the new patch set (#2). Change subject: cpu/x86/smm: Add helper functions to deal with different save states ...................................................................... cpu/x86/smm: Add helper functions to deal with different save states This abstracts the different save_states to get some common registers. Change-Id: I85325a25dc38d7cfc7eb0dfde621e5ebfeef0e15 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/smihelper.c M src/include/cpu/x86/smm.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36589/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85325a25dc38d7cfc7eb0dfde621e5ebfeef0e15 Gerrit-Change-Number: 36589 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) Nov. 3, 2019

Nov. 3, 2019

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 49: > Patch Set 49: > > (43 comments) Will address these next week. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 49 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Sun, 03 Nov 2019 07:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/autoport: Make dsdt.asl prettier
by Angel Pons (Code Review) Nov. 3, 2019

Nov. 3, 2019

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30971 Change subject: util/autoport: Make dsdt.asl prettier ...................................................................... util/autoport: Make dsdt.asl prettier Small cosmetic changes which fix OCD-inducing aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/main.go 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/30971/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..5d660d1 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -842,13 +842,14 @@ for _, define := range DSDTDefines { if define.Comment != "" { - fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) + fmt.Fprintf(dsdt, "\t/* %s. */\n", define.Comment) } dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } dsdt.WriteString( - `#include <arch/acpi.h> + ` +#include <arch/acpi.h> DefinitionBlock( "dsdt.aml", "DSDT", @@ -858,7 +859,7 @@ 0x20141018 // OEM revision ) { - // Some generic macros + /* Some generic macros */ #include "acpi/platform.asl" `) @@ -870,9 +871,8 @@ } dsdt.WriteString(` - Scope (\_SB) { - Device (PCI0) - { + Device (\_SB.PCI0) + { `) for _, x := range DSDTPCI0Includes { if x.Comment != "" { @@ -881,8 +881,7 @@ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) } dsdt.WriteString( - ` } - } + ` } } `) -- To view, visit https://review.coreboot.org/c/coreboot/+/30971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Gerrit-Change-Number: 30971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: pmclib: make use of the new ETR address API
by Arthur Heymans (Code Review) Nov. 3, 2019

Nov. 3, 2019

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36570 ) Change subject: soc/intel/common: pmclib: make use of the new ETR address API ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block… PS4, Line 434: soc_read_pmc_etr_addr(); Check for NULL and unaligned? https://review.coreboot.org/c/coreboot/+/36570/4/src/soc/intel/common/block… PS4, Line 432: void pmc_global_reset_lock(void) : { : uint32_t *etr = soc_read_pmc_etr_addr(); : uint32_t reg; : : reg = read32(etr); : reg = (reg & ~CF9_GLB_RST) | CF9_LOCK; : write32(etr, reg); : } > besides that, why duplicate code again and again in soc/ when we can have a common function? If you go through the complexity of implementing a callback to fetch an offset and do sanity check on it, just to clear and set a few bits at that offset it might as well be done per soc. That likely ends up with less code. if it's PCI config register it is one line: pci_update_config32(..., ETR, ~CF9_GLB_RST, CF9_LOCK); if it's a MMIO reg it's 2 lines: uint8_t *base = get_base_... write32(base + ETR, (read32(base + ETR) & ~CF9_GLB_RST) | CF9_LOCK); -- To view, visit https://review.coreboot.org/c/coreboot/+/36570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Gerrit-Change-Number: 36570 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Nov 2019 06:23:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: boot_state: Reduce accuracy of reported times
by Kyösti Mälkki (Code Review) Nov. 3, 2019

Nov. 3, 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36528 ) Change subject: boot_state: Reduce accuracy of reported times ...................................................................... boot_state: Reduce accuracy of reported times When diffing boot logs, lines reporting times spent in each boot_state always get highlighed due the little fluctuation in microsecond-scale. Recude the logged resolution to milliseconds to avoid that. Change-Id: I7a27d6c250d8432131f30e9a4869cb45ad75d9fd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/hardwaremain.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36528/1 diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2ff2b8c..5967052 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -23,6 +23,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <commonlib/helpers.h> #include <cbmem.h> #include <version.h> #include <device/device.h> @@ -256,7 +257,12 @@ run_time = mono_time_diff_microseconds(&samples[1], &samples[2]); exit_time = mono_time_diff_microseconds(&samples[2], &samples[3]); - printk(BIOS_DEBUG, "BS: %s times (us): entry %ld run %ld exit %ld\n", + /* Report with millisecond accuracy to reduce log diffs. */ + entry_time = DIV_ROUND_CLOSEST(entry_time, 1000); + run_time = DIV_ROUND_CLOSEST(run_time, 1000); + exit_time = DIV_ROUND_CLOSEST(exit_time, 1000); + + printk(BIOS_DEBUG, "BS: %s times (ms): entry %ld run %ld exit %ld\n", state->name, entry_time, run_time, exit_time); } #else -- To view, visit https://review.coreboot.org/c/coreboot/+/36528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a27d6c250d8432131f30e9a4869cb45ad75d9fd Gerrit-Change-Number: 36528 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/quark: Switch to TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) Nov. 3, 2019

Nov. 3, 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36554 ) Change subject: intel/quark: Switch to TSC_MONOTONIC_TIMER ...................................................................... intel/quark: Switch to TSC_MONOTONIC_TIMER Change-Id: I5ea899863c5b9ed516a55ba2e7524dd33a6f651d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/quark/Kconfig M src/soc/intel/quark/tsc_freq.c 2 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/36554/1 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 75f1354..461d230 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -36,6 +36,7 @@ select SPI_FLASH select UART_OVERRIDE_REFCLK select UDELAY_TSC + select TSC_MONOTONIC_TIMER select UNCOMPRESSED_RAMSTAGE select USE_MARCH_586 select NO_SMM diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c index e6d0369..fa5bd67 100644 --- a/src/soc/intel/quark/tsc_freq.c +++ b/src/soc/intel/quark/tsc_freq.c @@ -14,21 +14,10 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <timer.h> unsigned long tsc_freq_mhz(void) { /* CPU freq = 400 MHz */ return 400; } - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t tsc_value; - - tsc_value = rdtscll(); - mt->microseconds = tsc_value / tsc_freq_mhz(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ea899863c5b9ed516a55ba2e7524dd33a6f651d Gerrit-Change-Number: 36554 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/broadwell: Switch to TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) Nov. 3, 2019

Nov. 3, 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36537 ) Change subject: intel/broadwell: Switch to TSC_MONOTONIC_TIMER ...................................................................... intel/broadwell: Switch to TSC_MONOTONIC_TIMER Change-Id: I01b73e20c8af1b00175dc6d9ee56e6b33ac5768d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc D src/soc/intel/broadwell/monotonic_timer.c 3 files changed, 1 insertion(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36537/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index fadbb41..0bbb668 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -29,6 +29,7 @@ select SSE2 select TSC_SYNC_MFENCE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SOC_INTEL_COMMON select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 91a3da0..055a004 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -39,11 +39,6 @@ romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c -bootblock-y += monotonic_timer.c -romstage-y += monotonic_timer.c -postcar-y += monotonic_timer.c -ramstage-y += monotonic_timer.c -smm-y += monotonic_timer.c ramstage-y += pch.c romstage-y += pch.c ramstage-y += pcie.c diff --git a/src/soc/intel/broadwell/monotonic_timer.c b/src/soc/intel/broadwell/monotonic_timer.c deleted file mode 100644 index 84eade8..0000000 --- a/src/soc/intel/broadwell/monotonic_timer.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <timer.h> -#include <soc/msr.h> - -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint32_t last_value; -} mono_counter; - -static inline uint32_t read_counter_msr(void) -{ - /* Even though the MSR is 64-bit it is assumed that the hardware - * is polled frequently enough to only use the lower 32-bits. */ - msr_t counter_msr; - - counter_msr = rdmsr(MSR_COUNTER_24_MHZ); - - return counter_msr.lo; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - uint32_t current_tick; - uint32_t usecs_elapsed; - - if (!mono_counter.initialized) { - mono_counter.last_value = read_counter_msr(); - mono_counter.initialized = 1; - } - - current_tick = read_counter_msr(); - usecs_elapsed = (current_tick - mono_counter.last_value) / 24; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01b73e20c8af1b00175dc6d9ee56e6b33ac5768d Gerrit-Change-Number: 36537 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE
by Kyösti Mälkki (Code Review) Nov. 3, 2019

Nov. 3, 2019

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33928 ) Change subject: cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE ...................................................................... cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/arch/x86/cpu.c M src/arch/x86/timestamp.c M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/via/nano/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/tsc/Makefile.inc M src/cpu/x86/tsc/delay_tsc.c M src/drivers/pc80/pc/i8254.c M src/include/cpu/x86/tsc.h M src/northbridge/via/vx900/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig 32 files changed, 43 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index cfab219..30d2cca 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -315,7 +315,7 @@ struct lb_tsc_info *tsc_info; /* Don't advertise a TSC rate unless it's constant. */ - if (!CONFIG(TSC_CONSTANT_RATE)) + if (!tsc_constant_rate()) return; freq_khz = tsc_freq_mhz() * 1000; diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 92d9590..8cf0f96 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -22,7 +22,7 @@ int timestamp_tick_freq_mhz(void) { /* Chipsets that have a constant TSC provide this value correctly. */ - if (CONFIG(TSC_CONSTANT_RATE)) + if (tsc_constant_rate()) return tsc_freq_mhz(); /* Filling tick_freq_mhz = 0 in timestamps-table will trigger diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 77ba0bd..3e71469 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -32,7 +32,6 @@ select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select NO_SMM diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index db119a0..d8d8b97 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -14,7 +14,6 @@ select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 16bc03b..564a428 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 43c4048..1ba8894 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 5727511..a76a95d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -12,7 +12,6 @@ select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 97d8d3d..8dae6ec 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -13,7 +13,6 @@ select MMX select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index ff16724..3af5272 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index e6c8256..cfd3e7c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index d932494..3d0522a 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -25,6 +25,7 @@ select CPU_INTEL_MODEL_6XX select NO_SMM select NO_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4ec46e0..a2ebeb2 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select MMX select SSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index a6c9b74..7504233 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,5 +20,6 @@ select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 4b96c7c..14acfd5 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,6 +25,7 @@ select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC select TSC_MONOTONIC_TIMER + select UNKNOWN_TSC_RATE select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index b316c1f..85ebd83 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -34,12 +34,9 @@ bool default n -config TSC_CONSTANT_RATE - def_bool n - depends on UDELAY_TSC - help - This option asserts that the TSC ticks at a known constant rate. - Therefore, no TSC calibration is required. +config UNKNOWN_TSC_RATE + bool + default y if LAPIC_MONOTONIC_TIMER config TSC_MONOTONIC_TIMER def_bool n diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index ab7453f..b3925b5 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c +postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c +smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index afcd1d1..7aa887a 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -18,26 +18,9 @@ #include <delay.h> #include <thread.h> -static unsigned long clocks_per_usec CAR_GLOBAL; - -static unsigned long calibrate_tsc(void) -{ - if (CONFIG(TSC_CONSTANT_RATE)) - return tsc_freq_mhz(); - else - return calibrate_tsc_with_pit(); -} - void init_timer(void) { - if (!car_get_var(clocks_per_usec)) - car_set_var(clocks_per_usec, calibrate_tsc()); -} - -static inline unsigned long get_clocks_per_usec(void) -{ - init_timer(); - return car_get_var(clocks_per_usec); + (void)tsc_freq_mhz(); } void udelay(unsigned int us) @@ -51,7 +34,7 @@ start = rdtscll(); clocks = us; - clocks *= get_clocks_per_usec(); + clocks *= tsc_freq_mhz(); current = rdtscll(); while ((current - start) < clocks) { cpu_relax(); @@ -89,7 +72,7 @@ current_tick = rdtscll(); ticks_elapsed = current_tick - mono_counter->last_value; - ticks_per_usec = get_clocks_per_usec(); + ticks_per_usec = tsc_freq_mhz(); /* Update current time and tick values only if a full tick occurred. */ if (ticks_elapsed >= ticks_per_usec) { diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c index 8e15d4d..654f84a 100644 --- a/src/drivers/pc80/pc/i8254.c +++ b/src/drivers/pc80/pc/i8254.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <arch/io.h> #include <commonlib/helpers.h> #include <cpu/x86/tsc.h> @@ -122,3 +123,25 @@ bad_ctc: return 0; } + +#if CONFIG(UNKNOWN_TSC_RATE) +static u32 g_timer_tsc CAR_GLOBAL; + +unsigned long tsc_freq_mhz(void) +{ + u32 tsc; + + tsc = car_get_var(g_timer_tsc); + if (tsc > 0) + return tsc; + + tsc = calibrate_tsc_with_pit(); + + /* Set some semi-ridiculous rate if approximation fails. */ + if (tsc == 0) + tsc = 5000; + + car_set_var(g_timer_tsc, tsc); + return tsc; +} +#endif diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index dd333e8..c18f878 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -63,4 +63,9 @@ /* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); +static inline int tsc_constant_rate(void) +{ + return !CONFIG(UNKNOWN_TSC_RATE); +} + #endif /* CPU_X86_TSC_H */ diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b..247cc24 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c -romstage-y += ./../../../drivers/pc80/pc/udelay_io.c ramstage-y += pci_util.c ramstage-y += pcie.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d87d634..5f9792b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -33,7 +33,6 @@ select GENERIC_GPIO_LIB select IOAPIC select HAVE_USBDEBUG_OPTIONS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b54528f..026f6da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -95,7 +95,6 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select UDELAY_TSC - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c833c53..397e867 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -27,7 +27,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5053790..7ea0186 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -34,7 +34,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5856ef1..fadbb41 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -27,7 +27,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 941c150..3330a69 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -102,7 +102,6 @@ select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 2aadcae..cb3713d 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -50,7 +50,6 @@ select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index efe12da..5a8bec9 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -36,7 +36,6 @@ select SMP select SPI_FLASH select SSE2 - select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 6c74a74..4c50828 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -24,7 +24,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select HAVE_FSP_BIN select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SOC_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 993e9b2..86f1ff5 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -53,7 +53,6 @@ select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b752784..75f1354 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -34,7 +34,6 @@ select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select SPI_FLASH - select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK select UDELAY_TSC select UNCOMPRESSED_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f9f6f93..d4720a2 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -76,7 +76,6 @@ select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS - select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC -- To view, visit https://review.coreboot.org/c/coreboot/+/33928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Gerrit-Change-Number: 33928 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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