coreboot-gerrit November 2019

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Change in coreboot[master]: mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCK
by Arthur Heymans (Code Review) 25 Nov '19

25 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37155 ) Change subject: mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCK ...................................................................... mb/Kconfig: Add a warning on boards with a ROMCC_BOOTLOCK This feature and therefore the boards using it, will be deprecated soon. Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37155/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index c88d317..97086b7 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,9 @@ comment "Important: Run 'make distclean' before switching boards" +if ROMCC_BOOTBLOCK +comment "Systems with ROMCC bootblocks will be deprecated soon!" +endif + choice prompt "Mainboard vendor" default VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/37155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde Gerrit-Change-Number: 37155 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Flip the meaning of C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 25 Nov '19

25 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37154 ) Change subject: Kconfig: Flip the meaning of C_ENVIRONMENT_BOOTBLOCK ...................................................................... Kconfig: Flip the meaning of C_ENVIRONMENT_BOOTBLOCK The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/arm/Kconfig M src/arch/arm64/Kconfig M src/arch/ppc64/Kconfig M src/arch/riscv/Kconfig M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/bootblock_crt0.S M src/arch/x86/bootblock_romcc.S M src/arch/x86/car.ld M src/arch/x86/include/arch/cpu.h M src/arch/x86/memlayout.ld M src/console/Kconfig M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/romstage.c M src/cpu/intel/microcode/Kconfig M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/Kconfig M src/lib/Makefile.inc M src/mainboard/facebook/fbg1701/Makefile.inc M src/mainboard/portwell/m107/Makefile.inc M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/pi/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/security/vboot/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/vendorcode/eltan/security/verified_boot/Makefile.inc M src/vendorcode/eltan/security/verified_boot/vboot_check.c 53 files changed, 48 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/37154/1 diff --git a/src/Kconfig b/src/Kconfig index ba9ae86..dddba2d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1193,9 +1193,7 @@ # src/lib/bootblock.c#main() C entry point. bool -config C_ENVIRONMENT_BOOTBLOCK - # To be selected by arch or platform if a C environment is available during the - # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). +config ROMCC_BOOTBLOCK bool ############################################################################### diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 47c333b..7b19339 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -4,7 +4,6 @@ config ARCH_BOOTBLOCK_ARM bool select ARCH_ARM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM bool diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 3d1d184..632d1bd 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -4,7 +4,6 @@ config ARCH_BOOTBLOCK_ARM64 bool select ARCH_ARM64 - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM64 bool diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0699e91..44dbb1d 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -5,7 +5,6 @@ bool select ARCH_PPC64 select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_PPC64 bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index f2ca571..8369afe 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -77,7 +77,6 @@ config ARCH_BOOTBLOCK_RISCV bool default n - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_RISCV bool diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 24a2065..a788bc0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -23,7 +23,7 @@ bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool @@ -47,7 +47,7 @@ bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool @@ -199,7 +199,7 @@ hex default 0x80 -# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. +# 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 @@ -239,7 +239,7 @@ choice prompt "Bootblock behaviour" default BOOTBLOCK_SIMPLE - depends on !C_ENVIRONMENT_BOOTBLOCK + depends on ROMCC_BOOTBLOCK config BOOTBLOCK_SIMPLE bool "Always load fallback" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc094d1..b810015 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,7 +116,7 @@ bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S @@ -128,7 +128,7 @@ bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # !C_ENVIRONMENT_BOOTBLOCK +else # !ROMCC_BOOTBLOCK # x86-specific linker flags ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -178,7 +178,7 @@ $(filter-out %.ld,$(bootblock-objs)) \ -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) -endif # C_ENVIRONMENT_BOOTBLOCK +endif # ROMCC_BOOTBLOCK endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 @@ -223,7 +223,9 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +romstage-y += gdt_init.S +endif romstage-y += cbmem.c romstage-y += cbfs_and_run.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index d9d6d4e..31fc538 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,14 +13,13 @@ #include <rules.h> -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) /* - * This path is for stages that are post bootblock when employing - * CONFIG_C_ENVIRONMENT_BOOTBLOCK. The gdt is reloaded to accommodate - * platforms that are executing out of CAR. In order to continue with - * C code execution one needs to set stack pointer and clear CAR_GLOBAL - * variables that are stage specific. + * This path is for stages that are post bootblock. The gdt is reloaded + * to accommodate platforms that are executing out of CAR. In order to + * continue with C code execution one needs to set stack pointer and + * clear .bss/CAR_GLOBAL variables that are stage specific. */ .section ".text._start", "ax", @progbits .global _start diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9fcb5c4..3256731 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -11,8 +11,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * This is the modern bootblock. It is used by platforms which select - * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. * * It provides a bootflow similar to other architectures, and thus is considered diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 05b34c6..7d6f42f 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -20,7 +20,7 @@ * - timestamp.inc: store TSC in MMX registers * - generated/bootblock.inc: ROMCC part of the bootblock * - * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * This is used on platforms which select ROMCC_BOOTBLOCK, and it * tries to do the absolute minimum before walking CBFS and jumping to romstage. * * This file assembles the bootblock program by the order of the includes. Thus, diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 3680250..483a908 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,7 +36,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; @@ -90,7 +90,7 @@ _ebss = .; _car_unallocated_start = .; -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; _ecar_stack = _car_region_end; #endif @@ -121,6 +121,6 @@ #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index e0e3ca1..6b49ecd 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -288,7 +288,7 @@ #define asmlinkage __attribute__((regparm(0))) /* - * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() + * When using not using a romcc bootblock the car_stage_entry() * is the symbol jumped to for each stage after bootblock using * cache-as-ram. */ diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889..4fa73b4 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,8 +49,7 @@ #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains - * the logic for the romcc linking. */ + /* arch/x86/bootblock.ld contains the logic for the romcc bootblock linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/console/Kconfig b/src/console/Kconfig index e767edd..bfb0e29 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,7 +5,7 @@ config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE + depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cd69720..5a668c4 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -29,7 +29,7 @@ bootblock_pre_c_entry: -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ #endif diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index a3487db..23df701 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,7 +18,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 9d19635..8059a70 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,8 +71,8 @@ /* We do not return here. */ } -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, +#if CONFIG(ROMCC_BOOTBLOCK) +/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index b783892..c76b10b 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if C_ENVIRONMENT_BOOTBLOCK + default n if ROMCC_BOOTBLOCK help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428..79dda28 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,4 +12,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f316329..e312605 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,7 +21,6 @@ select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c..e3d327c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -13,4 +13,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index a7984a9..2f1c6b4 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,13 +13,9 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -else bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S -endif postcar-y += ../car/p4-netburst/exit_car.S diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index a2ebeb2..176ae9e 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -11,7 +11,6 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM - select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 7504233..e6025b5 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -21,5 +21,4 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9e00c55..e0babd5 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,7 +29,7 @@ #include <arch/rom_segs.h> -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ +#if !CONFIG(ROMCC_BOOTBLOCK) || \ CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 85ebd83..efb5fa9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -77,7 +77,7 @@ config SETUP_XIP_CACHE bool - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK depends on !NO_XIP_EARLY_STAGES help Select this option to set up an MTRR to cache XIP stages loaded diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index dc0c46d..b444ea3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,7 +268,9 @@ postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += program.ld +endif decompressor-y += program.ld postcar-y += program.ld diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index ac4e571..07b3e35 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -16,13 +16,13 @@ ## ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += board_verified_boot.c +bootblock-y += board_verified_boot.c postcar-y += board_verified_boot.c ramstage-y += board_verified_boot.c romstage-y += board_verified_boot.c endif -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += cpld.c ramstage-y += gpio.c diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index 7d4725ef..5d88549 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a..50dba25 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 65c6556..fb8cb43 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,6 +18,7 @@ default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 4877fa9..69b055e 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index aad2674..6dc4ef0 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index df1e365..427af26 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,6 +17,7 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP + select ROMCC_BOOTBLOCK config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index a0550ec..c22275a 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -27,7 +27,6 @@ select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..a119b81 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,7 +21,6 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP - select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index edf4f23..7306036 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -28,7 +28,6 @@ select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VGA_BIOS_ID string diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..247686a 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,6 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index df1b7e4..a829443 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -95,7 +95,7 @@ config VBOOT_STARTS_IN_BOOTBLOCK bool default n - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK help Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5f9792b..e192818 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,7 +49,6 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -82,7 +81,6 @@ default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff..cbf88df 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -69,7 +69,6 @@ select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -98,7 +97,6 @@ default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 026f6da..0b3b30a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,7 +38,6 @@ select ACPI_NHLT select SOC_INTEL_COMMON_NHLT # Misc options - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 397e867..fac14cb 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7ea0186..f08b589 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -46,7 +46,6 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select C_ENVIRONMENT_BOOTBLOCK config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 095ed98..07bcf22 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -41,7 +41,6 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5731cff..5c91ac1 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -58,7 +58,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index cb3713d..0ce0d5b 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -32,7 +32,6 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select C_ENVIRONMENT_BOOTBLOCK select IOAPIC select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 418c317..c196d4b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -14,7 +14,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 461d230..099c7dd 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,7 +26,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select C_ENVIRONMENT_BOOTBLOCK select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 @@ -226,11 +225,6 @@ The location in CBFS that the RMU is located. It must match the strap-determined base address. -##### -# Bootblock -# The following options support the C_ENVIRONMENT_BOOTBLOCK. -##### - config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f5f1e30..032ded4 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -30,7 +30,6 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING - select C_ENVIRONMENT_BOOTBLOCK select FSP_M_XIP select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2824e52..9c5fc98 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -14,7 +14,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 357e520..cac4f3a 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -17,7 +17,9 @@ CPPFLAGS_common += -I$(src)/security/vboot -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += vboot_check.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += vboot_check.c +endif postcar-y += vboot_check.c romstage-y += vboot_check.c ramstage-y += vboot_check.c diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9fb8370..bc502c9 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,7 +276,7 @@ { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK) && + if (CONFIG(ROMCC_BOOTBLOCK) && CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { printk(BIOS_SPEW, "%s: check the manifest\n", __func__); if (verified_boot_check_manifest() != 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/37154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Gerrit-Change-Number: 37154 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks
by Arthur Heymans (Code Review) 25 Nov '19

25 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37157 ) Change subject: Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks ...................................................................... Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks Some guarding is not needed because the linker drops the code, other guarding is not needed because all platforms using the code now have C_ENVIRONMENT_BOOTBLOCK. Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/mainboard/facebook/fbg1701/Makefile.inc M src/mainboard/portwell/m107/Makefile.inc M src/vendorcode/eltan/security/verified_boot/Makefile.inc 6 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/37157/1 diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428..79dda28 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -12,4 +12,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c..e3d327c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -13,4 +13,4 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK + select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index a7984a9..56e7311 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,9 +13,6 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) -cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S -else bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c bootblock-y += ../../x86/early_reset.S diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index ac4e571..07b3e35 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -16,13 +16,13 @@ ## ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += board_verified_boot.c +bootblock-y += board_verified_boot.c postcar-y += board_verified_boot.c ramstage-y += board_verified_boot.c romstage-y += board_verified_boot.c endif -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += cpld.c ramstage-y += gpio.c diff --git a/src/mainboard/portwell/m107/Makefile.inc b/src/mainboard/portwell/m107/Makefile.inc index 7d4725ef..5d88549 100644 --- a/src/mainboard/portwell/m107/Makefile.inc +++ b/src/mainboard/portwell/m107/Makefile.inc @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +bootblock-y += com_init.c ramstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 357e520..97d8f81 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -17,7 +17,7 @@ CPPFLAGS_common += -I$(src)/security/vboot -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += vboot_check.c +bootblock-y += vboot_check.c postcar-y += vboot_check.c romstage-y += vboot_check.c ramstage-y += vboot_check.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32 Gerrit-Change-Number: 37157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/broadwell: Fix 'dead increment'
by HAOUAS Elyes (Code Review) 25 Nov '19

25 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36130 ) Change subject: soc/intel/broadwell: Fix 'dead increment' ...................................................................... soc/intel/broadwell: Fix 'dead increment' Dead increment spotted out using clang-tools. Change-Id: Icfab0b9ce97722fe97a0306cb45fbc2bd072bad6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36130/1 diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e47a78d..9575935 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -76,7 +76,7 @@ /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ - reg16 = 1 << 5; /* BWG step 12 */ + reg16 |= (1 << 5); /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfab0b9ce97722fe97a0306cb45fbc2bd072bad6 Gerrit-Change-Number: 36130 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/octopus: disable fmap cache for all octopus devices
by Patrick Georgi (Code Review) 25 Nov '19

25 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37163 ) Change subject: mb/google/octopus: disable fmap cache for all octopus devices ...................................................................... mb/google/octopus: disable fmap cache for all octopus devices Meep was just the first one to fail, but the others aren't any better. Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37163/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d712600..ef61499 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -22,7 +22,7 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION - select NO_FMAP_CACHE if BOARD_GOOGLE_MEEP + select NO_FMAP_CACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/37163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2 Gerrit-Change-Number: 37163 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/intel/i82801ix: Update comment on default decoded IO ranges
by Arthur Heymans (Code Review) 25 Nov '19

25 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36995 ) Change subject: sb/intel/i82801ix: Update comment on default decoded IO ranges ...................................................................... sb/intel/i82801ix: Update comment on default decoded IO ranges Now the comment matches what is programmed into LPC_EN. Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801ix/early_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/36995/1 diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 51ce9e8..92db7d8 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -76,6 +76,8 @@ * - 0x378-0x37f and 0x778-0x77f LPT * - 0x2f8-0x2ff COMB * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL */ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); -- To view, visit https://review.coreboot.org/c/coreboot/+/36995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b Gerrit-Change-Number: 36995 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Arthur Heymans (Code Review) 25 Nov '19

25 Nov '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 4: Can we agree on a timeline to get this + the open source CAR bootguard code in? Is the end of December ok? -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 08:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: /mb/google/hatch: add new memory config support
by Chen Wisley (Code Review) 25 Nov '19

25 Nov '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36665 ) Change subject: /mb/google/hatch: add new memory config support ...................................................................... /mb/google/hatch: add new memory config support 1. Add 16G 2666 2 bank group 2. Add 8G 3200 4 bank group BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- A src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex A src/mainboard/google/hatch/spd/8G_3200_4bg.spd.hex 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36665/1 diff --git a/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex b/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex new file mode 100644 index 0000000..3b41882 --- /dev/null +++ b/src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/spd/8G_3200_4bg.spd.hex b/src/mainboard/google/hatch/spd/8G_3200_4bg.spd.hex new file mode 100644 index 0000000..ad04454 --- /dev/null +++ b/src/mainboard/google/hatch/spd/8G_3200_4bg.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/36665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8 Gerrit-Change-Number: 36665 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Add Jasperlake platform support under IFDv2
by Subrata Banik (Code Review) 25 Nov '19

25 Nov '19

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37111 ) Change subject: util/ifdtool: Add Jasperlake platform support under IFDv2 ...................................................................... util/ifdtool: Add Jasperlake platform support under IFDv2 Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084 Signed-off-by: rkanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37111 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a6d0ffa..a59f36b 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -217,6 +217,7 @@ PLATFORM_CNL, PLATFORM_ICL, PLATFORM_TGL, + PLATFORM_JSL, }; unsigned int i; @@ -1637,6 +1638,8 @@ platform = PLATFORM_GLK; } else if (!strcmp(optarg, "icl")) { platform = PLATFORM_ICL; + } else if (!strcmp(optarg, "jsl")) { + platform = PLATFORM_JSL; } else if (!strcmp(optarg, "sklkbl")) { platform = PLATFORM_SKLKBL; } else if (!strcmp(optarg, "tgl")) { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 2f5b3c3..aecd8fa 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -57,6 +57,7 @@ PLATFORM_CNL, PLATFORM_GLK, PLATFORM_ICL, + PLATFORM_JSL, PLATFORM_SKLKBL, PLATFORM_TGL, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084 Gerrit-Change-Number: 37111 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/ifdtool: Add Jasperlake platform support under IFDv2
by V Sowmya (Code Review) 25 Nov '19

25 Nov '19

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37111 ) Change subject: util/ifdtool: Add Jasperlake platform support under IFDv2 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084 Gerrit-Change-Number: 37111 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 04:09:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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