coreboot-gerrit November 2019

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Change in coreboot[master]: AGESA,binaryPI: Move SCI enable outside table creation
by Kyösti Mälkki (Code Review) 23 Nov '19

23 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36812 ) Change subject: AGESA,binaryPI: Move SCI enable outside table creation ...................................................................... AGESA,binaryPI: Move SCI enable outside table creation Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/lpc.c 4 files changed, 24 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36812/1 diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 28f035c..586fbdb 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -20,7 +20,6 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> -#include <arch/io.h> #include <device/device.h> #include <version.h> @@ -78,15 +77,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 4cfbb64..7759758 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -23,6 +23,7 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> #include <pc80/i8254.h> @@ -335,6 +336,16 @@ return current; } +static void lpc_final(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + } +} + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -347,6 +358,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, + .init = lpc_final, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 28e20d3..5d07624 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -20,7 +20,6 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> -#include <arch/io.h> #include <device/device.h> #include <version.h> @@ -70,15 +69,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 1e080a0..6654830 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -23,6 +23,7 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> #include <pc80/i8254.h> @@ -351,6 +352,16 @@ return NULL; } +static void lpc_final(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + } +} + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -363,6 +374,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, + .init = lpc_final, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, -- To view, visit https://review.coreboot.org/c/coreboot/+/36812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68 Gerrit-Change-Number: 36812 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd: Move SCI enable outside table creation
by Kyösti Mälkki (Code Review) 23 Nov '19

23 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36811 ) Change subject: soc/amd: Move SCI enable outside table creation ...................................................................... soc/amd: Move SCI enable outside table creation Preferably, coreboot tables creation is kept hardware-invariant. Change-Id: Id7f79fc959766813d60f847482567579a02db124 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/finalize.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/finalize.c 4 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36811/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8597c4e..2a7ae0b 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -98,15 +98,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 0ec7bd9..3e66d88 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <bootstate.h> #include <timer.h> #include <console/console.h> +#include <soc/acpi.h> static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d1ea24f..2327ed9 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -100,15 +100,6 @@ fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_disable_sci(); - } else { - fadt->smi_cmd = 0; /* disable system management mode */ - fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ - fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ - fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ - fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 0ec7bd9..3e66d88 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -13,12 +13,14 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <bootstate.h> #include <timer.h> #include <console/console.h> +#include <soc/acpi.h> static void per_core_finalize(void *unused) { @@ -53,6 +55,13 @@ { finalize_cores(); + if (!acpi_is_wakeup_s3()) { + if (CONFIG(HAVE_SMI_HANDLER)) + acpi_disable_sci(); + else + acpi_enable_sci(); + } + post_code(POST_OS_BOOT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7f79fc959766813d60f847482567579a02db124 Gerrit-Change-Number: 36811 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: {commonlib,device,drivers}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32822 to look at the new patch set (#3). Change subject: {commonlib,device,drivers}: Use 'include <stdlib.h>' when appropriate ...................................................................... {commonlib,device,drivers}: Use 'include <stdlib.h>' when appropriate Also, including <types.h>, is supposed to provide stdint and stddef. Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/bouncebuf.h M src/device/i2c_bus.c M src/device/oprom/yabel/vbe.c M src/device/pnp_device.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/emulation/qemu/bochs.c M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/gma/intel_ddi.c M src/drivers/net/ne2k.c M src/drivers/parade/ps8625/ps8625.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/uart8250io.c M src/drivers/vpd/vpd.c M src/drivers/xgi/common/xgi_coreboot.h 15 files changed, 2 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32822/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Gerrit-Change-Number: 32822 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bss
by Krystian Hebel (Code Review) 23 Nov '19

23 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36976 ) Change subject: vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bss ...................................................................... vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bss This fixes issue that became visible after implementing post-CAR stage on top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`. Compilation error was: Forbidden global variables in romstage: ffffff00 d top.2205 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db --- M src/vendorcode/amd/pi/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36976/1 diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4e8787b..90714aa 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -68,7 +68,7 @@ AGESA_INC += -I$(src)/commonlib/include AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include -AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow AGESA_CFLAGS += -fno-strict-aliasing -D__LIBAGESA__ CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/36976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db Gerrit-Change-Number: 36976 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: MSR: Move MSR_PLATFORM_INFO to common place
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33504 Change subject: MSR: Move MSR_PLATFORM_INFO to common place ...................................................................... MSR: Move MSR_PLATFORM_INFO to common place Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/include/cpu/x86/tsc.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 13 files changed, 2 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33504/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 6c5cc31..4ee294f 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -30,8 +30,6 @@ #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4ebbe18..b7ce762 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -43,8 +43,6 @@ #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5..cc830a9 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -30,8 +30,6 @@ #define FERR_ENABLE (1 << 0) #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434..795ab79 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -30,8 +30,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_PIC_MSG_CONTROL 0x2e -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce..a4657c5 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,9 +25,10 @@ #define CPUID_DCA (1 << 18) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 #define IA32_MCG_CAP 0x179 diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8dd9b75..dd333e8 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,8 +11,6 @@ #define TSC_SYNC #endif -#define MSR_PLATFORM_INFO 0xce - struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c..8b35355 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 6137820..a121180 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -18,7 +18,6 @@ #define _SOC_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index e8e3aa2..58dcba8 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,7 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..655b325 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,7 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 0d469c4..d63257b 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index b8fe7fe..8ace3f6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -17,7 +17,6 @@ #define _BAYTRAIL_MSR_H_ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd -#define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index e4b8c50..6ae0bae 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -19,7 +19,6 @@ #define _SOC_MSR_H_ #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_PLATFORM_INFO 0xce #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 -- To view, visit https://review.coreboot.org/c/coreboot/+/33504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45cd255e0af4369926a6cb884be9ee71bf1a66de Gerrit-Change-Number: 33504 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: mainboard/gigabyte: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33898 Change subject: mainboard/gigabyte: remove stdlib.h when unused ...................................................................... mainboard/gigabyte: remove stdlib.h when unused Change-Id: Id80fa9cfb2cc72730fc0ced545d6f0a9d0e48715 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gigabyte/ma785gm/get_bus_conf.c M src/mainboard/gigabyte/ma785gmt/get_bus_conf.c M src/mainboard/gigabyte/ma78gm/get_bus_conf.c 3 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33898/1 diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 5c53476..16fdca1 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index ee2a6ca..77d55a8 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -15,9 +15,7 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable -- To view, visit https://review.coreboot.org/c/coreboot/+/33898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id80fa9cfb2cc72730fc0ced545d6f0a9d0e48715 Gerrit-Change-Number: 33898 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mainboard/{advansus,tyan}: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33902 Change subject: mainboard/{advansus,tyan}: remove stdlib.h when unused ...................................................................... mainboard/{advansus,tyan}: remove stdlib.h when unused Change-Id: Id95329ee6906b1def8e9024b64088ef6ae9ca200 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/get_bus_conf.c M src/mainboard/tyan/s2912_fam10/get_bus_conf.c 2 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/33902/1 diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 6b5ae68..7aca540 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -15,7 +15,6 @@ #include <device/pci.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index f589ef6..dc30718 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -- To view, visit https://review.coreboot.org/c/coreboot/+/33902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id95329ee6906b1def8e9024b64088ef6ae9ca200 Gerrit-Change-Number: 33902 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/lenovo/*: Add MAINBOARD_FAMILY
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32727 Change subject: mb/lenovo/*: Add MAINBOARD_FAMILY ...................................................................... mb/lenovo/*: Add MAINBOARD_FAMILY The Kconfig MAINBOARD_FAMILY sets the family type of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/z61t/Kconfig 19 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32727/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..e6dbddd 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -39,6 +39,10 @@ string default "LENOVO G505S" +config MAINBOARD_FAMILY + string + default "LENOVO G505S" + config HW_MEM_HOLE_SIZEK hex default 0x200000 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 4495d79..8066bf3 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -26,6 +26,10 @@ string default "ThinkPad L520" +config MAINBOARD_FAMILY + string + default "ThinkPad L520" + config VGA_BIOS_FILE string default "pci8086,0126.rom" diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 9200ad5..b388646 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -28,6 +28,10 @@ string default "ThinkPad S230U (Twist)" +config MAINBOARD_FAMILY + string + default "ThinkPad S230U (Twist)" + config EC_BASE_ADDRESS hex default 0xff000000 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f94051..db6c98a 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -37,6 +37,13 @@ default "ThinkPad R400" if BOARD_LENOVO_R400 default "ThinkPad W500" if BOARD_LENOVO_W500 +config MAINBOARD_FAMILY + string + default "ThinkPad T400" if BOARD_LENOVO_T400 + default "ThinkPad T500" if BOARD_LENOVO_T500 + default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad W500" if BOARD_LENOVO_W500 + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index ce81907..fb4f0ee 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad T420" +config MAINBOARD_FAMILY + string + default "ThinkPad T420" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index c5efb55..c603753 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad T420s" +config MAINBOARD_FAMILY + string + default "ThinkPad T420s" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..3c2a473 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad T430" +config MAINBOARD_FAMILY + string + default "ThinkPad T430" + config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..9f69430 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -40,6 +40,11 @@ default "ThinkPad T430s" if BOARD_LENOVO_T430S default "ThinkPad T431s" if BOARD_LENOVO_T431S +config MAINBOARD_FAMILY + string + default "ThinkPad T430s" if BOARD_LENOVO_T430S + default "ThinkPad T431s" if BOARD_LENOVO_T431S + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..62a91a6 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T520" if BOARD_LENOVO_T520 default "ThinkPad W520" if BOARD_LENOVO_W520 +config MAINBOARD_FAMILY + string + default "ThinkPad T520" if BOARD_LENOVO_T520 + default "ThinkPad W520" if BOARD_LENOVO_W520 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..62a3ac8 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T530" if BOARD_LENOVO_T530 default "ThinkPad W530" if BOARD_LENOVO_W530 +config MAINBOARD_FAMILY + string + default "ThinkPad T530" if BOARD_LENOVO_T530 + default "ThinkPad W530" if BOARD_LENOVO_W530 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a6a88b3..2ef5ebf 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad T60" +config MAINBOARD_FAMILY + string + default "ThinkPad T60" + config MAX_CPUS int default 2 diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index fc1c6a7..1e31c89 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -43,6 +43,10 @@ string default "ThinkCentre A58" +config MAINBOARD_FAMILY + string + default "ThinkCentre A58" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..a61c1bd 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -29,6 +29,10 @@ string default "ThinkPad X131e" +config MAINBOARD_FAMILY + string + default "ThinkPad X131e" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..6c84ba6 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad X1 carbon gen 1" +config MAINBOARD_FAMILY + string + default "ThinkPad X1 Carbon gen 1" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bc..8b341cc 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -32,6 +32,10 @@ string default "ThinkPad X200" +config MAINBOARD_FAMILY + string + default "ThinkPad X200" + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 16f42e8..1861984 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -35,13 +35,18 @@ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I default "x1" if BOARD_LENOVO_X1 - config MAINBOARD_PART_NUMBER string default "ThinkPad X220" if BOARD_LENOVO_X220 default "ThinkPad X220i" if BOARD_LENOVO_X220I default "ThinkPad X1" if BOARD_LENOVO_X1 +config MAINBOARD_FAMILY + string + default "ThinkPad X220" if BOARD_LENOVO_X220 + default "ThinkPad X220i" if BOARD_LENOVO_X220I + default "ThinkPad X1" if BOARD_LENOVO_X1 + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..2da651e 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad X230" +config MAINBOARD_FAMILY + string + default "ThinkPad X230" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 6db7f11..6ffe3b6 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad X60" +config MAINBOARD_FAMILY + string + default "ThinkPad X60" + config IRQ_SLOT_COUNT int default 18 diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index a223077..f0a20fd 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad Z61t" +config MAINBOARD_FAMILY + string + default "ThinkPad Z61t" + config MAX_CPUS int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Gerrit-Change-Number: 32727 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069 Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code ...................................................................... nb/intel/sandybridge: Fill common MRC settings in northbridge code Fill northbridge and southbridge BARs in raminit code. Allows to drop duplicated code from mainboard directories. Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7a..c544a74 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -275,6 +275,24 @@ u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -286,6 +304,7 @@ enable_usb_bar(); mainboard_fill_pei_data(&pei_data); + northbridge_fill_pei_data(&pei_data); post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Gerrit-Change-Number: 32069 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: drivers/intel/fsp1_0: Remove unnecessary comment
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36228 ) Change subject: drivers/intel/fsp1_0: Remove unnecessary comment ...................................................................... drivers/intel/fsp1_0: Remove unnecessary comment Change-Id: I27338bf64a2690253dbf363a8dbc29217921f051 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36228/1 diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 7eba875..71a480c 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -25,7 +25,7 @@ #include <cbmem.h> #include <spi-generic.h> #include <spi_flash.h> -#include <lib.h> // hexdump +#include <lib.h> #include "fsp_util.h" /* convert a pointer to flash area into the offset inside the flash */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index a7f3017..67d6e92 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -19,7 +19,7 @@ #include <bootstate.h> #include <cbmem.h> #include "fsp_util.h" -#include <lib.h> // hexdump +#include <lib.h> #include <ip_checksum.h> #include <timestamp.h> #include <cpu/intel/microcode.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27338bf64a2690253dbf363a8dbc29217921f051 Gerrit-Change-Number: 36228 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019