coreboot-gerrit November 2019

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Change in coreboot[4.11_branch]: lib: Fix FMAP cache on FSP1.0 platforms
by Andrey Petrov (Code Review) 25 Nov '19

25 Nov '19

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37214 ) Change subject: lib: Fix FMAP cache on FSP1.0 platforms ...................................................................... lib: Fix FMAP cache on FSP1.0 platforms On FSP1.0 platforms CAR region is torn down by FspMemoryInit() on exit, since there is no FspTempRamExit() API. Current FMAP cache code correctly assumes CAR is around and usable after. However this assumption is only correct for >= FSP1.0. This change address the problem by using cache only if CAR region is usable. TEST=boot test on OCP monolake. Change-Id: I9f64c26650fa4c397a0e4835e470ab41922e1290 --- M src/lib/fmap.c 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37214/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 48aab8f..b2dde6b 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -114,15 +114,22 @@ { const struct region_device *boot; struct fmap *fmap; - struct mem_region_device *cache; + struct mem_region_device *cache = NULL; size_t offset = FMAP_OFFSET; - /* Try FMAP cache first */ - cache = car_get_var_ptr(&fmap_cache); - if (!region_device_sz(&cache->rdev)) - setup_preram_cache(cache); - if (region_device_sz(&cache->rdev)) - return rdev_chain_full(fmrd, &cache->rdev); + /* + * Try FMAP cache first. + * On FSP 1.0 platforms make sure CAR is still around because + * the contents are destroyed on FspMemoryInit() exit. + */ + if (!CONFIG(PLATFORM_USES_FSP1_0) || + (CONFIG(PLATFORM_USES_FSP1_0) && car_active())) { + cache = car_get_var_ptr(&fmap_cache); + if (!region_device_sz(&cache->rdev)) + setup_preram_cache(cache); + if (region_device_sz(&cache->rdev)) + return rdev_chain_full(fmrd, &cache->rdev); + } boot_device_init(); boot = boot_device_ro(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I9f64c26650fa4c397a0e4835e470ab41922e1290 Gerrit-Change-Number: 37214 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Andrey Petrov (Code Review) 25 Nov '19

25 Nov '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36941 ) Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36941/1/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/36941/1/src/arch/x86/smbios.c@678 PS1, Line 678: t->core_count = (res.ebx >> 16) & 0xff; > We have talked about it but somehow we forgot to tell Jenkins about it (see the warning above) Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Nov 2019 00:32:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Andrey Petrov (Code Review) 25 Nov '19

25 Nov '19

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36941 ) Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/36941/2/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/36941/2/src/arch/x86/smbios.c@677 PS2, Line 677: t->core_count = (res.ebx >> 16) & 0xff; > I was talking about the runtime extended devicetree where after MP init you will have the real numbe […] oh I see. Yeah that would be good idea and perhaps should be implemented long term. We would to refactor this file a bit though https://review.coreboot.org/c/coreboot/+/36941/3/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/36941/3/src/arch/x86/smbios.c@673 PS3, Line 673: if (leaf_b_threads == 0) { > braces {} are not necessary for single statement blocks this is fine, ignore this -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Nov 2019 00:31:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by build bot (Jenkins) (Code Review) 25 Nov '19

25 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36941 ) Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36941/3/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/36941/3/src/arch/x86/smbios.c@673 PS3, Line 673: if (leaf_b_threads == 0) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Nov 2019 00:22:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Andrey Petrov (Code Review) 25 Nov '19

25 Nov '19

Hello Werner Zeh, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36941 to look at the new patch set (#3). Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... arch/x86: SMBIOS: Improve core count reporting Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/arch/x86/smbios.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/36941/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Nico Huber (Code Review) 25 Nov '19

25 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i94… File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i94… PS22, Line 2473: MCHBAR32(C1ODT) > High-speed electrical signalling is very cursed. If there is a bifurcation on a high-speed trace, the electrical signals will propagate across the two branches and go back after reflecting at the end of the path. Because of propagation delays, the reflected signals are not necessarily in phase with the original signal, so their superposition seriously degrades signal quality. To mitigate this problem, chips with high-speed interfaces often have on-die termination (ODT) resistors. That, and reflections anyway. You don't need bifurcation to get into trouble. A reflected signal is always bad. > > In the case of DRAM, since a chip does not care about the values on high-speed lanes when it is not selected, ODT can be enabled to dissipate the energy of signals that would otherwise be ignored and reflect. On consumer mainboards, these bifurcations only happen on memory topologies with two or more DIMMs per channel. This would explain the original code: Calistoga can only have one DIMM per channel. However, Lakeport can have two DIMMs per channel, and thus a need for ODT. And, of course, it does not make sense to enable ODT when only one DIMM is installed, as the DIMM is never unselected when the bus is active. > > Therefore, ODT should only be enabled when both DIMMs are present on a channel. Um, why does it need 3 bits to disable something? I don't think this disables ODT. It rather configures something, e.g. what rank should enable ODT or maybe it adapts the resistance on the MCH side. -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 21:41:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Angel Pons (Code Review) 25 Nov '19

25 Nov '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i94… File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/c/coreboot/+/18548/22/src/northbridge/intel/i94… PS22, Line 2473: MCHBAR32(C1ODT) > ODT is no magic, so I think it's fair to assume that the current code […] High-speed electrical signalling is very cursed. If there is a bifurcation on a high-speed trace, the electrical signals will propagate across the two branches and go back after reflecting at the end of the path. Because of propagation delays, the reflected signals are not necessarily in phase with the original signal, so their superposition seriously degrades signal quality. To mitigate this problem, chips with high-speed interfaces often have on-die termination (ODT) resistors. In the case of DRAM, since a chip does not care about the values on high-speed lanes when it is not selected, ODT can be enabled to dissipate the energy of signals that would otherwise be ignored and reflect. On consumer mainboards, these bifurcations only happen on memory topologies with two or more DIMMs per channel. This would explain the original code: Calistoga can only have one DIMM per channel. However, Lakeport can have two DIMMs per channel, and thus a need for ODT. And, of course, it does not make sense to enable ODT when only one DIMM is installed, as the DIMM is never unselected when the bus is active. Therefore, ODT should only be enabled when both DIMMs are present on a channel. -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 21:07:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/samsung: remove header guards for SuperIO
by Matt DeVillier (Code Review) 25 Nov '19

25 Nov '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37183 ) Change subject: mb/samsung: remove header guards for SuperIO ...................................................................... mb/samsung: remove header guards for SuperIO SuperIO header needs to be included regardless of Kconfig option, otherwise compilation fails due to missing prototype for try_enabling_LPC47N207_uart() if DRIVERS_UART_8250IO is not set. Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c 2 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37183/1 diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index af4e55d..28cd5c3 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -29,10 +29,8 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include "option_table.h" -#if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> -#endif +#include "option_table.h" void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 7fca8ad..157fdf1 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -29,9 +29,7 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG(USE_OPTION_TABLE) -- To view, visit https://review.coreboot.org/c/coreboot/+/37183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d Gerrit-Change-Number: 37183 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by HAOUAS Elyes (Code Review) 25 Nov '19

25 Nov '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/18548/26//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/18548/26//COMMIT_MSG@10 PS26, Line 10: > Do you observe any functionality change on your board? no, maybe I'm wrong, but CxODT are not a big deal for a desktop. As I've commented, sdram_rcomp_buffer_strength_and_slew () is the thing that I have to understand and try to modify to make my board running correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 18:59:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i945: Programm CxODT value for each channel
by Paul Menzel (Code Review) 25 Nov '19

25 Nov '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 ) Change subject: nb/intel/i945: Programm CxODT value for each channel ...................................................................... Patch Set 26: (1 comment) https://review.coreboot.org/c/coreboot/+/18548/26//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/18548/26//COMMIT_MSG@10 PS26, Line 10: Do you observe any functionality change on your board? -- To view, visit https://review.coreboot.org/c/coreboot/+/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Nov 2019 15:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2019