coreboot-gerrit November 2019

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Change in coreboot[master]: soc/intel/fsp_baytrail: Use common SPI code
by Arthur Heymans (Code Review) 26 Nov '19

26 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36406 ) Change subject: soc/intel/fsp_baytrail: Use common SPI code ...................................................................... soc/intel/fsp_baytrail: Use common SPI code Tested on Intel Minnowboard Turbot. Change-Id: Ief8507b2ef2c7a614dd06e061feefbfdbd1467ab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc D src/soc/intel/fsp_baytrail/spi.c 3 files changed, 2 insertions(+), 587 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36406/1 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 072df29..3815c2b 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -29,7 +29,9 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_SPI select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fa71932..e15534a 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -32,7 +32,6 @@ romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c @@ -51,13 +50,11 @@ ramstage-y += pmutil.c ramstage-y += ramstage.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c # Remove as ramstage gets fleshed out diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c deleted file mode 100644 index 0b52ea96..0000000 --- a/src/soc/intel/fsp_baytrail/spi.c +++ /dev/null @@ -1,584 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2016 Siemens AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include <arch/early_variables.h> -#include <stdint.h> -#include <stdlib.h> -#include <commonlib/helpers.h> -#include <delay.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <spi_flash.h> -#include <spi-generic.h> - -#include <soc/lpc.h> -#include <soc/pci_devs.h> - -typedef struct spi_slave ich_spi_slave; - -static int g_ichspi_lock CAR_GLOBAL = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint8_t _reserved3[16]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller g_cntlr CAR_GLOBAL; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#define SPI_OFFSET_MASK 0x3ff - -static uint8_t readb_(const void *addr) -{ - uint8_t v = read8(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint16_t readw_(const void *addr) -{ - uint16_t v = read16(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static uint32_t readl_(const void *addr) -{ - uint32_t v = read32(addr); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", - v, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } - return v; -} - -static void writeb_(uint8_t b, void *addr) -{ - write8(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writew_(uint16_t b, void *addr) -{ - write16(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void writel_(uint32_t b, void *addr) -{ - write32(addr, b); - if (CONFIG(DEBUG_SPI_FLASH)) { - printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", - b, (((uint32_t) addr) & SPI_OFFSET_MASK)); - } -} - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -#define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) - -void spi_init(void) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - ich9_spi_regs *ich9_spi = spi_regs(); - - car_set_var(g_ichspi_lock, readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN); - cntlr->opmenu = ich9_spi->opmenu; - cntlr->menubytes = sizeof(ich9_spi->opmenu); - cntlr->optype = &ich9_spi->optype; - cntlr->addr = &ich9_spi->faddr; - cntlr->data = (uint8_t *)ich9_spi->fdata; - cntlr->databytes = sizeof(ich9_spi->fdata); - cntlr->status = &ich9_spi->ssfs; - cntlr->control = (uint16_t *)ich9_spi->ssfc; - cntlr->preop = &ich9_spi->preop; -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t optypes; - uint8_t opmenu[MENU_BYTES]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!car_get_var(g_ichspi_lock)) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr->opmenu); - optypes = readw_(cntlr->optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr->optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == ARRAY_SIZE(opmenu)) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr->optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(uint16_t bitmask, int wait_til_set) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - int timeout = 40000; /* This will result in 400 ms */ - uint16_t status = 0; - - while (timeout--) { - status = readw_(cntlr->status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr->status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (!car_get_var(g_ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - writew_(trans.opcode, cntlr->preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr->preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr->control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - goto spi_xfer_exit; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr->databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr->addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr->databytes); - else - data_length = min(trans.bytesin, cntlr->databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr->data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr->databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr->control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr->data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - -spi_xfer_exit: - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr->preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/36406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8507b2ef2c7a614dd06e061feefbfdbd1467ab Gerrit-Change-Number: 36406 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: binaryPI: Drop BINARYPI_LEGACY_WRAPPER support
by Kyösti Mälkki (Code Review) 26 Nov '19

26 Nov '19

Hello Marshall Dawson, Paul Menzel, build bot (Jenkins), Marc Jones, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/19275 to look at the new patch set (#10). Change subject: binaryPI: Drop BINARYPI_LEGACY_WRAPPER support ...................................................................... binaryPI: Drop BINARYPI_LEGACY_WRAPPER support Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/Kconfig M src/cpu/amd/pi/Makefile.inc D src/cpu/amd/pi/amd_late_init.c D src/cpu/amd/pi/romstage.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/include/cpu/amd/car.h M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/bettong/OemCustomize.c M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/db-ft3b-lc/OemCustomize.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/OemCustomize.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/olivehillplus/OemCustomize.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/OemCustomize.c M src/mainboard/bap/ode_e21XX/romstage.c M src/northbridge/amd/agesa/state_machine.h M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/Makefile.inc M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/agesawrapper.c D src/northbridge/amd/pi/agesawrapper.h D src/northbridge/amd/pi/agesawrapper_call.h M src/vendorcode/amd/Kconfig D src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c D src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c D src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c M src/vendorcode/amd/pi/Makefile.inc 39 files changed, 9 insertions(+), 2,074 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19275/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/19275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Gerrit-Change-Number: 19275 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: util/sconfig: Fix illogical override rule for resource
by Bill XIE (Code Review) 26 Nov '19

26 Nov '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37109 ) Change subject: util/sconfig: Fix illogical override rule for resource ...................................................................... util/sconfig: Fix illogical override rule for resource The old logic only use type to identify resources, which makes a resource in override tree overriding the first resource with the same type (but possibly different index) in base tree, and resources with same type (but again different index) in override tree overriding each other. Resources had better be identified with both their type and index. Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M util/sconfig/main.c 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37109/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5c23333..3b60e2a 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1073,6 +1073,16 @@ } /* + * Match resource nodes from base and override tree to see if they are the same + * node. + */ +static int res_match(struct resource *a, struct resource *b) +{ + return ((a->type == b->type) && + (a->index == b->index)); +} + +/* * Walk through the override subtree in breadth-first manner starting at node to * see if chip_instance pointer of the node is same as chip_instance pointer of * override parent that is passed into the function. If yes, then update the @@ -1104,8 +1114,7 @@ struct resource *base_res = dev->res; while (base_res) { - if (base_res->type == res->type) { - base_res->index = res->index; + if (res_match(base_res, res)) { base_res->base = res->base; return; } @@ -1195,9 +1204,9 @@ * | | | * | res | Each resource that is present in override | * | | device is copied over to base device: | - * | | 1. If resource of same type is present in | - * | | base device, then index and base of the | - * | | resource is copied. | + * | | 1. If resource of same type and index is | + * | | present in base device, then base of | + * | | the resource is copied. | * | | 2. If not, then a new resource is allocated| * | | under the base device using type, index | * | | and base from override res. | -- To view, visit https://review.coreboot.org/c/coreboot/+/37109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea Gerrit-Change-Number: 37109 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Werner Zeh (Code Review) 26 Nov '19

26 Nov '19

1 0

Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Werner Zeh (Code Review) 26 Nov '19

26 Nov '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36941 ) Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36941/2/src/arch/x86/smbios.c File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/36941/2/src/arch/x86/smbios.c@677 PS2, Line 677: t->core_count = (res.ebx >> 16) & 0xff; > oh I see. Yeah that would be good idea and perhaps should be implemented long term. […] Sure, keep this in mind for future refactorings. It will help you if one have, for some reason, reduced MAX_NUM_CPUS to a smaller number. -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 3 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Nov 2019 08:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: src/drivers/ipmi: Implement BMC Get Self Test Result function
by David Hendricks (Code Review) 26 Nov '19

26 Nov '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37087 ) Change subject: src/drivers/ipmi: Implement BMC Get Self Test Result function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/37087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Gerrit-Change-Number: 37087 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Nov 2019 06:13:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: keep XO_SOC always in Full Power Mode
by Weiyi Lu (Code Review) 26 Nov '19

26 Nov '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35905 to review the following change. Change subject: mediatek/mt8183: keep XO_SOC always in Full Power Mode ...................................................................... mediatek/mt8183: keep XO_SOC always in Full Power Mode We could have XO_SOC output 26MHz to SOC by keeping it always in Full Power Mode even when the system suspended as a workaround for the random failure of suspend resume test. BRANCH=none TEST=suspend resume stress test by 2500 times passed on Krane. Change-Id: Id6cf8a9968cbdd2a5865aa2fd158a1ba0beb90f5 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35905/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 19b717c..c2d6c80 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -411,8 +411,11 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* + * Enable clock buffer XO_SOC and XO_CEL. + * Also keep XO_SOC always in Full Power Mode. + */ + rtc_write(PMIC_RG_DCXO_CW00, 0x6805); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); /* Load thermal coefficient */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6cf8a9968cbdd2a5865aa2fd158a1ba0beb90f5 Gerrit-Change-Number: 35905 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add I2C driver
by Roja Rani Yarubandi (Code Review) 26 Nov '19

26 Nov '19

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36830 ) Change subject: sc7180: Add I2C driver ...................................................................... Patch Set 4: (1 comment) > Patch Set 4: Code-Review+2 > > (1 comment) Done, share patch with Mike https://review.coreboot.org/c/coreboot/+/36830/4/src/soc/qualcomm/sc7180/i2… File src/soc/qualcomm/sc7180/i2c.c: https://review.coreboot.org/c/coreboot/+/36830/4/src/soc/qualcomm/sc7180/i2… PS4, Line 155: if (seg == NULL || seg->buf == NULL) > nit: should be unnecessary Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Gerrit-Change-Number: 36830 Gerrit-PatchSet: 4 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Nov 2019 04:38:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake palatfrom
by Name of user not set (Code Review) 26 Nov '19

26 Nov '19

Name of user not set #1002648 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36764 ) Change subject: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake palatfrom ...................................................................... src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake palatfrom Create SMBIOS type 16 for Monolake palatfrom, but the ECC setting can`t be confirmed in FSP, so hardcoded the Memory Error Correction field. Change-Id: I821f2c9d6833478d4a6676d93832529295cfb53b Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/monolake/mainboard.c 1 file changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36764/1 diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index dffd19f..7a4c022 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -95,3 +95,139 @@ dimm->dimm_num); t->bank_locator = smbios_add_string(t->eos, locator); } +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <pc80/mc146818rtc.h> +#include <cf9_reset.h> +#include <smbios.h> +#include <string.h> +#include <drivers/vpd/vpd.h> +#include <console/console.h> +#include <drivers/ipmi/ipmi_ops.h> +#include "ipmi.h" +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "FRB2_TIMER" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "FRB2_COUNTDOWN" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 +#define MAX_IMC 1 +#define MAX_DIMM_SIZE 32 //in GB + +static void init_frb2_wdt(void) +{ + + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(BMC_KCS_BASE); + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d\n", + countdown); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d\n", + DEFAULT_COUNTDOWN); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int write_smbios_type16(struct device *dev, int *handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + u32 maximum_capacity; + int len = sizeof(struct smbios_type16); + + printk(BIOS_DEBUG, "Create SMBIOS type 16\n"); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; //The ECC setting can`t be confirmed in FSP, so hardcode it. + t->memory_error_information_handle = 0xFFFE; + t->number_of_memory_devices = CONFIG_DIMM_MAX/MAX_IMC; + + maximum_capacity = (u32)(CONFIG_DIMM_MAX * MAX_DIMM_SIZE) << 20; + if (maximum_capacity >= 0x80000000) { + t->maximum_capacity = 0x80000000; + t->extended_maximum_capacity = maximum_capacity << 10; + } else { + t->maximum_capacity = (u32)maximum_capacity; + t->extended_maximum_capacity = 0; + } + + *current += len; + t->handle = *handle; + *handle += 1; + t->length = len - 2; + return len; +} +#endif + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(struct device *dev) +{ + ipmi_oem_rsp_t rsp; + + init_frb2_wdt(); + if (is_ipmi_clear_cmos_set(&rsp)) { + /* TODO: Should also try to restore CMOS to cmos.default + * if USE_OPTION_TABLE is set */ + cmos_init(1); + clear_ipmi_flags(&rsp); + system_reset(); + } +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = write_smbios_type16; +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + + char locator[64] = {0}; + + snprintf(locator, sizeof(locator), "DIMM_%c%u", 'A' + dimm->channel_num, + dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "_Node0_Channel%d_Dimm%d", dimm->channel_num, + dimm->dimm_num); + t->bank_locator = smbios_add_string(t->eos, locator); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I821f2c9d6833478d4a6676d93832529295cfb53b Gerrit-Change-Number: 36764 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002648 Gerrit-MessageType: newchange

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Change in coreboot[master]: binaryPI: Drop CAR teardown without POSTCAR_STAGE
by Marshall Dawson (Code Review) 25 Nov '19

25 Nov '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18526 ) Change subject: binaryPI: Drop CAR teardown without POSTCAR_STAGE ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/0063… File src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc: https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/0063… PS8, Line 920: wbinvd > Was this used as a very hacky way to make sure cbmem hits ram during romstage? That is definitely nasty and makes me wonder if S3 resume is even possible doing this. I kind of doubt it was for cbmem, although its addition predates me. There was definitely a "known" low memory corruption problem for S3 when I started working on it, so that was defeatured for all binaryPI IIRC. In those days, cbmem on AMD was initialized "late". I speculate the wbinvd was a way of preserving CAR data and stack info. I seem to recall Kyösti had solved the non-binaryPI AGESA stack problem by ensuring it was 100% popped when it got reassigned. Also a bit of trivia: a challenge to moving Stoney's cbmem_init to early was that detecting whether migration had occurred was unreliable because the CAR region was over top of DRAM. Intel implementations placed it in MMIO, ensuring FFs were read once CAR was disabled. Aaron pointed me at postcar to get around that. Kyösti, BTW if I'm able to license the binaryPI glue, or whatever that looks like, we need to make sure that the APs aren't also using a wbinvd! Unsure what implementation made that change. We fixed it for ST, then ultimately changed binaryPI to call out to coreboot for tearing down APs' CAR. https://review.coreboot.org/c/coreboot/+/18526/8/src/vendorcode/amd/pi/0063… PS8, Line 1550: * AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine : * should only be executed on the BSP > Is there some documentation of what is run on AP's by AGESA and in what state those are? I sort of implied it in my other comment, however the binary implementations I've looked at use duplicated CAR teardown routines, one still inside AGESA image for the APs, and this one run by the BSP. When the BSP hits the AmdInitEarly() entry point, it releases the APs which start running from the reset vector (vs. an INIT SIPI). The BSP waits for the APs to catch up inside AmdInitEarly() before parking them and continuing. (Sorry but...) without taking the time to go back and look at it, IIRC the BSP's teardown process triggers the APs to run the internal teardown routine. -- To view, visit https://review.coreboot.org/c/coreboot/+/18526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Gerrit-Change-Number: 18526 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Nov 2019 02:27:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit November 2019