coreboot-gerrit November 2019

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Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
by Krystian Hebel (Code Review) 26 Nov '19

26 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421 Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER ...................................................................... nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI wrapper to use new interface for dispatcher. Tested only on 00730F01 (apu2) - no other platforms available. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/state_machine.c 5 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..c64a7ba 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1006,3 +1009,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..08dfd84 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -991,3 +994,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c..f69f226 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,6 +40,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1242,3 +1244,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..349761b 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += agesawrapper.c ramstage-y += agesawrapper.c +else +romstage-y += state_machine.c +ramstage-y += state_machine.c endif romstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c new file mode 100644 index 0000000..f42e97f --- /dev/null +++ b/src/northbridge/amd/pi/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2019 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Gerrit-Change-Number: 32421 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: soc/intel/cannonlake: Add kconfig to override CPU flex ratio
by Subrata Banik (Code Review) 26 Nov '19

26 Nov '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36864 ) Change subject: soc/intel/cannonlake: Add kconfig to override CPU flex ratio ...................................................................... soc/intel/cannonlake: Add kconfig to override CPU flex ratio This patch provides options to override FIT default CPU flex ratio from coreboot code. CONFIG_CPU_FLEX_RATIO to provide the required CPU ratio and CONFIG_OVERRIDE_CPU_FLEX_RATIO to tell if override is required. TEST=Without override flex_ratio is 0 and verified booting to OS after overriding with flex_ratio value 5. Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36864/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5731cff..3f7afea 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -332,4 +332,17 @@ hex default 0x40000 # 256KB +config OVERRIDE_CPU_FLEX_RATIO + bool + help + Provide an option to override CPU ratio value. + +config CPU_FLEX_RATIO + hex + depends on OVERRIDE_CPU_FLEX_RATIO + default 0 + help + CPU ratio value controls the maximum processor non-turbo ratio. + Valid Range 0 to 63. CPU Ratio is 0 when disabled. + endif diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 996c135..5c0328b 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -77,7 +77,10 @@ /* Set CpuRatio to match existing MSR value */ msr_t flex_ratio; flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + if (CONFIG(OVERRIDE_CPU_FLEX_RATIO)) + m_cfg->CpuRatio = CONFIG_CPU_FLEX_RATIO; + else + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; /* If ISH is enabled, enable ISH elements */ if (!dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/36864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec Gerrit-Change-Number: 36864 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 50

Change in coreboot[master]: mediatek/mt8183: disable BBLPM of DCXO core
by Weiyi Lu (Code Review) 26 Nov '19

26 Nov '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37136 to review the following change. Change subject: mediatek/mt8183: disable BBLPM of DCXO core ...................................................................... mediatek/mt8183: disable BBLPM of DCXO core When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM). Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided and crystal voltage will drop from 1.8V to 0.7V or lower. In order to ensure the stability by always outputting an accuarate system clock when system is running. We should disable BBLPM when only XO_SOC enabled. BUG=b:136980838 BRANCH=kukui TEST=accurate 26MHz provided and correct crystal voltage swing Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/37136/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 19b717c..6e17a30 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -435,8 +435,8 @@ { /* Disable clock buffer XO_CEL */ rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); - /* Mask bblpm */ - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } /* the rtc boot flow entry */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Gerrit-Change-Number: 37136 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__
by Arthur Heymans (Code Review) 26 Nov '19

26 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37079 ) Change subject: southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__ ...................................................................... southbridge/intel/common/spi.c: Define __SIMPLE_DEVICE__ This simplifies PCI config space accessors. Change-Id: Idf0f90ee2dc1dcb0003ef5d56eff44ca9a5634e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/spi.c 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37079/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 4926df9..3b7842d 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + /* This file is derived from the flashrom project. */ #include <arch/early_variables.h> #include <stdint.h> @@ -274,11 +276,7 @@ #define RCBA 0xf0 #define SBASE 0x54 -#ifdef __SIMPLE_DEVICE__ static void *get_spi_bar(pci_devfn_t dev) -#else -static void *get_spi_bar(struct device *dev) -#endif { uintptr_t rcba; /* Root Complex Register Block */ uintptr_t sbase; @@ -306,11 +304,7 @@ struct ich7_spi_regs *ich7_spi; uint16_t hsfs; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = pcidev_on_root(31, 0); -#endif if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = get_spi_bar(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/37079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf0f90ee2dc1dcb0003ef5d56eff44ca9a5634e7 Gerrit-Change-Number: 37079 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/common/spi: Add Baytrail/Braswell support
by Arthur Heymans (Code Review) 26 Nov '19

26 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36342 ) Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ...................................................................... sb/intel/common/spi: Add Baytrail/Braswell support Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 57 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 73181cf..fd53217 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -33,6 +33,10 @@ #include "spi.h" +#if (!ICH7_SPI && !ICH9_SPI && !BYT_BSW_SPI) +#error "Unsupported SPI controller! +#endif + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -271,6 +275,30 @@ #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) #endif +static void *get_spi_bar(void) +{ + uint32_t rcba; /* Root Complex Register Block */ + uint32_t sbase; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = pcidev_on_root(31, 0); +#endif + if (ICH7_SPI) { + rcba = pci_read_config32(dev, 0xf0); + return (void *)((rcba & 0xffffc000) + 0x3020); + } + if (BYT_BSW_SPI) { + sbase = pci_read_config32(dev, 0x52); + sbase &= ~0x1ff; + return (void *)sbase; + } + if (ICH9_SPI) { + rcba = pci_read_config32(dev, 0xf0); + return (void *)((rcba & 0xffffc000) + 0x3800); + } +} + void spi_init(void) { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); @@ -281,17 +309,8 @@ struct ich7_spi_regs *ich7_spi; uint16_t hsfs; -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = pcidev_on_root(31, 0); -#endif - - rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + if (ICH7_SPI) { + ich7_spi = get_spi_bar(); cntlr->ich7_spi = ich7_spi; cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -306,7 +325,7 @@ cntlr->fpr = &ich7_spi->pbr[0]; cntlr->fpr_max = 3; } else { - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + ich9_spi = get_spi_bar(); cntlr->ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); cntlr->hsfs = hsfs; @@ -333,11 +352,20 @@ ich_set_bbar(0); - /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + if (BYT_BSW_SPI) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = readl_(ich9_spi + 0xfc); + bios_cntl |= 1; + writel_(bios_cntl, ich9_spi + 0xfc); + } + + if (ICH7_SPI || ICH9_SPI) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + } } static int spi_locked(void) diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..84e183e 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,18 @@ struct intel_spi_op ops[8]; }; +#define ICH7_SPI CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#define ICH9_SPI (CONFIG(SOUTHBRIDGE_INTEL_I82801IX) || \ + CONFIG(SOUTHBRIDGE_INTEL_I82801JX) || \ + CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) || \ + CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ + CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) || \ + CONFIG(SOC_INTEL_BROADWELL) || \ + CONFIG(SOC_INTEL_BROADWELL_DE)) +#define BYT_BSW_SPI (CONFIG(SOC_INTEL_BAYTRAIL) || \ + CONFIG(SOC_INTEL_FSP_BAYTRAIL) || \ + CONFIG(SOC_INTEL_BRASWELL)) + void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/36342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Gerrit-Change-Number: 36342 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Remove duplicate offsetof() definition
by Jacob Garber (Code Review) 26 Nov '19

26 Nov '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37181 ) Change subject: security/vboot: Remove duplicate offsetof() definition ...................................................................... security/vboot: Remove duplicate offsetof() definition This macro is already defined in commonlib/helpers.h Change-Id: I1fce2936757b13807e254f4a844f583b938bf349 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/security/vboot/secdata_tpm.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37181/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 38a1810..2fbb30b 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -40,10 +40,6 @@ #include <vb2_api.h> #include <console/console.h> -#ifndef offsetof -#define offsetof(A,B) __builtin_offsetof(A,B) -#endif - #ifdef FOR_TEST #include <stdio.h> #define VBDEBUG(format, args...) printf(format, ## args) -- To view, visit https://review.coreboot.org/c/coreboot/+/37181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fce2936757b13807e254f4a844f583b938bf349 Gerrit-Change-Number: 37181 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/nvidia/tegra: Remove duplicate macros
by Jacob Garber (Code Review) 26 Nov '19

26 Nov '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37182 ) Change subject: soc/nvidia/tegra: Remove duplicate macros ...................................................................... soc/nvidia/tegra: Remove duplicate macros These macros are already defined in stdbool.h or commonlib/helpers.h Change-Id: I6e474fc233d3134c89c29840471797b1e0c9e3c3 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/soc/nvidia/tegra/types.h 1 file changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37182/1 diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index 9af4b20..0cbbd5d 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -26,29 +26,4 @@ #define IS_ERR_PTR(ptr) \ (ptr == (void *)-EPTR) -#ifndef bool -#define bool int -#endif - -#ifndef false -#define false 0 -#endif - -#ifndef true -#define true 1 -#endif - -#ifndef container_of -/** - * container_of - cast a member of a structure out to the containing structure - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - * - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) -#endif - #endif /* __TEGRA_MISC_TYPES_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e474fc233d3134c89c29840471797b1e0c9e3c3 Gerrit-Change-Number: 37182 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: SMBIOS: Improve core count reporting
by Patrick Georgi (Code Review) 26 Nov '19

26 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36941 ) Change subject: arch/x86: SMBIOS: Improve core count reporting ...................................................................... arch/x86: SMBIOS: Improve core count reporting Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/smbios.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7e05408..a599add 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -647,7 +647,26 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + /* + * If CPUID leaf 11 is available, calculate "core count" by dividing + * SMT_ID (logical processors in a core) by Core_ID (number of cores). + * This seems to be the way to arrive to a number of cores mentioned on + * ark.intel.com. + */ + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0xb) { + uint32_t leaf_b_cores = 0, leaf_b_threads = 0; + res = cpuid_ext(0xb, 1); + leaf_b_cores = res.ebx; + res = cpuid_ext(0xb, 0); + leaf_b_threads = res.ebx; + /* if hyperthreading is not available, pretend this is 1 */ + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } + t->core_count = leaf_b_cores / leaf_b_threads; + } else { + t->core_count = (res.ebx >> 16) & 0xff; + } /* Assume we enable all the cores always, capped only by MAX_CPUS */ t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS); t->l1_cache_handle = 0xffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/36941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Gerrit-Change-Number: 36941 Gerrit-PatchSet: 4 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/exit_car.S: Drop redundant enabling cache
by Arthur Heymans (Code Review) 26 Nov '19

26 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37179 ) Change subject: soc/amd/exit_car.S: Drop redundant enabling cache ...................................................................... soc/amd/exit_car.S: Drop redundant enabling cache This is already done in arch/x86/exit_car.S Change-Id: Ie954aa11d5e76aaa3e2185ba552aafe8d075feb6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/car/exit_car.S 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37179/1 diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index f9d056e..16880e7 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -29,9 +29,4 @@ AMD_DISABLE_STACK - /* enable cache */ - movl %cr0, %eax - andl $(~(CR0_CD | CR0_NW)), %eax - movl %eax, %cr0 - jmp *%esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie954aa11d5e76aaa3e2185ba552aafe8d075feb6 Gerrit-Change-Number: 37179 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Fix mrc.bin path
by Arthur Heymans (Code Review) 26 Nov '19

26 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37185 ) Change subject: nb/intel/sandybridge: Fix mrc.bin path ...................................................................... nb/intel/sandybridge: Fix mrc.bin path The mrc.bin uses a lot of stack. Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37185/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..7a27d09 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -74,7 +74,10 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x2800 + default 0x10000 + help + The amount of BSP stack anticipated in bootblock and + other stages. if USE_NATIVE_RAMINIT -- To view, visit https://review.coreboot.org/c/coreboot/+/37185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c Gerrit-Change-Number: 37185 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019