coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: .gitignore: Add pmh7tool binary
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37216 ) Change subject: .gitignore: Add pmh7tool binary ...................................................................... .gitignore: Add pmh7tool binary Change-Id: Ide09ac2f61cffadb86f8a52b99a8ed9536a86a50 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M .gitignore 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37216/1 diff --git a/.gitignore b/.gitignore index 84b3af1..0cc6ae2 100644 --- a/.gitignore +++ b/.gitignore @@ -114,6 +114,7 @@ util/nvramtool/.dependencies util/nvramtool/nvramtool util/optionlist/Options.wiki +util/pmh7tool/pmh7tool util/romcc/build util/runfw/googlesnow util/superiotool/superiotool -- To view, visit https://review.coreboot.org/c/coreboot/+/37216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide09ac2f61cffadb86f8a52b99a8ed9536a86a50 Gerrit-Change-Number: 37216 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: i945/early_init.c: Use BIT(x) macro
by HAOUAS Elyes (Code Review) 27 Nov '19

27 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37269 ) Change subject: i945/early_init.c: Use BIT(x) macro ...................................................................... i945/early_init.c: Use BIT(x) macro Change-Id: I78634ea4f51deb82e98939abbed8f07ce98c117b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37269/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 13dce61..f0f6261 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -173,7 +173,7 @@ which requires to have TSEG_BASE aligned to TSEG_SIZE. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); reg8 &= ~0x7; - reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ + reg8 |= BIT(1) | BIT(0); /* 2M and TSEG_Enable */ pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); /* Set C0000-FFFFF to access RAM on both reads and writes */ @@ -262,17 +262,17 @@ /* Is internal graphics enabled? */ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) - MCHBAR32(MMARB1) |= (1 << 17); + MCHBAR32(MMARB1) |= BIT(17); /* Assign Virtual Channel ID 1 to VC1 */ reg32 = EPBAR32(EPVC1RCTL); reg32 &= ~(7 << 24); - reg32 |= (1 << 24); + reg32 |= BIT(24); EPBAR32(EPVC1RCTL) = reg32; reg32 = EPBAR32(EPVC1RCTL); reg32 &= 0xffffff01; - reg32 |= (1 << 7); + reg32 |= BIT(7); EPBAR32(EPVC1RCTL) = reg32; EPBAR32(PORTARB + 0x00) = 0x01000001; @@ -284,8 +284,8 @@ EPBAR32(PORTARB + 0x18) = 0x00001000; EPBAR32(PORTARB + 0x1c) = 0x00000040; - EPBAR32(EPVC1RCTL) |= (1 << 16); - EPBAR32(EPVC1RCTL) |= (1 << 16); + EPBAR32(EPVC1RCTL) |= BIT(16); + EPBAR32(EPVC1RCTL) |= BIT(16); printk(BIOS_DEBUG, "Loading port arbitration table ..."); /* Loop until bit 0 becomes 0 */ @@ -298,12 +298,12 @@ printk(BIOS_DEBUG, "ok\n"); /* Now enable VC1 */ - EPBAR32(EPVC1RCTL) |= (1 << 31); + EPBAR32(EPVC1RCTL) |= BIT(31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7fff; - while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) + while ((EPBAR16(EPVC1RSTS) & BIT(1)) && --timeout) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -334,7 +334,7 @@ reg32 = RCBA32(V1CTL); reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); - reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); + reg32 |= (0x40 << 1) | (4 << 17) | BIT(24) | BIT(31); RCBA32(V1CTL) = reg32; RCBA32(LCAP) |= (3 << 10); @@ -360,21 +360,21 @@ reg32 = DMIBAR32(DMIVC1RCTL); reg32 &= ~(7 << 24); - reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ + reg32 |= BIT(24); /* NOTE: This ID must match ICH7 side */ DMIBAR32(DMIVC1RCTL) = reg32; reg32 = DMIBAR32(DMIVC1RCTL); reg32 &= 0xffffff01; - reg32 |= (1 << 7); + reg32 |= BIT(7); DMIBAR32(DMIVC1RCTL) = reg32; /* Now enable VC1 */ - DMIBAR32(DMIVC1RCTL) |= (1 << 31); + DMIBAR32(DMIVC1RCTL) |= BIT(31); printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); /* Wait for VC1 negotiation pending */ timeout = 0x7ffff; - while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) + while ((DMIBAR16(DMIVC1RSTS) & BIT(1)) && --timeout) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -395,9 +395,9 @@ reg32 = DMIBAR32(DMICC); reg32 &= 0x00ffffff; reg32 &= ~(3 << 0); - reg32 |= (1 << 0); + reg32 |= BIT(0); reg32 &= ~(3 << 20); - reg32 |= (1 << 20); + reg32 |= BIT(20); DMIBAR32(DMICC) = reg32; @@ -424,14 +424,14 @@ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { printk(BIOS_DEBUG, "Internal graphics: enabled\n"); - DMIBAR32(0x200) |= (1 << 21); + DMIBAR32(0x200) |= BIT(21); } else { printk(BIOS_DEBUG, "Internal graphics: disabled\n"); - DMIBAR32(0x200) &= ~(1 << 21); + DMIBAR32(0x200) &= ~BIT(21); } reg32 = DMIBAR32(0x204); - reg32 &= ~((1 << 11) | (1 << 10)); + reg32 &= ~(BIT(11) | BIT(10)); DMIBAR32(0x204) = reg32; reg32 = DMIBAR32(0x204); @@ -446,8 +446,8 @@ reg32 |= (0x02 << 26); DMIBAR32(0x200) = reg32; - DMIBAR32(DMIDRCCFG) &= ~(1 << 31); - DMIBAR32(DMICTL2) |= (1 << 31); + DMIBAR32(DMIDRCCFG) &= ~BIT(31); + DMIBAR32(DMICTL2) |= BIT(31); if (i945_silicon_revision() >= 3) { reg32 = DMIBAR32(0xec0); @@ -474,7 +474,7 @@ /* wait for bit toggle to 0 */ printk(BIOS_DEBUG, "Waiting for DMI hardware..."); timeout = 0x7fffff; - while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) + while ((DMIBAR8(0x32) & BIT(1)) && --timeout) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -494,7 +494,7 @@ DMIBAR32(0x334) = DMIBAR32(0x334); DMIBAR32(0x338) = DMIBAR32(0x338); - if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { + if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & BIT(5))) { if ((MCHBAR32(0x214) & 0xf) != 0x3) { printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); reg32 = DMIBAR32(0x224); @@ -523,7 +523,7 @@ pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); reg32 = pci_read_config32(p2peg, PEGCC); - reg32 &= ~(1 << 8); + reg32 &= ~BIT(8); pci_write_config32(p2peg, PEGCC, reg32); /* We have no success with querying the usual PCIe registers @@ -539,20 +539,20 @@ printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); if (!(reg16 & 0x48)) goto disable_pciexpress_x16_link; - reg16 |= (1 << 4) | (1 << 0); + reg16 |= BIT(4) | BIT(0); pci_write_config16(p2peg, SLOTSTS, reg16); pci_s_bridge_set_secondary(p2peg, tmp_secondary); reg32 = pci_read_config32(p2peg, 0x224); - reg32 &= ~(1 << 8); + reg32 &= ~BIT(8); pci_write_config32(p2peg, 0x224, reg32); - MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); + MCHBAR16(UPMC1) &= ~(BIT(5) | BIT(0)); /* Initialize PEG_CAP */ reg16 = pci_read_config16(p2peg, PEG_CAP); - reg16 |= (1 << 8); + reg16 |= BIT(8); pci_write_config16(p2peg, PEG_CAP, reg16); /* Setup SLOTCAP */ @@ -630,7 +630,7 @@ printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); - reg16 = (1 << 1); + reg16 = BIT(1); pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); @@ -640,7 +640,7 @@ /* Enable GPEs */ reg32 = pci_read_config32(p2peg, PEG_LC); - reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ + reg32 |= BIT(2) | BIT(1) | BIT(0); /* PMEGPE, HPGPE, GENGPE */ pci_write_config32(p2peg, PEG_LC, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ @@ -689,7 +689,7 @@ pci_write_config32(p2peg, 0xf0, reg32); reg32 = pci_read_config32(p2peg, 0xf0); - reg32 |= (1 << 5); + reg32 |= BIT(5); pci_write_config32(p2peg, 0xf0, reg32); reg32 = pci_read_config32(p2peg, 0x200); @@ -699,17 +699,17 @@ reg32 = pci_read_config32(p2peg, 0xe80); if (i945_silicon_revision() >= 2) - reg32 |= (1 << 12); + reg32 |= BIT(12); else - reg32 &= ~(1 << 12); + reg32 &= ~BIT(12); pci_write_config32(p2peg, 0xe80, reg32); reg32 = pci_read_config32(p2peg, 0xeb4); - reg32 &= ~(1 << 31); + reg32 &= ~BIT(31); pci_write_config32(p2peg, 0xeb4, reg32); reg32 = pci_read_config32(p2peg, 0xfc); - reg32 |= (1 << 31); + reg32 |= BIT(31); pci_write_config32(p2peg, 0xfc, reg32); if (i945_silicon_revision() >= 3) { @@ -732,7 +732,7 @@ /* Set voltage specific parameters */ reg32 = pci_read_config32(p2peg, 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ - if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ + if ((MCHBAR32(DFT_STRAP1) & BIT(20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } pci_write_config32(p2peg, 0xe80, reg32); @@ -744,13 +744,13 @@ /* For now we just disable the x16 link */ printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); - MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) |= BIT(5) | BIT(0); /* Toggle PCIRST# */ pci_s_assert_secondary_reset(p2peg); reg32 = pci_read_config32(p2peg, 0x224); - reg32 |= (1 << 8); + reg32 |= BIT(8); pci_write_config32(p2peg, 0x224, reg32); pci_s_deassert_secondary_reset(p2peg); @@ -781,14 +781,14 @@ reg32 = EPBAR32(EPESD); reg32 &= 0xff00ffff; - reg32 |= (1 << 16); + reg32 |= BIT(16); EPBAR32(EPESD) = reg32; - EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); + EPBAR32(EPLE1D) |= BIT(16) | BIT(0); EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; - EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); + EPBAR32(EPLE2D) |= BIT(16) | BIT(0); /* DMI Port Root Topology */ @@ -798,12 +798,12 @@ reg32 &= 0xff00ffff; reg32 |= (2 << 16); - reg32 |= (1 << 0); + reg32 |= BIT(0); DMIBAR32(DMILE1D) = reg32; DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; - DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); + DMIBAR32(DMILE2D) |= BIT(16) | BIT(0); DMIBAR32(DMILE2A) = DEFAULT_EPBAR; @@ -811,7 +811,7 @@ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); reg32 = pci_read_config32(p2peg, LE1D); - reg32 |= (1 << 0); + reg32 |= BIT(0); pci_write_config32(p2peg, LE1D, reg32); } } @@ -822,7 +822,7 @@ RCBA32(ESD) |= (2 << 16); - RCBA32(ULD) |= (1 << 24) | (1 << 16); + RCBA32(ULD) |= BIT(24) | BIT(16); RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; /* Write ESD.CID to TCID */ @@ -837,7 +837,7 @@ static void ich7_setup_pci_express(void) { - RCBA32(CG) |= (1 << 0); + RCBA32(CG) |= BIT(0); /* Initialize slot power limit for root ports */ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); @@ -869,7 +869,7 @@ RCBA32(GCS) &= (~0x04); /* Just do it that way */ - RCBA32(0x2010) |= (1 << 10); + RCBA32(0x2010) |= BIT(10); } static void i945_prepare_resume(int s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78634ea4f51deb82e98939abbed8f07ce98c117b Gerrit-Change-Number: 37269 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: [RFC and WIP]Add an option to align FMAP regions
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33300 Change subject: [RFC and WIP]Add an option to align FMAP regions ...................................................................... [RFC and WIP]Add an option to align FMAP regions This eases writing FMD files when there are alignment requirement on some regions (e.g. MRC_VAR_CACHE). Some questions: - Do we want to error out on options that have a base defined but that does not follow its alignment or do we want to fix the alignment if such configuration presents itself - '~' is used. Is that the 'best' symbol Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fmd.c M util/cbfstool/fmd.h M util/cbfstool/fmd_parser.y M util/cbfstool/fmd_scanner.l 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33300/1 diff --git a/util/cbfstool/fmd.c b/util/cbfstool/fmd.c index 7a289d7..d39ec20 100644 --- a/util/cbfstool/fmd.c +++ b/util/cbfstool/fmd.c @@ -248,6 +248,10 @@ } else if (!first_incomplete_it) { watermark = cur_section->offset + cur_section->size; } + if (cur_section->alignment_known) { + cur_section->offset = (cur_section->offset + cur_section->alignment - 1) + & ~(cur_section->alignment); + } } if (first_incomplete_it && diff --git a/util/cbfstool/fmd.h b/util/cbfstool/fmd.h index 90e6d6e..91ae2fd 100644 --- a/util/cbfstool/fmd.h +++ b/util/cbfstool/fmd.h @@ -53,6 +53,8 @@ bool size_known; /** It is an error to read this field unless size_known is set. */ unsigned size; + bool alignment_known; + unsigned alignment; size_t list_len; union flashmap_flags flags; /** It is an error to dereference this array if list_len is 0. */ diff --git a/util/cbfstool/fmd_parser.y b/util/cbfstool/fmd_parser.y index 3ba710c..e7e1caf 100644 --- a/util/cbfstool/fmd_parser.y +++ b/util/cbfstool/fmd_parser.y @@ -52,7 +52,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children); + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children); void yyerror(const char *s); } @@ -71,6 +72,8 @@ %type <maybe_intval> region_offset %type <maybe_intval> region_size_opt %type <maybe_intval> region_size +%type <maybe_intval> region_alignment_opt +%type <maybe_intval> region_alignment %type <region_listhdr> region_list_opt %type <region_listhdr> region_list %type <region_listhdr> region_list_entries @@ -80,13 +83,14 @@ flash_chip: region_name region_offset_opt region_size region_list { union flashmap_flags flags = { .v=0 }; - if (!(res = parse_descriptor($1, flags, $2, $3, $4))) + struct unsigned_option alignment = { .val_known = false }; + if (!(res = parse_descriptor($1, flags, $2, $3, alignment, $4))) YYABORT; }; flash_region: region_name region_flags_opt region_offset_opt region_size_opt - region_list_opt + region_alignment_opt region_list_opt { - struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5); + struct flashmap_descriptor *node = parse_descriptor($1, $2, $3, $4, $5, $6); if (!node) YYABORT; @@ -115,6 +119,9 @@ region_size_opt: { $$ = (struct unsigned_option){false, 0}; } | region_size; region_size: INTEGER { $$ = (struct unsigned_option){true, $1}; }; +region_alignment_opt: { $$ = (struct unsigned_option){false, 0}; } + | region_alignment; +region_alignment: '~' INTEGER { $$ = (struct unsigned_option){true, $2}; }; region_list_opt: { $$ = (struct descriptor_list) @@ -152,7 +159,8 @@ struct flashmap_descriptor *parse_descriptor( char *name, union flashmap_flags flags, struct unsigned_option offset, - struct unsigned_option size, struct descriptor_list children) + struct unsigned_option size, struct unsigned_option alignment, + struct descriptor_list children) { struct flashmap_descriptor *region = malloc(sizeof(*region)); if (!region) { @@ -165,6 +173,8 @@ region->offset = offset.val; region->size_known = size.val_known; region->size = size.val; + region->alignment_known = alignment.val_known; + region->alignment = alignment.val; region->list_len = children.len; if (region->list_len) { region->list = malloc(region->list_len * sizeof(*region->list)); diff --git a/util/cbfstool/fmd_scanner.l b/util/cbfstool/fmd_scanner.l index be9a5de..4c7d322 100644 --- a/util/cbfstool/fmd_scanner.l +++ b/util/cbfstool/fmd_scanner.l @@ -39,7 +39,7 @@ [1-9][0-9]*{MULTIPLIER}? return parse_integer(yytext, 10); 0[0-9]+{MULTIPLIER}? return OCTAL; 0[xX][0-9a-fA-F]+{MULTIPLIER}? return parse_integer(yytext + 2, 16); -[^#@{}()[:space:]]* return copy_string(yytext); +[^#@~{}()[:space:]]* return copy_string(yytext); . return *yytext; %% -- To view, visit https://review.coreboot.org/c/coreboot/+/33300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e01112f0c98f45876bcc7012f195f5aa693efd Gerrit-Change-Number: 33300 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot: Add const modifier to vb2api_relocate argument
by Yu-Ping Wu (Code Review) 27 Nov '19

27 Nov '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37232 ) Change subject: security/vboot: Add const modifier to vb2api_relocate argument ...................................................................... security/vboot: Add const modifier to vb2api_relocate argument BRANCH=none BUG=none TEST=emerge-nami vboot_reference coreboot Cq-Depend: chromium:1935272 Change-Id: I599262586f30b6768e394bd9795d4e52269f4fdf Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/security/vboot/common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37232/1 diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index cb4c569..11a5189 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -92,7 +92,7 @@ static void vboot_migrate_cbmem(int unused) { const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; - void *wb_preram = (void *)_vboot2_work; + const void *wb_preram = (void *)_vboot2_work; void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wb_cbmem != NULL); vb2api_relocate(wb_cbmem, wb_preram, cbmem_size, -- To view, visit https://review.coreboot.org/c/coreboot/+/37232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I599262586f30b6768e394bd9795d4e52269f4fdf Gerrit-Change-Number: 37232 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: sc7180: Add I2C driver
by Julius Werner (Code Review) 26 Nov '19

26 Nov '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36830 ) Change subject: sc7180: Add I2C driver ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61221ffff8afe5c7ede5abb9e194e242ab0274d8 Gerrit-Change-Number: 36830 Gerrit-PatchSet: 5 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Satya Priya Kakitapalli <c_skakit(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Nov 2019 02:05:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7180: Add UART support
by Julius Werner (Code Review) 26 Nov '19

26 Nov '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 18 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 27 Nov 2019 01:27:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: private patch test
by David Hendricks (Code Review) 26 Nov '19

26 Nov '19

David Hendricks has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37252 ) Change subject: private patch test ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/37252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27aa26214eb2781f60e52c06f068e36295ebdfa1 Gerrit-Change-Number: 37252 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: include: introduce update* for mmio operations
by Nico Huber (Code Review) 26 Nov '19

26 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36596 ) Change subject: include: introduce update* for mmio operations ...................................................................... Patch Set 5: > (Sorry, I must have missed this going by when it was committed...) > > We already have clrsetbits_le32() (and _le16(), etc.) in <endian.h> that have been used for the same purpose all across the code base for years. Why are we adding a new API that covers exactly the same thing? If we don't like that name anymore we can discuss changing it, but I don't think we should have a bunch of different ways to write exactly the same access. Um, all across the code base == some ARM stuff? I think you are exaggerating a bit too much, it's the first time I hear about it. I agree, however, that we shouldn't have competing APIs. > > Also, I thought <device/mmio.h> was now supposed to be the new catchall header you should include for MMIO stuff, and that's what most code is including. We've been starting to add more generic MMIO helper functions there already, but now you're introducing this confusingly similarly named file but neither of them includes the other. Shouldn't we keep all the MMIO stuff under one common include point? (Whether that's <mmio.h> or <device/mmio.h> I don't care, but considering that most files already include the latter it would probably be easier to keep it that way.) Might be enough to point out that `device/mmio.h` existed already. I think it was just missed here. -- To view, visit https://review.coreboot.org/c/coreboot/+/36596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb Gerrit-Change-Number: 36596 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 26 Nov 2019 23:06:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/kconfig: Make Prairie Falcon selection explicit
by Richard Spiegel (Code Review) 26 Nov '19

26 Nov '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36823 ) Change subject: soc/amd/stoneyridge/kconfig: Make Prairie Falcon selection explicit ...................................................................... soc/amd/stoneyridge/kconfig: Make Prairie Falcon selection explicit Current code surreptitiously selected Prairie Falcon if Merlin Falcon is selected and no Merlin Falcon binaries are available. This is not optimal, make the selection an explicit choice. Main differences between Stoneyridge, Merlin Falcon and Prairie Falcon are related to number of memory channels, binaries used and if PSP is capable of dual load (combo capable). Though Prairie Falcon internally uses the same CPU (and thus same binaries) as Stoneyridge, only Stoneyridge is combo capable. Merlin Falcon uses the same internal CPU as Carrizo, thus it has dual memory channel while Prairie Falcon and Stoney ridge have only one channel. However, only one particular version of Carrizo binaries were tested and worked for Merlin Falcon, so for the time being it must use its own binary image (not all Carrizo images work). BUG=None TEST=Build padmelon with Prarie Falcon and Merlin Falcon Change-Id: I309c5918fdc98d9927641466bbe6149b97b250f0 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Kconfig 4 files changed, 15 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36823/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff..965ca5d 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -28,6 +28,11 @@ help AMD Merlin Falcon FP4 support +config SOC_AMD_PRAIRIEFALCON + bool + help + AMD Prairie Falcon FP4 support + config HAVE_MERLINFALCON_BINARIES depends on SOC_AMD_MERLINFALCON bool "Merlinfalcon binaries are present" @@ -36,7 +41,7 @@ This config option will be removed once the binaries are merged to the blobs repo. See 33615. -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON config CPU_SPECIFIC_OPTIONS def_bool y @@ -315,7 +320,7 @@ config SOC_AMD_PSP_SELECTABLE_SMU_FW bool - default n if SOC_AMD_MERLINFALCON + default n if (SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON) default y help Some ST implementations allow storing SMU firmware into cbfs and @@ -402,4 +407,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 53aabf5..0866425 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_PRAIRIEFALCON)$(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -218,7 +218,7 @@ OPT_SMUFWM_FN_FILE=$(call add_opt_prefix, $(SMUFWM_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware) OPT_SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FN_FILE), --subprogram $(SUBPROG_FN_SMU_FW) --smufirmware2) -ifeq ($(FIRMWARE_TYPE),ST) +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) OPT_COMBOCAPABLE=--combo-capable endif @@ -320,4 +320,4 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_PRAIRIEFALCON)$(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index fef7dff..6f52916 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -28,7 +28,7 @@ # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_PRAIRIEFALCON)$(CONFIG_SOC_AMD_MERLINFALCON)$(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 08e7cc6..c21360b 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,13 +26,14 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_MERLINFALCON || SOC_AMD_PRAIRIEFALCON config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01 default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_MERLINFALCON + default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_PRAIRIEFALCON default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FP4 default "src/vendorcode/amd/pi/00670F00" if SOC_AMD_STONEYRIDGE_FT4 default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 @@ -46,6 +47,7 @@ default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 default "3rdparty/blobs/pi/amd/merlinfalcon/FP4/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_PRAIRIEFALCON default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/36823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I309c5918fdc98d9927641466bbe6149b97b250f0 Gerrit-Change-Number: 36823 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add UART support
by mturney mturney (Code Review) 26 Nov '19

26 Nov '19

mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35500 ) Change subject: sc7180: Add UART support ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… File src/soc/qualcomm/sc7180/uart.c: https://review.coreboot.org/c/coreboot/+/35500/11/src/soc/qualcomm/sc7180/u… PS11, Line 78: XBL > Sure, I will update in next patch Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb Gerrit-Change-Number: 35500 Gerrit-PatchSet: 18 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Nov 2019 22:11:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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