coreboot-gerrit November 2019

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Change in coreboot[master]: soc/intel/tigerlake: Fix smm_relocation_params
by Kyösti Mälkki (Code Review) 27 Nov '19

27 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37165 ) Change subject: soc/intel/tigerlake: Fix smm_relocation_params ...................................................................... soc/intel/tigerlake: Fix smm_relocation_params Platform is not yet build-tested, this should have gone in with commit f5c0d61 intel/smm: Provide common smm_relocation_params. Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smmrelocate.c 2 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37165/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2824e52..e93d87c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -36,6 +36,7 @@ select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 53f206d..46f550b 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -33,17 +33,6 @@ #include <soc/soc_chip.h> #include <soc/systemagent.h> -/* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; - -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) -- To view, visit https://review.coreboot.org/c/coreboot/+/37165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06 Gerrit-Change-Number: 37165 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail: Don't reinitialize SPI after lockdown
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36008 ) Change subject: soc/intel/baytrail: Don't reinitialize SPI after lockdown ...................................................................... soc/intel/baytrail: Don't reinitialize SPI after lockdown With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/southcluster.c 2 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36008/1 diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 7de9d96..7804253 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -233,22 +233,6 @@ } #endif -static void finalize(void) -{ - static int finalize_done; - - if (finalize_done) { - printk(BIOS_DEBUG, "SMM already finalized.\n"); - return; - } - finalize_done = 1; - -#if CONFIG(SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif -} - /* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are @@ -353,10 +337,6 @@ southbridge_smi_gsmi(); break; #endif - case APM_CNT_FINALIZE: - finalize(); - break; - case APM_CNT_LEGACY: soc_legacy(); break; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 3c0c07f..139d2be 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -577,9 +577,6 @@ write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } - - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - outb(APM_CNT_FINALIZE, APM_CNT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/36008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb Gerrit-Change-Number: 36008 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Select SOUTHBRIDGE_INTEL_COMMON_SPI
by Arthur Heymans (Code Review) 27 Nov '19

27 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33206 Change subject: soc/intel/baytrail: Select SOUTHBRIDGE_INTEL_COMMON_SPI ...................................................................... soc/intel/baytrail: Select SOUTHBRIDGE_INTEL_COMMON_SPI Use the common implementation. Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc D src/soc/intel/baytrail/spi.c 3 files changed, 2 insertions(+), 603 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33206/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 43c2906..1d4a4df 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -17,7 +17,9 @@ select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_SPI select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6e6eb9c..f99ea57 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -16,10 +16,6 @@ romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c -romstage-y += spi.c -postcar-y += spi.c -ramstage-y += spi.c -smm-y += spi.c ramstage-y += chip.c ramstage-y += gfx.c ramstage-y += iosf.c diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c deleted file mode 100644 index d5b962f..0000000 --- a/src/soc/intel/baytrail/spi.c +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include <stdint.h> -#include <stdlib.h> -#include <bootstate.h> -#include <delay.h> -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <spi_flash.h> -#include <spi-generic.h> - -#include <soc/lpc.h> -#include <soc/pci_devs.h> - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8((unsigned long)addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16((unsigned long)addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32((unsigned long)addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -void spi_init(void) -{ - ich9_spi_regs *ich9_spi = spi_regs(); - - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/33206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d Gerrit-Change-Number: 33206 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#25). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 446 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 25 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#33). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 + BP3 | DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows the coreboot to set CSE to boot from required boot partition(either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 33 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor cleanup some late comments
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Sridhar Siricilla has uploaded a new patch set (#11) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor cleanup some late comments ...................................................................... soc/intel/common/block/cse: Minor cleanup some late comments Made some changes based on comments received on merged patches. * Consistent HECI command/group ID naming * Add description for structure members. * Fix up HFSTS1 inconsistency between APL/GKL and rest of the platforms. * Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 23 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 11 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
by Angel Pons (Code Review) 27 Nov '19

27 Nov '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35170 ) Change subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot ...................................................................... soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35170/1 diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..740ce89 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -35,6 +35,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include <soc/systemagent.h> #include "../chip.h" @@ -50,6 +51,12 @@ fast_spi_early_init(SPI_BASE_ADDRESS); p2sb_enable_bar(); p2sb_configure_hpet(); + + /* Write the IOAPIC Bus:Dev.Fun value to P2SB IBDF register */ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF); + + /* Write the HPET Bus:Dev.Fun value to P2SB HBDF register */ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 43bf27c..ed33c20 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -484,10 +484,8 @@ params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = V_P2SB_IBDF_BUS; - params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV; - params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; + /* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */ + params->PchIoApicBdfValid = 0; } soc_irq_settings(params); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 565c885..91209c8 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -66,9 +66,11 @@ #define V_P2SB_IBDF_BUS 250 #define V_P2SB_IBDF_DEV 31 #define V_P2SB_IBDF_FUN 0 +#define V_DEFAULT_IBDF ((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN)) #define V_P2SB_HBDF_BUS 250 #define V_P2SB_HBDF_DEV 15 #define V_P2SB_HBDF_FUN 0 +#define V_DEFAULT_HBDF ((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN)) #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 4844660..a4d1d50 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -246,10 +246,8 @@ cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; - m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; - m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; + /* HPET Bus:Dev.Fun already set in coreboot, so tell FSP to ignore UPDs */ + m_cfg->PchHpetBdfValid = 0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Gerrit-Change-Number: 35170 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: src/drivers/ipmi: Implement BMC Get Self Test Result function
by Patrick Georgi (Code Review) 27 Nov '19

27 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37087 ) Change subject: src/drivers/ipmi: Implement BMC Get Self Test Result function ...................................................................... src/drivers/ipmi: Implement BMC Get Self Test Result function According to IPMI SPEC, it is recommended that BIOS includes provisions for checking and reporting on the basic health of BMC by executing the Get Self Test Results command and checking the result. TEST=Check the result in response data to confirm the BMC status is fine or not. Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> (cherry picked from commit 50155024141f48cf3048272073d352906a2be0b6) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37087 --- M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 72 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index f35802e..b377521 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -22,6 +22,12 @@ #define IPMI_BMC_GET_DEVICE_ID 0x01 #define IPMI_IPMI_VERSION_MINOR(x) ((x) >> 4) #define IPMI_IPMI_VERSION_MAJOR(x) ((x) & 0xf) +#define IPMI_BMC_GET_SELFTEST_RESULTS 0x04 +#define IPMI_APP_SELFTEST_RESERVED 0xFF +#define IPMI_APP_SELFTEST_NO_ERROR 0x55 +#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56 +#define IPMI_APP_SELFTEST_ERROR 0x57 +#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58 #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a @@ -52,4 +58,11 @@ uint8_t product_id[2]; } __packed; +/* Get Self Test Results */ +struct ipmi_selftest_rsp { + struct ipmi_rsp resp; + uint8_t result; + uint8_t param; +} __packed; + #endif diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 90f19dd..5cb8995 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -59,11 +59,34 @@ return 0; } +static int ipmi_get_bmc_self_test_result(struct device *dev, struct ipmi_selftest_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_APPLICATION, 0, + IPMI_BMC_GET_SELFTEST_RESULTS, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->resp.completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + + return 0; +} + static void ipmi_kcs_init(struct device *dev) { struct ipmi_devid_rsp rsp; uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = NULL; + struct ipmi_selftest_rsp selftestrsp; + uint8_t retry_count; if (!dev->enabled) return; @@ -92,6 +115,42 @@ } } + printk(BIOS_INFO, "Get BMC self test result..."); + for (retry_count = 0; retry_count < conf->bmc_boot_timeout; retry_count++) { + if (!ipmi_get_bmc_self_test_result(dev, &selftestrsp)) + break; + + mdelay(1000); + } + + switch (selftestrsp.result) { + case IPMI_APP_SELFTEST_NO_ERROR: /* 0x55 */ + printk(BIOS_DEBUG, "No Error\n"); + break; + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: /* 0x56 */ + printk(BIOS_DEBUG, "Function Not Implemented\n"); + break; + case IPMI_APP_SELFTEST_ERROR: /* 0x57 */ + printk(BIOS_ERR, "BMC: Corrupted or inaccessible data or device\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: /* 0x58 */ + printk(BIOS_ERR, "BMC: Fatal Hardware Error\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + case IPMI_APP_SELFTEST_RESERVED: /* 0xFF */ + printk(BIOS_DEBUG, "Reserved\n"); + break; + + default: /* Other Device Specific Hardware Error */ + printk(BIOS_ERR, "BMC: Device Specific Error\n"); + /* Don't write tables if communication failed */ + dev->enabled = 0; + break; + } + if (!ipmi_get_device_id(dev, &rsp)) { /* Queried the IPMI revision from BMC */ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); -- To view, visit https://review.coreboot.org/c/coreboot/+/37087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Gerrit-Change-Number: 37087 Gerrit-PatchSet: 2 Gerrit-Owner: Morgan Jang Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: google/jecht: add libgfxinit support
by Matt DeVillier (Code Review) 27 Nov '19

27 Nov '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37209 ) Change subject: google/jecht: add libgfxinit support ...................................................................... google/jecht: add libgfxinit support Tested on Guado variant Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/jecht/Kconfig M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37209/1 diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 41727c5..6d1fda9 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -7,6 +7,7 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 9ea24f6..ed71776 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -28,6 +28,8 @@ bootblock-y += bootblock.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/jecht/gma-mainboard.ads b/src/mainboard/google/jecht/gma-mainboard.ads new file mode 100644 index 0000000..3a92b59 --- /dev/null +++ b/src/mainboard/google/jecht/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/37209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3a42d1d69d11eebda25e60572f5d9a7452144c2 Gerrit-Change-Number: 37209 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/beltino: add libgfxinit support
by Matt DeVillier (Code Review) 27 Nov '19

27 Nov '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37208 ) Change subject: google/beltino: add libgfxinit support ...................................................................... google/beltino: add libgfxinit support Tested on Zako variant Change-Id: I433863b34731584797456eee6c2d270868a4f13f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/Kconfig M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37208/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 4b18c8c..01e0cbf 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -10,6 +10,7 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e1bebc1..3b763a0 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -22,5 +22,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/beltino/gma-mainboard.ads b/src/mainboard/google/beltino/gma-mainboard.ads new file mode 100644 index 0000000..3a92b59 --- /dev/null +++ b/src/mainboard/google/beltino/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/37208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I433863b34731584797456eee6c2d270868a4f13f Gerrit-Change-Number: 37208 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019