coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG@7 PS9, Line 7: soc/intel/common/block/cse: Minor cleanup for some late comments > The comment is still valid. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 12 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Nov 2019 14:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#26). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC. * FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME Verified that the basic update flows are working on Cometlake RVP and hatch. Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 446 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 26 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#34). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 + BP3 | DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows the coreboot to set CSE to boot from required boot partition(either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 34 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor clean up some late comments
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Sridhar Siricilla has uploaded a new patch set (#12) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor clean up some late comments ...................................................................... soc/intel/common/block/cse: Minor clean up some late comments Made some changes based on comments received on merged patches. * Consistent HECI command/group ID naming * Add description for structure members. * Fix up HFSTS1 inconsistency between APL/GKL and rest of the platforms. * Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 23 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 12 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Minor cleanup some late comments
by Paul Menzel (Code Review) 27 Nov '19

27 Nov '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor cleanup some late comments ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG@7 PS9, Line 7: soc/intel/common/block/cse: Minor cleanup for some late comments > Done The comment is still valid. -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 11 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Nov 2019 14:29:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Minor cleanup some late comments
by Sridhar Siricilla (Code Review) 27 Nov '19

27 Nov '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/common/block/cse: Minor cleanup some late comments ...................................................................... Patch Set 11: (3 comments) https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG@7 PS9, Line 7: soc/intel/common/block/cse: Minor cleanup for some late comments > Statement: […] Done https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG@15 PS9, Line 15: * Log some messages. > Separate commit please. Done https://review.coreboot.org/c/coreboot/+/35546/9//COMMIT_MSG@16 PS9, Line 16: Fixup > Fix up Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 11 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Nov 2019 13:53:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Add selectable APU names
by Marshall Dawson (Code Review) 27 Nov '19

27 Nov '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37219 ) Change subject: soc/amd/stoneyridge: Add selectable APU names ...................................................................... soc/amd/stoneyridge: Add selectable APU names Add APU names of STONEYRIDGE and MERLINFALCON to Kconfig. The existing convention of SOC_AMD_PRODUCTNAME_PKG will be phased out. Don't explicitely use the APU_STONEYRIDGE name yet when creating default paths. Prairie Falcon relies on the default setting, and this will be addressed in a later change. Change-Id: I2061b9b02f6e9def4e151fc38951ad8abb68df1d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 2 files changed, 31 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37219/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6454dec..b55833d 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -15,24 +15,27 @@ config SOC_AMD_STONEYRIDGE_FP4 bool + select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FP4 help AMD Stoney Ridge FP4 support config SOC_AMD_STONEYRIDGE_FT4 bool + select AMD_APU_STONEYRIDGE select AMD_APU_PKG_FT4 help AMD Stoney Ridge FT4 support config SOC_AMD_MERLINFALCON bool + select AMD_APU_MERLINFALCON select AMD_APU_PKG_FP4 help AMD Merlin Falcon FP4 support config HAVE_MERLINFALCON_BINARIES - depends on SOC_AMD_MERLINFALCON + depends on AMD_APU_MERLINFALCON bool "Merlinfalcon binaries are present" default n help @@ -81,6 +84,16 @@ select SSE2 select RTC +config AMD_APU_STONEYRIDGE + bool + help + AMD Stoney Ridge APU + +config AMD_APU_MERLINFALCON + bool + help + AMD Merlin Falcon APU + config AMD_APU_PKG_FP4 bool help @@ -155,7 +168,7 @@ config VGA_BIOS_ID string - default "1002,9874" if SOC_AMD_MERLINFALCON + default "1002,9874" if AMD_APU_MERLINFALCON default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the @@ -163,7 +176,7 @@ config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/VBIOS.bin" config S3_VGA_ROM_RUN @@ -212,7 +225,7 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/soc/amd/merlinfalcon/PSP/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON && HAVE_MERLINFALCON_BINARIES default "3rdparty/blobs/soc/amd/stoneyridge/PSP/AmdPubKeyST.bin" config STONEYRIDGE_SATA_MODE @@ -333,8 +346,7 @@ config SOC_AMD_PSP_SELECTABLE_SMU_FW bool - default n if SOC_AMD_MERLINFALCON - default y + default y if AMD_APU_STONEYRIDGE help Some ST implementations allow storing SMU firmware into cbfs and calling the PSP to load the blobs at the proper time. diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index b74bc68..f697fc2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -137,11 +137,23 @@ ### 0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) + +ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) +FIRMWARE_TYPE=ST +else + +ifeq ($(CONFIG_AMD_APU_MERLINFALCON),y) +# If Merlin Falcon, but blobs aren't present, use Stoney Ridge instead ifeq ($(CONFIG_HAVE_MERLINFALCON_BINARIES),y) FIRMWARE_TYPE=CZ else FIRMWARE_TYPE=ST -endif +endif # CONFIG_HAVE_MERLINFALCON_BINARIES +else +$(error stoneyridge: Unknown FIRMWARE_TYPE) + +endif # CONFIG_AMD_APU_MERLINFALCON +endif # CONFIG_AMD_APU_STONEYRIDGE ###5 PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -- To view, visit https://review.coreboot.org/c/coreboot/+/37219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2061b9b02f6e9def4e151fc38951ad8abb68df1d Gerrit-Change-Number: 37219 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Add selectable packages
by Marshall Dawson (Code Review) 27 Nov '19

27 Nov '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37218 ) Change subject: soc/amd/stoneyridge: Add selectable packages ...................................................................... soc/amd/stoneyridge: Add selectable packages The StoneyPI package supports Family 15h Models 60h-6Fh and 70h-7Fh in FT4 and FP4 packages. Add options for the packages. The existing convention of SOC_AMD_PRODUCTNAME_PKG will be phased out. Change-Id: I60232ca099b813640742868db08aa66b32265f3b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/Kconfig 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37218/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff..6454dec 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -15,16 +15,19 @@ config SOC_AMD_STONEYRIDGE_FP4 bool + select AMD_APU_PKG_FP4 help AMD Stoney Ridge FP4 support config SOC_AMD_STONEYRIDGE_FT4 bool + select AMD_APU_PKG_FT4 help AMD Stoney Ridge FT4 support config SOC_AMD_MERLINFALCON bool + select AMD_APU_PKG_FP4 help AMD Merlin Falcon FP4 support @@ -78,6 +81,21 @@ select SSE2 select RTC +config AMD_APU_PKG_FP4 + bool + help + AMD FP4 package + +config AMD_APU_PKG_FT4 + bool + help + AMD FT4 package + +config AMD_SOC_PACKAGE + string + default "FP4" if AMD_APU_PKG_FP4 + default "FT4" if AMD_APU_PKG_FT4 + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 08e7cc6..0605563 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -44,10 +44,10 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/pi/amd/merlinfalcon/FP4/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES - default "3rdparty/blobs/pi/amd/00670F00/FP4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 + default "3rdparty/blobs/pi/amd/merlinfalcon/$(CONFIG_AMD_SOC_PACKAGE)/AGESA_CZ_FP4.bin" if SOC_AMD_MERLINFALCON && HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_MERLINFALCON && !HAVE_MERLINFALCON_BINARIES + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FP4 + default "3rdparty/blobs/pi/amd/00670F00/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if SOC_AMD_STONEYRIDGE_FT4 default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/37218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60232ca099b813640742868db08aa66b32265f3b Gerrit-Change-Number: 37218 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Clean up report_cpu_info() function
by Usha P (Code Review) 27 Nov '19

27 Nov '19

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36840 ) Change subject: soc/intel/skylake: Clean up report_cpu_info() function ...................................................................... soc/intel/skylake: Clean up report_cpu_info() function This patch makes below clean up for report_cpu_info() function 1. Replace cpu_string with cpu_not_found 2. Assign default string "Platform info not available" to cpu_not_found string 3. Add array out of bound check while skiping leading white space in cpu brand string name TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/skylake/bootblock/report_platform.c 1 file changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36840/1 diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 0bd65c3..6eec951 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -166,7 +166,8 @@ { struct cpuid_result cpuidr; u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ + const char cpu_not_found[] = "Platform info not available"; + const char *cpu_name = cpu_not_found; int vt, txt, aes; msr_t microcode_ver; static const char *const mode[] = {"NOT ", ""}; @@ -174,10 +175,8 @@ index = 0x80000000; cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *) cpu_string; + if (cpuidr.eax >= 0x80000004) { + u32 *p = (u32 *) cpu_not_found; for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; @@ -187,7 +186,7 @@ } } /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') + while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) cpu_name++; microcode_ver.lo = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/36840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe Gerrit-Change-Number: 36840 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
by Surendranath R Gurivireddy (Code Review) 27 Nov '19

27 Nov '19

Surendranath R Gurivireddy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36519 ) Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP] ...................................................................... soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP] Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy(a)intel.com> Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36519/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4..27b109d 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -273,6 +273,9 @@ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } + /* Disable USB2 PHY Power gating */ + params->PchUsb2PhySusPgEnable = 0; + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; -- To view, visit https://review.coreboot.org/c/coreboot/+/36519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Gerrit-Change-Number: 36519 Gerrit-PatchSet: 1 Gerrit-Owner: Surendranath R Gurivireddy <surendranath.r.gurivireddy(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019