Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31450
to review the following change.
Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
......................................................................
lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S
which is currently not used by any of coreboot-supported boards. Also
enable the discrete graphics PCI bus leading to HD 8570M (1002,6663)
or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround
for PCI resource allocation problems to AMD AGESA vendorcode.
Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu>
Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
---
M src/device/Kconfig
M src/mainboard/lenovo/g505s/devicetree.cb
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
3 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 33c1e5b3..5d2087e 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -247,8 +247,15 @@
Enable this option for a good compromise between security and speed.
config MULTIPLE_VGA_ADAPTERS
+ prompt "Multiple VGA Adapters"
bool
+ depends on BOARD_LENOVO_G505S
default n
+ help
+ Some motherboards may have more than one VGA adapter - for example,
+ there are versions of Lenovo G505S that have a discrete VGA adapter
+ in addition to its' integrated VGA adapter which is a part of APU.
+ Enable this option to try to initialize this discrete VGA adapter.
menu "Display"
depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 99f42d6..1f33c27 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -27,7 +27,7 @@
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 off end
+ device pci 2.0 on end # Discrete Graphics PCI bus 0x666X
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index c566061..ee6d2c2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -437,8 +437,15 @@
RefPtr = MemPtr->ParameterListPtr;
// Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
+ if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) &&
+ (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) {
+ // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems
+ RefPtr->BottomIo = 0xD0;
+ }
+ else {
+ // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+ RefPtr->BottomIo = 0xE0;
+ }
RefPtr->UmaMode = UserOptions.CfgUmaMode;
RefPtr->UmaSize = UserOptions.CfgUmaSize;
RefPtr->MemHoleRemapping = TRUE;
--
To view, visit https://review.coreboot.org/c/coreboot/+/31450
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
Gerrit-Change-Number: 31450
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36192 )
Change subject: vc/amd/agesa/f16kb: Fix out of bounds read
......................................................................
vc/amd/agesa/f16kb: Fix out of bounds read
ByteLane is incorrectly used unitialized from prior for statement.
Found nothing in following code that attempted to reference
PassTestRxEnDly at that index, so appears safe to delete.
Additionally, found nothing following with the
OutOfRange[ByteLane]==TRUE condition that would expect
'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'.
Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd(a)danwin1210.me>
Found-by: Coverity CID 1241804
---
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/1
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
index ce295ac..caf8f51 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
@@ -314,7 +314,6 @@
//
IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t Setting PassTestRxEnDly\n");
IDS_HDT_CONSOLE (MEM_FLOW, "\t PassTestRxEnDly: ");
- PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];
for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) {
if (RxEnDlyTargetFound[ByteLane] == FALSE) {
// Calculate "PassTestRxEnDly" from current "RxEnDly"
--
To view, visit https://review.coreboot.org/c/coreboot/+/36192
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Gerrit-Change-Number: 36192
Gerrit-PatchSet: 1
Gerrit-Owner: awokd(a)danwin1210.me
Gerrit-MessageType: newchange
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36177 )
Change subject: util/lint: Enforce SPDX licenses only in src/acpi directory
......................................................................
util/lint: Enforce SPDX licenses only in src/acpi directory
Signed-off-by: Martin Roth <martin(a)coreboot.org>
Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680
---
M util/lint/lint-stable-000-license-headers
1 file changed, 5 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36177/1
diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers
index 441e679..fcaf32c 100755
--- a/util/lint/lint-stable-000-license-headers
+++ b/util/lint/lint-stable-000-license-headers
@@ -1,22 +1,14 @@
#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-only
# This file is part of the coreboot project.
#
-# Copyright (C) 2016 Google Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-#
# DESCR: Check that files have license headers
+# Directories requiring SPDX Identifiers only
+util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY
+
# Top level
-util/lint/lint-000-license-headers "src/acpi src/arch src/commonlib src/console \
+util/lint/lint-000-license-headers "src/arch src/commonlib src/console \
src/cpu src/device src/ec src/mainboard src/northbridge src/soc \
src/southbridge src/superio"
--
To view, visit https://review.coreboot.org/c/coreboot/+/36177
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680
Gerrit-Change-Number: 36177
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange