Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34464 )
Change subject: src/soc/intel/byatrail: Add minimal SMBus support
......................................................................
src/soc/intel/byatrail: Add minimal SMBus support
Change-Id: I6b7bdbc94cfbc9fbd8eda92ca924c74638388bfb
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/Makefile.inc
A src/soc/intel/baytrail/smbus.c
3 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/34464/1
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 4b816a2..f5a1d81 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -40,6 +40,7 @@
select POSTCAR_CONSOLE
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
+ select SOUTHBRIDGE_INTEL_COMMON_SMBUS
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 3ad6a8f..55af6e6 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -12,6 +12,7 @@
romstage-y += iosf.c
romstage-y += memmap.c
romstage-y += pmutil.c
+romstage-y += smbus.c
romstage-y += spi.c
romstage-y += stage_cache.c
romstage-y += tsc_freq.c
@@ -42,6 +43,7 @@
ramstage-y += sata.c
ramstage-y += scc.c
ramstage-y += sd.c
+ramstage-y += smbus.c
ramstage-y += smm.c
ramstage-y += southcluster.c
ramstage-y += spi.c
diff --git a/src/soc/intel/baytrail/smbus.c b/src/soc/intel/baytrail/smbus.c
new file mode 100644
index 0000000..91dd173
--- /dev/null
+++ b/src/soc/intel/baytrail/smbus.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2019 3mdeb
+ * Copyright (C) 2019 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/early_smbus.h>
+#include <soc/iomap.h>
+#include <southbridge/intel/common/smbus.h>
+
+u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
+{
+ return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset);
+}
+
+u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
+{
+ return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6b7bdbc94cfbc9fbd8eda92ca924c74638388bfb
Gerrit-Change-Number: 34464
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange