Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34663 )
Change subject: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
......................................................................
soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
SATA Mode Select is bit 16 of the SATA General Configuration
register. This code currently incorrectly pokes at the Port Clock
Disable bits in the Port Mapping Register, and without clock the
affected ports can't link.
Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com>
---
M src/soc/intel/denverton_ns/sata.c
1 file changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34663/1
diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c
index ddb8b02..610a4c6 100644
--- a/src/soc/intel/denverton_ns/sata.c
+++ b/src/soc/intel/denverton_ns/sata.c
@@ -31,7 +31,6 @@
static void sata_init(struct device *dev)
{
u32 reg32;
- u16 reg16;
u32 abar;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -46,10 +45,9 @@
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set the controller mode */
- reg16 = pci_read_config16(dev, SATA_MAP);
- reg16 &= ~(3 << 6);
- reg16 |= SATA_MAP_AHCI;
- pci_write_config16(dev, SATA_MAP, reg16);
+ reg32 = pci_read_config16(dev, SATAGC);
+ reg32 &= ~SATAGC_AHCI;
+ pci_write_config16(dev, SATAGC, reg32);
/* Initialize AHCI memory-mapped space */
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Gerrit-Change-Number: 34663
Gerrit-PatchSet: 1
Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com>
Gerrit-MessageType: newchange