coreboot-gerrit October 2019

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Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: README: Spell Web site with one space
by Paul Menzel (Code Review) 03 Mar '20

03 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos: Add unzip as a dependency
by Mete Balci (Code Review) 03 Mar '20

03 Mar '20

Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821 Change subject: util/chromeos: Add unzip as a dependency ...................................................................... util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84..0564106 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() -- To view, visit https://review.coreboot.org/c/coreboot/+/31821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Gerrit-Change-Number: 31821 Gerrit-PatchSet: 1 Gerrit-Owner: Mete Balci <metebalci(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: clang-format: set to 80 chars per line
by Philipp Deppenwiese (Code Review) 03 Mar '20

03 Mar '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31947 Change subject: clang-format: set to 80 chars per line ...................................................................... clang-format: set to 80 chars per line Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M .clang-format 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31947/1 diff --git a/.clang-format b/.clang-format index d853f50..c292e2f 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 80 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false -- To view, visit https://review.coreboot.org/c/coreboot/+/31947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Gerrit-Change-Number: 31947 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi_s3: Remove trailing dots from debug message
by Paul Menzel (Code Review) 02 Mar '20

02 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806 Change subject: x86/acpi_s3: Remove trailing dots from debug message ...................................................................... x86/acpi_s3: Remove trailing dots from debug message The dot is not needed, as it is no sentence and followed by a line break. Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/arch/x86/acpi_s3.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..07c0332 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -34,10 +34,10 @@ { if (acpi_slp_type < 0) { if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume.\n"); + printk(BIOS_DEBUG, "S3 Resume\n"); acpi_slp_type = ACPI_S3; } else { - printk(BIOS_DEBUG, "Normal boot.\n"); + printk(BIOS_DEBUG, "Normal boot\n"); acpi_slp_type = ACPI_S0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624 Gerrit-Change-Number: 30806 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/superiotool: Add AST2400
by Patrick Rudolph (Code Review) 01 Mar '20

01 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32984 Change subject: util/superiotool: Add AST2400 ...................................................................... util/superiotool: Add AST2400 Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for PCI devices and known bits in scratch registers. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M util/superiotool/Makefile A util/superiotool/aspeed.c M util/superiotool/superiotool.h 3 files changed, 161 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32984/1 diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 3a0bcf0..d1d7f243 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -OBJS += pci.o via.o amd.o +OBJS += pci.o via.o amd.o aspeed.o LIBS += -lpci ifeq ($(OS_ARCH),NetBSD) LIBS += -lpciutils diff --git a/util/superiotool/aspeed.c b/util/superiotool/aspeed.c new file mode 100644 index 0000000..0a7b624 --- /dev/null +++ b/util/superiotool/aspeed.c @@ -0,0 +1,151 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks <dhendrix(a)google.com> for Aspeed Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "superiotool.h" + +#define DEVICE_SCRATCH_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x00, "AST2400", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x02,RSVD,EOT}}, + {0x03, "SUART1", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x02,0x00,EOT}}, + {0x04, "SWC", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x70,0x71,EOT}, + {0x00,0x08,0xe6,0x08,0xe0,0x08,0xe4,0x08,0xe8, + 0x09,0x01,EOT}}, + {0x05, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73, + 0xf0,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x0c,0x02, + 0x83,EOT}}, + {0x07, "GPIO", + {0x30,0x38,0x70,0x71,EOT}, + {0x00,0x00,0x0b,0x01,EOT}}, + {0x0b, "SUART3", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x03,0xe8,0x06,0x02,0x00,EOT}}, + {0x0c, "SUART4", + {0x30,0x60,0x61,0x70,0x71,0xf0,EOT}, + {0x00,0x02,0xe8,0x05,0x02,0x00,EOT}}, + {0x0d, "iLPC2AHB", + {0x30,0x70,0x71,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xfe,EOT}, + {0x00,0x09,0x01,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,0x00,0x00,EOT}}, + {0x0e, "Mailbox", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x08,0xc0,0x09,0x01,EOT}}, + {EOT}}}, + {EOT} +}; + +static void enter_conf_mode_ast(uint16_t port) +{ + OUTB(0xa5, port); + OUTB(0xa5, port); +} + +static void exit_conf_mode_ast(uint16_t port) +{ + OUTB(0xaa, port); +} + +static int detect_ast_pci(void) +{ + int i; + static const uint16_t ids[] = { + 0x2000, 0x1150, + }; + + for (i = 0; i < ARRAY_SIZE(ids); i++) { + if (pci_dev_find(0x1a03, ids[i])) + return 1; + } + + return 0; +} + +static int detect_ast_superio(uint16_t port) +{ + int i; + enter_conf_mode_ast(port); + + /* Aspeed devices doesn't have a DEVICE_ID_REG. + * Host cycles that aren't decoded read as 0xff. + * Probe for the scratch register that are initialized to zero. + * The firmware might overwrite that, but it's the best we have. + * Together with PCI detection that should be sufficient. + */ + + for (i = DEVICE_SCRATCH_REG; i < 0x30; i++) { + if (regval(port, i) == 0) + break; + } + if (i == 0x30) { + if (verbose) + printf(NOTFOUND + "scratch registers all read as non zero\n"); + } + exit_conf_mode_ast(port); + + return i < 0x30; +} + +void probe_idregs_aspeed(uint16_t port) +{ + uint16_t chip_id = 0; + + probing_for("Aspeed", "", port); + + if (!detect_ast_pci()) { + if (verbose) + printf(NOTFOUND "missing PCI device\n"); + return; + } + + if (!detect_ast_superio(port)) + return; + + if (superio_unknown(reg_table, chip_id)) { + if (verbose) + printf(NOTFOUND "id=0x%02x\n", chip_id); + return; + } + + printf("Found Aspeed %s (id=0x%02x) at 0x%x\n", + get_superio_name(reg_table, chip_id), chip_id, port); + chip_found = 1; + + enter_conf_mode_ast(port); + dump_superio("Aspeed", reg_table, port, chip_id, LDN_SEL); + exit_conf_mode_ast(port); +} + +void print_aspeed_chips(void) +{ + print_vendor_chips("Aspeed", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1a10fb6..f2a4d5e 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -184,6 +184,12 @@ void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* aspeed.c */ +#ifdef PCI_SUPPORT +void probe_idregs_aspeed(uint16_t port); +void print_aspeed_chips(void); +#endif + /* amd.c */ void probe_idregs_amd(uint16_t port); void print_amd_chips(void); @@ -252,6 +258,8 @@ {probe_idregs_via, {0x2e, 0x4e, 0x3f0, EOT}}, /* in fact read the BASE from HW */ {probe_idregs_amd, {0xaa, EOT}}, + /* Probe for aspeed PCI devices */ + {probe_idregs_aspeed, {0x2e, 0x4e, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, {probe_idregs_infineon, {0x2e, 0x4e, EOT}}, @@ -272,6 +280,7 @@ #ifdef PCI_SUPPORT {print_via_chips}, {print_amd_chips}, + {print_aspeed_chips}, #endif {print_serverengines_chips}, {print_infineon_chips}, -- To view, visit https://review.coreboot.org/c/coreboot/+/32984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Gerrit-Change-Number: 32984 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
by Nicola Corna (Code Review) 17 Feb '20

17 Feb '20

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470 Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 ...................................................................... mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3 thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01 (Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3). This is true for most of the Thinkpads, however on the X1 Carbon Gen1 (and possibly others), the battery hotkey is not present and the lock one is instead on Fn-F3. Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so that the lock hotkey is on F3 and the battery one is on F2 (even if it's not marked so). Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 327a2cf..6ffba5e 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -197,12 +197,20 @@ Method (_Q11, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x03) +#else ^HKEY.RHK (0x02) +#endif } Method (_Q12, 0, NotSerialized) { +#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3) + ^HKEY.RHK (0x02) +#else ^HKEY.RHK (0x03) +#endif } Method (_Q64, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8c9bd5a..2696607 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -20,6 +20,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 +#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1 #include <arch/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/31470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca Gerrit-Change-Number: 31470 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for...
by Michał Żygowski (Code Review) 17 Feb '20

17 Feb '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35313 ) Change subject: src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports ...................................................................... src/northbridge/amd/pi/00730F01/northbridge.c: enable ACS and AER for PCIe ports Currently it is impossible to enable ACS with AGESA by setting the correct bit for AmdInitMid phase. AGESA code path does not call the right function that enables these functionalities. Disabled ACS result in multiple PCIe devices to be assigned to the same IOMMU group. Without IOMMU group separation the devices cannot be passed through independently. Enable Access Control Services and Advanced Error Reporting for PCI Express bridges in order to have PCIe devices in separate IOMMU groups for correct passthrough. TEST=run dmesg on Debian Buster and check whether PCIe devices have separate groups Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/35313/1 diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ba17c61..fede1e9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -783,6 +783,25 @@ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + /* Select GPP link core IO Link Strap Control register 0xB0 */ + pci_write_config32(dev, 0xE0, 0x014000B0); + value = pci_read_config32(dev, 0xE4); + + /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ + value |= (BIT(5) | BIT(6)); + pci_write_config32(dev, 0xE4, value); + + /* Select GPP link core Wrapper register 0x00 (undocumented) */ + pci_write_config32(dev, 0xE0, 0x01300000); + value = pci_read_config32(dev, 0xE4); + + /* Enable ACS capabilities straps including sub-items. From lspci it + * looks like these bits enable: Source Validation and Translation + * Blocking + */ + value |= (BIT(24) | BIT(25) | BIT(26)); + pci_write_config32(dev, 0xE4, value); + /* disable No Snoop */ dev = pcidev_on_root(1, 1); if (dev != NULL) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a8eff0ba37196692f9db6519e498fe535ecd15 Gerrit-Change-Number: 35313 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/k8resdump: Remove util
by Arthur Heymans (Code Review) 17 Feb '20

17 Feb '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36085 ) Change subject: util/k8resdump: Remove util ...................................................................... util/k8resdump: Remove util AMD K8 support dropped. Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D util/k8resdump/Makefile D util/k8resdump/description.md D util/k8resdump/k8resdump.c 3 files changed, 0 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36085/1 diff --git a/util/k8resdump/Makefile b/util/k8resdump/Makefile deleted file mode 100644 index a1d4dfa..0000000 --- a/util/k8resdump/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -## -## Makefile for k8resdump utility -## -## (C) 2005 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -PROGRAM = k8resdump - -CC = gcc -INSTALL = /usr/bin/env install -PREFIX = /usr/local -#CFLAGS = -O2 -g -Wall -Werror -CFLAGS = -Os -Wall -Werror -OS_ARCH = $(shell uname) -ifeq ($(OS_ARCH), SunOS) -LDFLAGS = -lpci -else -LDFLAGS = -lpci -lz -static -endif - -OBJS = k8resdump.o - -all: pciutils dep $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - rm -f *.o *~ - -distclean: clean - rm -f $(PROGRAM) .dependencies - -dep: - @$(CC) -MM *.c > .dependencies - -pciutils: - @echo; echo -n "Checking for pciutils and zlib... " - @$(shell ( echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ - echo "found." || ( echo "not found."; echo; \ - echo "Please install pciutils-devel and zlib-devel."; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test; exit 1) - @rm -f .test.c .test - -.PHONY: all clean distclean dep pciutils - --include .dependencies diff --git a/util/k8resdump/description.md b/util/k8resdump/description.md deleted file mode 100644 index dd1f144..0000000 --- a/util/k8resdump/description.md +++ /dev/null @@ -1,2 +0,0 @@ -This program will dump the IO/memory/PCI resources from the K8 memory -controller `C` diff --git a/util/k8resdump/k8resdump.c b/util/k8resdump/k8resdump.c deleted file mode 100644 index 66d7060..0000000 --- a/util/k8resdump/k8resdump.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This program will dump the IO/memory/PCI resources from the K8 - * memory controller - */ - -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <unistd.h> -#include <sys/types.h> -#include <pci/pci.h> - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -static uint8_t dram_bases[] = - { 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78 }; -static uint8_t dram_limits[] = - { 0x44, 0x4C, 0x54, 0x5C, 0x64, 0x6C, 0x74, 0x7C }; -static uint8_t iomem_bases[] = - { 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8 }; -static uint8_t iomem_limits[] = - { 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC }; - -static uint8_t pciio_bases[] = { 0xC0, 0xC8, 0xD0, 0xD8 }; -static uint8_t pciio_limits[] = { 0xC4, 0xCC, 0xD4, 0xDC }; - -void print_info(struct pci_dev *dev) -{ - int i; - uint32_t regb, regl; - - for (i = 0; i < ARRAY_SIZE(dram_bases); i++) { - regb = pci_read_long(dev, dram_bases[i]); - regl = pci_read_long(dev, dram_limits[i]); - - printf - ("DRAM map: #%d 0x%04x000000 - 0x%04xffffff Access: %s/%s" - " IntlvEN:0x%x IntlvSEL:0x%x Dstnode:%d\n", - i, regb >> 16, regl >> 16, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", (regb & 0x700) >> 8, - (regl & 0x700) >> 8, (regl & 0x7)); - } - - - for (i = 0; i < ARRAY_SIZE(iomem_bases); i++) { - regb = pci_read_long(dev, iomem_bases[i]); - regl = pci_read_long(dev, iomem_limits[i]); - - printf - ("MMIO map: #%d 0x%06x0000 - 0x%06xffff Access: %s/%s %s %s" - " %s Dstnode:%d DstLink %d\n", - i, regb >> 8, regl >> 8, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 4 ? "CPU Dis" : "", - regb & 8 ? "Locked" : "", - regl & 0x80 ? "NonPosted" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - for (i = 0; i < ARRAY_SIZE(pciio_bases); i++) { - regb = pci_read_long(dev, pciio_bases[i]); - regl = pci_read_long(dev, pciio_limits[i]); - - printf - (" IO map: #%d 0x%03x000 - 0x%03xfff Access: %s/%s %s %s" - " Dstnode:%d DstLink %d\n", - i, (regb & ~0xff000000) >> 12, - (regl & ~0xff000000) >> 12, regb & 1 ? "R" : "", - regb & 2 ? "W" : "", regb & 0x20 ? "ISA" : "", - regb & 0x10 ? "VGA" : "", regl & 0x7, - (regl & 0x30) >> 4); - } - - -} - -int main(void) -{ - struct pci_access *pacc; - struct pci_dev *dev; - - if (getuid()) { - fprintf(stderr, "Please run me root, need access to all" - " PCI regs!\n"); - exit(1); - } - - pacc = pci_alloc(); - pci_init(pacc); - pci_scan_bus(pacc); - for (dev = pacc->devices; dev; dev = dev->next) { - pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | - PCI_FILL_CLASS); - if ((dev->vendor_id == 0x1022) /* AMD */ - && (dev->device_id == 0x1101)) { /* Address MAP */ - print_info(dev); - } - } - pci_cleanup(pacc); - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Gerrit-Change-Number: 36085 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple/macbookair4_2: Add CMOS support
by Evgeny Zinoviev (Code Review) 17 Feb '20

17 Feb '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33045 Change subject: mb/apple/macbookair4_2: Add CMOS support ...................................................................... mb/apple/macbookair4_2: Add CMOS support Added CMOS support for MacBook Air 4,2. In future, I hope there will be more useful options available, because I'm working on macbooks support. Also, it may be necessary for hyper_threading support (#29669) once it will be ready. Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/mainboard/apple/macbookair4_2/Kconfig A src/mainboard/apple/macbookair4_2/cmos.default A src/mainboard/apple/macbookair4_2/cmos.layout 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33045/1 diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 4b2ee8f..263d550 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -14,6 +14,8 @@ select SYSTEM_TYPE_LAPTOP select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout new file mode 100644 index 0000000..86d55b4 --- /dev/null +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +# ----------------------------------------------------------------- +entries +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight +# coreboot config options: cpu +#424 8 r 0 unused +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +# coreboot config options: check sums +984 16 h 0 check_sum +# ----------------------------------------------------------------- +enumerations +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums +checksum 392 447 984 -- To view, visit https://review.coreboot.org/c/coreboot/+/33045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e Gerrit-Change-Number: 33045 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019