coreboot-gerrit October 2019

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Change in ...coreboot[master]: nb/i945: Consolidate sdram_setup_processor_side()
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33781 Change subject: nb/i945: Consolidate sdram_setup_processor_side() ...................................................................... nb/i945: Consolidate sdram_setup_processor_side() Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33781/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 281e7b2..c994786 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2695,13 +2695,11 @@ static void sdram_setup_processor_side(void) { - if (i945_silicon_revision() == 0) + if (i945_silicon_revision() == 0) { MCHBAR32(FSBPMC3) |= (1 << 2); - - MCHBAR8(0xb00) |= 1; - - if (i945_silicon_revision() == 0) MCHBAR32(SLPCTL) |= (1 << 8); + } + MCHBAR8(0xb00) |= 1; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/33781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5aae06ae8e3643253fe4a5b080448403f81ebc Gerrit-Change-Number: 33781 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/i945: Remove unneeded whitespaces
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36467 ) Change subject: nb/i945: Remove unneeded whitespaces ...................................................................... nb/i945: Remove unneeded whitespaces Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/36467/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7096774..27fdf00 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -816,9 +816,9 @@ const u8 *slew_group; /* Dual Channel needs different tables. */ if (dual_channel) - slew_group = dual_channel_slew_group_lookup; + slew_group = dual_channel_slew_group_lookup; else - slew_group = single_channel_slew_group_lookup; + slew_group = single_channel_slew_group_lookup; switch (slew_group[index]) { case DQ2030: return dq2030; @@ -957,7 +957,7 @@ printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; dual_channel = 1; - idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; + idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; @@ -1209,7 +1209,7 @@ if (sysinfo->interleaved) tolud = (cum0 + cum1) << 1; else - tolud = (cum1 ? cum1 : cum0) << 1; + tolud = (cum1 ? cum1 : cum0) << 1; /* The TOM register has a different format */ tom = tolud >> 3; @@ -1349,7 +1349,7 @@ reg32 |= (1 << 11); MCHBAR32(C0DRC1) = reg32; - /* Do we have to do this if we're in Single Channel Mode? */ + /* Do we have to do this if we're in Single Channel Mode? */ reg32 = MCHBAR32(C1DRC1); for (i = 4; i < 8; i++) { @@ -1706,7 +1706,7 @@ if (voltage == VOLTAGE_1_50) { second_vco = 1; - } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { + } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -2034,7 +2034,7 @@ u32 chan0 = 0, chan1 = 0; int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; - chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); @@ -2514,7 +2514,7 @@ } #define RTT_ODT_NONE 0 -#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) +#define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) #define RTT_ODT_75_OHM (1 << 5) #define RTT_ODT_150_OHM (1 << 9) -- To view, visit https://review.coreboot.org/c/coreboot/+/36467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1cbb5d466666eff6006d1137525dd5fb0de8e18 Gerrit-Change-Number: 36467 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: Remove never used 'dra' value
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34558 ) Change subject: nb/intel/i440bx: Remove never used 'dra' value ...................................................................... nb/intel/i440bx: Remove never used 'dra' value Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i440bx/raminit.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34558/1 diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 91959c7..3a1b66a 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -799,7 +799,6 @@ } /* "DRA" is our RPS for the two rows on this DIMM. */ - dra = 0; /* Columns */ col = spd_read_byte(device, SPD_NUM_COLUMNS); -- To view, visit https://review.coreboot.org/c/coreboot/+/34558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c41f56d7a0639eac821844e653e5644aca4f0c Gerrit-Change-Number: 34558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34434 ) Change subject: nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT ...................................................................... nb/intel/x4x/gma: Store 'vga_disable' if MAINBOARD_USE_LIBGFXINIT Found-by: scan-build 7.0.1-8 Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/gma.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34434/1 diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 61731fe..6577153 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -68,9 +68,8 @@ /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); - int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6feaa3a19d44b1d6f650bc7bc72dc575b032f4b1 Gerrit-Change-Number: 34434 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/cimx/{sb800,sb900}: Remove some superfluous comments
by HAOUAS Elyes (Code Review) 07 Jan '20

07 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36227 ) Change subject: sb/amd/cimx/{sb800,sb900}: Remove some superfluous comments ...................................................................... sb/amd/cimx/{sb800,sb900}: Remove some superfluous comments Change-Id: Ied64879d294670d452845ff47d417d595b72864a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/cimx/sb900/lpc.c M src/southbridge/amd/cimx/sb900/smbus.c 5 files changed, 9 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36227/1 diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 4233a6f..67938c5 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -17,16 +17,16 @@ #include <device/mmio.h> #include <device/device.h> -#include <device/pci.h> /* device_operations */ +#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include <bootstate.h> #include <arch/ioapic.h> -#include <device/smbus.h> /* smbus_bus_operations */ +#include <device/smbus.h> #include <pc80/mc146818rtc.h> #include <pc80/i8254.h> #include <pc80/i8259.h> -#include <console/console.h> /* printk */ +#include <console/console.h> #include <arch/acpi.h> #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index a4426ff..f54bcd3 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -13,10 +13,9 @@ * GNU General Public License for more details. */ - #include <arch/io.h> #include "smbus.h" -#include <console/console.h> /* printk */ +#include <console/console.h> static int smbus_wait_until_ready(u32 smbus_io_base) { diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 3a65e33..423b996 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -13,15 +13,14 @@ * GNU General Public License for more details. */ - #include <device/device.h> -#include <device/pci.h> /* device_operations */ +#include <device/pci.h> #include <device/pci_ids.h> -#include <device/smbus.h> /* smbus_bus_operations */ +#include <device/smbus.h> #include <pc80/mc146818rtc.h> #include <pc80/i8254.h> #include <pc80/i8259.h> -#include <console/console.h> /* printk */ +#include <console/console.h> #include <device/pci_ehci.h> #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 8e7c1cc..3f365bd 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -16,10 +16,9 @@ #include <device/pci.h> #include <device/pci_ops.h> #include "lpc.h" -#include <console/console.h> /* printk */ +#include <console/console.h> #include <arch/ioapic.h> - void lpc_read_resources(struct device *dev) { struct resource *res; diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 389aa8e..cc76c64 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -13,10 +13,9 @@ * GNU General Public License for more details. */ - #include <arch/io.h> #include "smbus.h" -#include <console/console.h> /* printk */ +#include <console/console.h> static int smbus_wait_until_ready(u32 smbus_io_base) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied64879d294670d452845ff47d417d595b72864a Gerrit-Change-Number: 36227 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/smc: Add and use new tool smcbiosinfo
by Patrick Rudolph (Code Review) 06 Jan '20

06 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35484 ) Change subject: util/smc: Add and use new tool smcbiosinfo ...................................................................... util/smc: Add and use new tool smcbiosinfo The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/supermicro/x11ssh/Kconfig M src/vendorcode/Makefile.inc A src/vendorcode/smc/Makefile.inc A util/smc/smcbiosinfo/Makefile A util/smc/smcbiosinfo/description.md A util/smc/smcbiosinfo/smcbiosinfo.c 6 files changed, 237 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35484/1 diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11ssh/Kconfig index e6f342d..8ee47b8 100644 --- a/src/mainboard/supermicro/x11ssh/Kconfig +++ b/src/mainboard/supermicro/x11ssh/Kconfig @@ -76,4 +76,8 @@ int default 512 +config SUPERMICRO_BOARDID + string + default "089C" + endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 8ccb0d0..d79fb0b 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan +subdirs-y += smc diff --git a/src/vendorcode/smc/Makefile.inc b/src/vendorcode/smc/Makefile.inc new file mode 100644 index 0000000..f1ac3a6 --- /dev/null +++ b/src/vendorcode/smc/Makefile.inc @@ -0,0 +1,19 @@ +ifeq ($(CONFIG_VENDOR_SUPERMICRO),y) +ifneq ($(CONFIG_SUPERMICRO_BOARDID), "") + +SMCBIOSINFOTOOL:=util/smc/smcbiosinfo/smcbiosinfo +cbfs-files-y += smcbiosinfo.bin + +smcbiosinfo.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/smcbiosinfo.bin +smcbiosinfo.bin-type := raw +smcbiosinfo.bin-compression := none + +$(SMCBIOSINFOTOOL): util/smc/smcbiosinfo/smcbiosinfo.c + printf " MAKE Creating SMCBIOSINFO tool\n" + $(MAKE) -C util/smc/smcbiosinfo + +$(obj)/mainboard/$(MAINBOARDDIR)/smcbiosinfo.bin: util/smc/smcbiosinfo/smcbiosinfo + printf " TOOL Creating SMC BIOSINFO metadata\n" + $(SMCBIOSINFOTOOL) -b $(CONFIG_SUPERMICRO_BOARDID) -o $(top)/$@ +endif +endif diff --git a/util/smc/smcbiosinfo/Makefile b/util/smc/smcbiosinfo/Makefile new file mode 100644 index 0000000..a0901bb --- /dev/null +++ b/util/smc/smcbiosinfo/Makefile @@ -0,0 +1,9 @@ +HOSTCC ?= cc + +smcbiosinfo: smcbiosinfo.c + $(HOSTCC) smcbiosinfo.c -I$(top)/$(obj)/ -o smcbiosinfo + +all: smcbiosinfo + +clean: + @rm -f smcbiosinfo diff --git a/util/smc/smcbiosinfo/description.md b/util/smc/smcbiosinfo/description.md new file mode 100644 index 0000000..21170eb --- /dev/null +++ b/util/smc/smcbiosinfo/description.md @@ -0,0 +1 @@ +Generates SMC biosinfo for BMC BIOS updates `C` diff --git a/util/smc/smcbiosinfo/smcbiosinfo.c b/util/smc/smcbiosinfo/smcbiosinfo.c new file mode 100644 index 0000000..a892b19 --- /dev/null +++ b/util/smc/smcbiosinfo/smcbiosinfo.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <stdint.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <getopt.h> +#include <errno.h> +#include <stdarg.h> +#include "build.h" + +/* Place the following struct somewhere in the ROM: */ +struct SMC_BIOS_Update { + uint32_t magic0; // always 0xaa00b1ed + char magic1[4]; // always $FID + uint16_t magic2; // always 0x7804 + uint8_t space0; // always zero + // SMCinfotool doesn't care for the first letter + // The BMC webinterface does + char boardid[9]; // "100000000" + uint8_t space1[15]; // unknown data + uint8_t space2; // always 0x1f + char ukn_majorVer[2]; + uint8_t space3; // always zero + char ukn_minorVer[2]; + uint8_t space4; // always zero + char majorVer[3]; + char minorVer[2]; + uint8_t space5; // always zero + uint16_t year; + uint8_t month; + uint8_t day; + uint32_t space6; // unknown data + uint8_t space7; // all ones + char str[15]; // "SUPERMSMCI--MB1" + uint8_t space8[3]; // always zero + uint64_t space9[6]; // all ones +} __packed; + +// Unused values: CDEPqR +static const char *optstring = "o:b:h"; + +static struct option long_options[] = { + {"output", required_argument, 0, 'o' }, + {"boardid", required_argument, 0, 'b' }, + {"help", no_argument, 0, 'h' }, +}; + +static void usage(void) +{ + printf("smcbiosinfo: Create BIOSInfo for BMC BIOS updates\n"); + printf("Usage: smcbiosinfo [options] -b <boardid> -o <filename>\n"); + printf("-o | --output <FILE> The file to generate\n"); + printf("-b | --boardid <id> The board ID\n"); + printf("-h | --help Print this help\n"); +} + +static int bcd2int(int hex) +{ + return ((hex & 0xF0) >> 4) * 10 + (hex & 0x0F); +} + +int main(int argc, char **argv) +{ + int c; + int ret = 0; + char *boardid = NULL; + char *filename = NULL; + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case 'o': + filename = strdup(optarg); + break; + case 'b': + boardid = strdup(optarg); + break; + case 'h': + usage(); + goto out; + default: + break; + } + } + if (!filename) { + fprintf(stderr, "E: Must specify a destination filename\n"); + ret = 1; + goto out; + } + + if (!boardid) { + fprintf(stderr, "E: Must specify a board ID\n"); + ret = 1; + goto out; + } else if (strlen(boardid) > 8) { + fprintf(stderr, "E: Board ID must be less than 8 characters\n"); + ret = 1; + goto out; + } + + // generate the table + + struct SMC_BIOS_Update sbu = { + 0xaa00b1ed, + "$FID", + 0x7804, + 0, // space + "100000000", //boardid + {}, // unknown data + 0x1f, // space + "05", + 0, // zero + "06", + 0, // zero + "000", // major, MSB first + "00", // minor + 0, // zero + bcd2int(COREBOOT_BUILD_YEAR_BCD) + 2000, // year + bcd2int(COREBOOT_BUILD_MONTH_BCD), // month + bcd2int(COREBOOT_BUILD_DAY_BCD), //day + 0, // zero + 0xff, // space + "SUPERMSMCI--MB1", + {0, 0, 0}, // all zero + {~0, ~0, ~0, ~0, ~0, ~0}, // all ones + }; + + if (COREBOOT_MAJOR_VERSION < 999) { + char tmp[4]; + snprintf(tmp, sizeof(tmp), "%03d", COREBOOT_MAJOR_VERSION); + memcpy(&sbu.majorVer, &tmp, sizeof(sbu.majorVer)); + } else { + fprintf(stderr, "E: Unsupported coreboot major version\n"); + ret = 1; + goto out; + } + + if (COREBOOT_MINOR_VERSION < 99) { + char tmp[3]; + snprintf(tmp, sizeof(tmp), "%02d", COREBOOT_MINOR_VERSION); + memcpy(&sbu.minorVer, &tmp, sizeof(sbu.minorVer)); + } else { + fprintf(stderr, "E: Unsupported coreboot minor version\n"); + ret = 1; + goto out; + } + memcpy(&sbu.boardid[1], boardid, strlen(boardid)); + + // write the table + + FILE *fd = fopen(filename, "wb"); + + if (!fd) { + fprintf(stderr, "%s open failed: %s\n", filename, strerror(errno)); + ret = 1; + goto out; + } + + if (fwrite(&sbu, 1, sizeof(sbu), fd) != sizeof(sbu)) { + fprintf(stderr, "%s write failed: %s\n", filename, strerror(errno)); + fclose(fd); + ret = 1; + goto out; + } + + if (fclose(fd)) { + fprintf(stderr, "%s close failed: %s\n", filename, strerror(errno)); + ret = 1; + goto out; + } + +out: + if (boardid) + free(boardid); + if (filename) + free(filename); + + return ret; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Gerrit-Change-Number: 35484 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1'
by HAOUAS Elyes (Code Review) 05 Jan '20

05 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34092 ) Change subject: ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1' ...................................................................... ec/lenovo/pmh7: Fix error: conversion from 'int' to 'signed char:1' Change-Id: Ie6c5a424ff49a2df586432e1390d5a30166d6c6a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/lenovo/pmh7/chip.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34092/1 diff --git a/src/ec/lenovo/pmh7/chip.h b/src/ec/lenovo/pmh7/chip.h index 46f74c1..3189767 100644 --- a/src/ec/lenovo/pmh7/chip.h +++ b/src/ec/lenovo/pmh7/chip.h @@ -17,8 +17,8 @@ #define EC_LENOVO_PMH7_CHIP_H struct ec_lenovo_pmh7_config { - int backlight_enable:1; - int dock_event_enable:1; + signed char backlight_enable:1; + signed char dock_event_enable:1; }; #endif /* EC_LENOVO_PMH7_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6c5a424ff49a2df586432e1390d5a30166d6c6a Gerrit-Change-Number: 34092 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 16

Change in ...coreboot[master]: src/device/pci: Add support for discrete VGA initialization and OpROM...
by mikeb mikeb (Code Review) 05 Jan '20

05 Jan '20

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31448 to review the following change. Change subject: src/device/pci: Add support for discrete VGA initialization and OpROM loading ...................................................................... src/device/pci: Add support for discrete VGA initialization and OpROM loading Required to make the discrete VGA working at some boards like AMD Lenovo G505S. If CONFIG_MULTIPLE_VGA_ADAPTERS is enabled, coreboot will try to initialize the discrete VGA and load OpROM on it. ACPI VFCT table will be created only for discrete VGA instead of integrated, but everything seems to be working fine. Maybe later we would find a way to make a common VFCT table for both adapters. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: If3269a0911e86ea07014484365c7c830485e52ec --- M src/device/pci_device.c M src/device/pci_rom.c 2 files changed, 68 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31448/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 82033a6..96dec0b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -764,7 +764,9 @@ * ROMs when coming out of an S3 resume. */ if (!IS_ENABLED(CONFIG_S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && - ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) + (((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) || + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) && + ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER)))) return 0; if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return 1; @@ -778,25 +780,41 @@ void pci_dev_init(struct device *dev) { struct rom_header *rom, *ram; + unsigned int pci_class = (dev->class >> 8); if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + /* Only load VGA ROMs. */ + if (pci_class != PCI_CLASS_DISPLAY_VGA) { + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + return; + } else if (pci_class != PCI_CLASS_DISPLAY_OTHER) { + return; + } + } if (!should_load_oprom(dev)) return; timestamp_add_now(TS_OPROM_INITIALIZE); rom = pci_rom_probe(dev); - if (rom == NULL) + if (rom == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM probe failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM probe failed\n"); return; + } ram = pci_rom_load(dev, rom); - if (ram == NULL) + if (ram == NULL) { + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA ROM load failed\n"); + else + printk(BIOS_DEBUG, "Discrete VGA ROM load failed\n"); return; + } timestamp_add_now(TS_OPROM_COPY_END); if (!should_run_oprom(dev)) @@ -804,7 +822,11 @@ run_bios(dev, (unsigned long)ram); gfx_set_init_done(1); - printk(BIOS_DEBUG, "VGA Option ROM was run\n"); + if (pci_class == PCI_CLASS_DISPLAY_VGA) + printk(BIOS_DEBUG, "Integrated VGA Option ROM was run\n"); + else + printk(BIOS_DEBUG, "Discrete VGA Option ROM was run\n"); + timestamp_add_now(TS_OPROM_END); } diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 82d9a30..60f9aed 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -179,13 +179,24 @@ /* VBIOS may be modified after oprom init so use the copy if present. */ static struct rom_header *check_initialized(struct device *dev) { - struct rom_header *run_rom; + struct rom_header *run_rom = NULL; struct pci_data *rom_data; if (!IS_ENABLED(CONFIG_VGA_ROM_RUN)) return NULL; - run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + /* Set the start of shadow memory for this Integrated or Discrete VGA. */ + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { + run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + } else if (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + run_rom = (struct rom_header *)(uintptr_t)PCI_RAM_IMAGE_START; + } + } + + if (run_rom == NULL) + return NULL; + if (read_le16(&run_rom->signature) != PCI_ROM_HDR) return NULL; @@ -217,11 +228,22 @@ return current; } - printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + /* Copy Integrated VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", rom == (struct rom_header *) (uintptr_t)PCI_VGA_RAM_IMAGE_START ? "initialized " : "", rom); + } else { + /* Copy Discrete VGA VBIOS from CBFS to ACPI VFCT. */ + printk(BIOS_DEBUG, " Copying %sVBIOS image from %p\n", + rom == (struct rom_header *) + (uintptr_t)PCI_RAM_IMAGE_START ? + "initialized " : "", + rom); + /* TODO: do this also for Integrated VGA VBIOS. */ + } header->DeviceID = device->device; header->VendorID = device->vendor; @@ -243,8 +265,20 @@ struct rom_header *rom; /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) - return current; + + if (!IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)) { + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) { + return current; + } + } else { + /* Write ACPI VFCT only for Discrete VGA. */ + if ((device->class >> 8) == PCI_CLASS_DISPLAY_OTHER) { + ; + } else { + return current; + } + /* TODO: do this also for Integrated VGA. */ + } /* Only handle enabled devices */ if (!device->enabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/31448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3269a0911e86ea07014484365c7c830485e52ec Gerrit-Change-Number: 31448 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

7 53

Change in coreboot[master]: mainboard/google: Allow Hatch variants to read SPD data over SMBus
by Edward O'Callaghan (Code Review) 02 Jan '20

02 Jan '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36449 ) Change subject: mainboard/google: Allow Hatch variants to read SPD data over SMBus ...................................................................... mainboard/google: Allow Hatch variants to read SPD data over SMBus All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Makefile.inc A src/mainboard/google/hatch/romstage_spd_smbus.c 3 files changed, 63 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36449/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 219be22..e339693 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -60,7 +60,11 @@ config ROMSTAGE_SPD_CBFS bool - default y + default y if !ROMSTAGE_SPD_SMBUS + +config ROMSTAGE_SPD_SMBUS + bool + default n config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 3ed82e7..0740c08 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c +romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c new file mode 100644 index 0000000..245b61d --- /dev/null +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/gpio.h> +#include <spd_bin.h> +#include <gpio.h> + +/* + * GPIO_MEM_CH_SEL is set to 1 for single channel skus + * and 0 for dual channel skus. + */ +#define GPIO_MEM_CH_SEL GPP_F2 + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + int is_single_ch_mem; + struct cnl_mb_cfg memcfg; + variant_memory_params(&memcfg); + + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + memcfg.dq_pins_interleaved = 1; + get_spd_smbus(&blk); + memcfg.spd[0].read_type = READ_SMBUS; + memcfg.spd[0].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[0]; + if (!is_single_ch_mem) { + memcfg.spd[1].read_type = READ_SMBUS; + memcfg.spd[1].spd_spec.spd_smbus_address = (uintptr_t)blk.spd_array[1]; + } + dump_spd_info(&blk); + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Gerrit-Change-Number: 36449 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: RFC) src/acpi: Update license headers to SPDX
by Martin Roth (Code Review) 02 Jan '20

02 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36176 ) Change subject: RFC) src/acpi: Update license headers to SPDX ...................................................................... RFC) src/acpi: Update license headers to SPDX While I was working on updating the headers to move copyrights into the AUTHORS file, I got a request to switch to SPDX headers as well. Linux has moved completely to SPDX headers, which are easier to maintain, have good definitions, are very short, and can be checked automatically. This is completely unlike our current header situation. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3 --- M src/acpi/Kconfig M src/acpi/Makefile.inc M src/acpi/sata.c M src/acpi/sata.h 4 files changed, 9 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/36176/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 72cfff5..3c6aeb1 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config ACPI_SATA_GENERATOR bool diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 53ac679..7c2092d 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -1 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. + ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c index d7fcbd6..ae43e7d 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +/* This file is part of the coreboot project. */ #include "sata.h" diff --git a/src/acpi/sata.h b/src/acpi/sata.h index fecf4c6..04cd80c 100644 --- a/src/acpi/sata.h +++ b/src/acpi/sata.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +/* This file is part of the coreboot project. */ #ifndef __ACPI_SATA_H__ #define __ACPI_SATA_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/36176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3 Gerrit-Change-Number: 36176 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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