coreboot-gerrit August 2018

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Change in coreboot[master]: mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device
by Crystal Lin (Code Review) 30 Aug '18

30 Aug '18

Crystal Lin has uploaded this change for review. ( https://review.coreboot.org/28398 Change subject: mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device ...................................................................... mainboard/google/kahlee/var/liara: Enable Synaptics touchpad device Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/variants/liara/devicetree.cb 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28398/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index bde91a1..9180906 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -20,6 +20,7 @@ select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index b330ec5..b41cd2a 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -134,6 +134,15 @@ register "wake" = "7" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end device mmio 0xfedc5000 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/28398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Gerrit-Change-Number: 28398 Gerrit-PatchSet: 1 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com>

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Change in coreboot[master]: google/grunt: Update Audio/H1/TP i2c timings
by Chris Zhou (Code Review) 30 Aug '18

30 Aug '18

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/28397 Change subject: google/grunt: Update Audio/H1/TP i2c timings ...................................................................... google/grunt: Update Audio/H1/TP i2c timings After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/28397/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index b330ec5..cf6dd5f 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -24,7 +24,7 @@ # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 95, + .rise_time_ns = 85, .fall_time_ns = 3, }" @@ -32,15 +32,15 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, + .rise_time_ns = 45, .fall_time_ns = 4, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, + .rise_time_ns = 48, + .fall_time_ns = 37, }" # Enable I2C3 for touchscreen at 400kHz -- To view, visit https://review.coreboot.org/28397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Gerrit-Change-Number: 28397 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com>

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Change in coreboot[master]: riscv: add entry assembly file for RAMSTAGE
by Xiang Wang (Code Review) 30 Aug '18

30 Aug '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28384 to look at the new patch set (#3). Change subject: riscv: add entry assembly file for RAMSTAGE ...................................................................... riscv: add entry assembly file for RAMSTAGE RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/assembly_entry.S M src/arch/riscv/include/arch/header.ld 3 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/3 -- To view, visit https://review.coreboot.org/28384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Gerrit-Change-Number: 28384 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28096 ) Change subject: riscv: add support for supervisor binary interface (SBI) ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/#/c/28096/13/src/arch/riscv/sbi.c File src/arch/riscv/sbi.c: https://review.coreboot.org/#/c/28096/13/src/arch/riscv/sbi.c@30 PS13, Line 30: printk(BIOS_ERR, "Please implement the function %s on your platform.", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/28096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Gerrit-Change-Number: 28096 Gerrit-PatchSet: 13 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Thu, 30 Aug 2018 07:50:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [Please test]nb/intel/i945/raminit: "Correct" DRTST
by Elyes HAOUAS (Code Review) 30 Aug '18

30 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28396 Change subject: [Please test]nb/intel/i945/raminit: "Correct" DRTST ...................................................................... [Please test]nb/intel/i945/raminit: "Correct" DRTST Tested on 945G-M4, it now boot even if channel 0 is not populated at all. Could you test if i945 laptop version will boot if DIMM0 is not populated? Change-Id: I0d3229b842808d0920e25dcefe49eaceb8e10cdc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28396/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530..af741d5 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1150,23 +1150,7 @@ asm volatile ("nop; nop;" ::: "memory"); - reg32 = MCHBAR32(DRTST); - - /* Is channel 0 populated? */ - if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - reg32 |= (1 << 7) | (1 << 5); - else - reg32 |= (1 << 31); - - /* Is channel 1 populated? */ - if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || - sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - reg32 |= (1 << 9) | (1 << 8); - else - reg32 |= (1 << 30); - - MCHBAR32(DRTST) = reg32; + MCHBAR32(DRTST) |= (1 << 7) | (1 << 5); /* Activate DRAM Channel IO Buffers */ if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || -- To view, visit https://review.coreboot.org/28396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0d3229b842808d0920e25dcefe49eaceb8e10cdc Gerrit-Change-Number: 28396 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 21: (2 comments) https://review.coreboot.org/#/c/27972/21/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/21/src/arch/riscv/misaligend.c@142 PS21, Line 142: for(i = 0; i < ARRAY_SIZE (insn_info); i++) space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/27972/21/src/arch/riscv/misaligend.c@142 PS21, Line 142: for(i = 0; i < ARRAY_SIZE (insn_info); i++) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 21 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Thu, 30 Aug 2018 07:34:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 20: (5 comments) https://review.coreboot.org/#/c/27972/20/src/arch/riscv/fp_asm.S File src/arch/riscv/fp_asm.S: https://review.coreboot.org/#/c/27972/20/src/arch/riscv/fp_asm.S@27 PS20, Line 27: /* trailing whitespace https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@45 PS20, Line 45: /* opcode/mask used to identify instruction, trailing whitespace https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@47 PS20, Line 47: uint32_t opcode; trailing whitespace https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@142 PS20, Line 142: for(i = 0; i < ARRAY_SIZE(insn_info); i++) space required before the open parenthesis '(' https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@143 PS20, Line 143: if((insn_info[i].mask & insn) == insn_info[i].opcode) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 20 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Thu, 30 Aug 2018 07:28:48 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/i945: Correct SLP_S4# comment
by Elyes HAOUAS (Code Review) 30 Aug '18

30 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28395 Change subject: nb/intel/i945: Correct SLP_S4# comment ...................................................................... nb/intel/i945: Correct SLP_S4# comment Bit #3 of GEN_PMCON_3 register will enable SLP_S4# Assertion Stretch. Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28395/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530..c22d4eb 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -265,7 +265,7 @@ do_reset = 1; } - /* Set SLP_S3# Assertion Stretch Enable */ + /* Set SLP_S4# Assertion Stretch Enable */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ reg8 |= (1 << 3); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); -- To view, visit https://review.coreboot.org/28395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0 Gerrit-Change-Number: 28395 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28096 ) Change subject: riscv: add support for supervisor binary interface (SBI) ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/28096/11/src/arch/riscv/sbi.c File src/arch/riscv/sbi.c: https://review.coreboot.org/#/c/28096/11/src/arch/riscv/sbi.c@30 PS11, Line 30: die("Please implement the set_msip function on your platform."); Prefer using '"%s...", __func__' to using 'set_msip', this function's name, in a string -- To view, visit https://review.coreboot.org/28096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Gerrit-Change-Number: 28096 Gerrit-PatchSet: 11 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Thu, 30 Aug 2018 06:40:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 30 Aug '18

30 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/28380/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28380/7//COMMIT_MSG@29 PS7, Line 29: - nouveau driver unloading (`rmmod` or `modprobe -r`) does not work well: it Can you test if it does work without the optimus patch? I could imagine it's related to missing ACPI _BCM, _BCL, _BQC. Have a look at drivers_intel_gma_displays_ssdt_generate() for Intel GMA. https://review.coreboot.org/#/c/28380/7//COMMIT_MSG@41 PS7, Line 41: - VGA ROM for Nvidia GPU is not loaded from BIOS (i.e. coreboot). Need Should work with pciXXXX,YYYY.rom in CBFS. You can use acpi_dump to read it in chunks from generated _ROM. -- To view, visit https://review.coreboot.org/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 7 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 06:28:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018