coreboot-gerrit August 2018

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20472 ) Change subject: nb/intel/sandybridge/peg: Add PEG driver ...................................................................... Patch Set 7: (10 comments) https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… File src/northbridge/intel/sandybridge/pcie.c: https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 52: static void pcie_programm_da0(device_t dev, u8 val) 'programm' may be misspelled - perhaps 'program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 97: static void pcie_programm_90x(device_t dev, u8 bundle, u8 a, u8 b) 'programm' may be misspelled - perhaps 'program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 128: /* Programm test values */ 'Programm' may be misspelled - perhaps 'Program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 129: pcie_programm_90x(dev, bundle, a[i], i); 'programm' may be misspelled - perhaps 'program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 138: /* No errors occured after 100msec ? */ 'occured' may be misspelled - perhaps 'occurred'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 177: for (bundle = 0; bundle < end_bundle; bundle ++) { space prohibited before that '++' (ctx:WxB) https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 190: /* Programm 0xda0 */ 'Programm' may be misspelled - perhaps 'Program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 191: pcie_programm_da0(dev, reg_da0[i]); 'programm' may be misspelled - perhaps 'program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 226: /* Programm 0xda0 */ 'Programm' may be misspelled - perhaps 'Program'? https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/p… PS7, Line 227: pcie_programm_da0(dev, reg_da0[best_da0]); 'programm' may be misspelled - perhaps 'program'? -- To view, visit https://review.coreboot.org/20472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f Gerrit-Change-Number: 20472 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 14:44:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by Xiang Wang (Code Review) 30 Aug '18

30 Aug '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28394 to look at the new patch set (#3). Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page Must to set MXR, when needs to read the page which is execution-only. So make this change. Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/vm.h 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28394/3 -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by build bot (Jenkins) (Code Review) 30 Aug '18

30 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28394 ) Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/28394/2/src/arch/riscv/include/vm.h File src/arch/riscv/include/vm.h: https://review.coreboot.org/#/c/28394/2/src/arch/riscv/include/vm.h@57 PS2, Line 57: DEFINE_MPRV_READ_FLAGS(name, type, insn, MSTATUS_MPRV) please, no spaces at the start of a line https://review.coreboot.org/#/c/28394/2/src/arch/riscv/include/vm.h@60 PS2, Line 60: DEFINE_MPRV_READ_FLAGS(name, type, insn, MSTATUS_MPRV | MSTATUS_MXR) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 13:34:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by Xiang Wang (Code Review) 30 Aug '18

30 Aug '18

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/28394 ) Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28394/1/src/arch/riscv/include/vm.h File src/arch/riscv/include/vm.h: https://review.coreboot.org/#/c/28394/1/src/arch/riscv/include/vm.h@41 PS1, Line 41: #define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \ > I suggest the following: […] Done -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 13:34:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
by Xiang Wang (Code Review) 30 Aug '18

30 Aug '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28394 to look at the new patch set (#2). Change subject: riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page ...................................................................... riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page Must to set MXR, when needs to read the page which is execution-only. So make this change. Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/vm.h 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28394/2 -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1
by Zhuohao Lee (Code Review) 30 Aug '18

30 Aug '18

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/28400 Change subject: mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1 ...................................................................... mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1 This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28400/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 1645451..df59c5e 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -196,6 +196,7 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_MAX98927 select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI select MAINBOARD_HAS_SPI_TPM_CR50 config VARIANT_SPECIFIC_OPTIONS_SORAKA -- To view, visit https://review.coreboot.org/28400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Gerrit-Change-Number: 28400 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org>

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Change in coreboot[master]: riscv: Fix the definition of DEFINE_MPRV_READ
by Jonathan Neuschäfer (Code Review) 30 Aug '18

30 Aug '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28394 ) Change subject: riscv: Fix the definition of DEFINE_MPRV_READ ...................................................................... Patch Set 1: Code-Review-1 (2 comments) I think the commit in its current form creates a (security) problem https://review.coreboot.org/#/c/28394/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28394/1//COMMIT_MSG@10 PS1, Line 10: So make this change. As far as I understand it, unprivileged code could use this to read from execute-only pages by reading at misaligned addresses and triggering the misaligned memory access handler. To avoid this problem, MXR should probably only be used to read instructions, but not to read data. https://review.coreboot.org/#/c/28394/1/src/arch/riscv/include/vm.h File src/arch/riscv/include/vm.h: https://review.coreboot.org/#/c/28394/1/src/arch/riscv/include/vm.h@41 PS1, Line 41: #define DEFINE_MPRV_READ(name, type, insn) \ I suggest the following: - Rename DEFINE_MPRV_READ to DEFINE_MPRV_READ_FLAGS and add an extra parameter called "flags" which is OR'd to the mprv variable in the definition. - #define DEFINE_MPRV_READ(name, type, insn) DEFINE_MPRV_READ_FLAGS(name, type, insn, 0) - #define DEFINE_MPRV_READ_MXR(name, type, insn) DEFINE_MPRV_READ_FLAGS(name, type, insn, MSTATUS_MXR) - Add a separate MXR-enabled read function for bytes. -- To view, visit https://review.coreboot.org/28394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Gerrit-Change-Number: 28394 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 12:07:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: separately define stack locations at different stages
by Jonathan Neuschäfer (Code Review) 30 Aug '18

30 Aug '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28383 ) Change subject: riscv: separately define stack locations at different stages ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Looks good to me, I'm not 100% familiar with memlayout files https://review.coreboot.org/#/c/28383/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28383/1//COMMIT_MSG@9 PS1, Line 9: BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begin "When RAMSTAGE begins ..." -- To view, visit https://review.coreboot.org/28383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Gerrit-Change-Number: 28383 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 11:58:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Correct number of root ports for CNL PCH H
by Maulik V Vaghela (Code Review) 30 Aug '18

30 Aug '18

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/28399 Change subject: soc/intel/cannonlake: Correct number of root ports for CNL PCH H ...................................................................... soc/intel/cannonlake: Correct number of root ports for CNL PCH H As per EDS#571182, maximum 24 root ports are supported for CNL PCH H. Change-Id: I2cc3ae282d4eb5da8b0618451e062a6c061f1d6f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28399/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ef39706..310ed24 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -164,6 +164,7 @@ config MAX_ROOT_PORTS int + default 24 if CANNONLAKE_SOC_PCH_H default 16 config SMM_TSEG_SIZE -- To view, visit https://review.coreboot.org/28399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2cc3ae282d4eb5da8b0618451e062a6c061f1d6f Gerrit-Change-Number: 28399 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>

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Change in coreboot[master]: riscv: update mtime initialize
by Jonathan Neuschäfer (Code Review) 30 Aug '18

30 Aug '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28372 ) Change subject: riscv: update mtime initialize ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Thanks. https://review.coreboot.org/#/c/28372/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28372/1//COMMIT_MSG@7 PS1, Line 7: riscv: update mtime initialize riscv: update mtime initialization https://review.coreboot.org/#/c/28372/1/src/arch/riscv/mcall.c File src/arch/riscv/mcall.c: https://review.coreboot.org/#/c/28372/1/src/arch/riscv/mcall.c@40 PS1, Line 40: void mtime_init(void); This function should also be declared in a header, so that SoC code can include that header and get type-checking for mtime_init. https://review.coreboot.org/#/c/28372/1/src/arch/riscv/mcall.c@43 PS1, Line 43: __weak void mtime_init(void) { } Consider adding a warning/error/die() message, for cases when this dummy implementation is called. https://review.coreboot.org/#/c/28372/1/src/soc/sifive/fu540/Makefile.inc File src/soc/sifive/fu540/Makefile.inc: https://review.coreboot.org/#/c/28372/1/src/soc/sifive/fu540/Makefile.inc@19 PS1, Line 19: bootblock-y += clint.c clint.c is not added in this commit -- To view, visit https://review.coreboot.org/28372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Gerrit-Change-Number: 28372 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 30 Aug 2018 09:53:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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coreboot-gerrit August 2018